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1. 发明授权

US06989563B1 Flash memory cell with UV protective layer 有权
标题翻译：具有UV保护层的闪存单元
公开(公告)号：US06989563B1
公开(公告)日：2006-01-24
申请号：US10770260
申请日：2004-02-02
申请人： Krishnashree Achuthan , Patrick K. Cheung , Cyrus Tabery , Jean Y. Yang , Ning Cheng , Minh Van Ngo
发明人： Krishnashree Achuthan , Patrick K. Cheung , Cyrus Tabery , Jean Y. Yang , Ning Cheng , Minh Van Ngo
IPC分类号： H01L29/788
CPC分类号： H01L29/7923 , H01L23/53295 , H01L23/552 , H01L29/66833 , H01L2924/0002 , H01L2924/00
摘要： A method of protecting a charge trapping dielectric flash memory cell from UV-induced charging, including fabricating a charge trapping dielectric flash memory cell in a semiconductor device; depositing and planarizing an interlevel dielectric layer over the charge trapping dielectric flash memory cell and depositing over the planarized interlevel dielectric layer at least one UV-protective layer, the UV-protective layer including a substantially UV-opaque material.
摘要翻译：一种保护电荷捕获电介质闪速存储器单元免受UV感应充电的方法，包括在半导体器件中制造电荷俘获电介质闪存单元; 在电荷俘获电介质闪存单元上沉积和平坦化层间电介质层，并在平坦化的层间电介质层上沉积至少一个UV保护层，UV保护层包括基本上不透紫外线的材料。

2. 发明授权

US06933219B1 Tightly spaced gate formation through damascene process 有权
标题翻译：通过镶嵌工艺紧密间隔的浇口形成
公开(公告)号：US06933219B1
公开(公告)日：2005-08-23
申请号：US10716209
申请日：2003-11-18
申请人： Emmanuil H. Lingunis , Krishnashree Achuthan , Minh Van Ngo , Cyrus Tabery , Jean Y. Yang
发明人： Emmanuil H. Lingunis , Krishnashree Achuthan , Minh Van Ngo , Cyrus Tabery , Jean Y. Yang
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/4763 , H01L21/8246 , H01L27/115
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115 , H01L29/66583
摘要： The invention includes an apparatus and a method of manufacturing such apparatus using a damascene process. The method includes the step of patterning a layer disposed over a substrate to include a line and space pattern. The line and space pattern in the layer includes at least one space comprising a width dimension of a feature to be formed. The feature may be, e.g., a wordline(s)/gate electrode(s). Additionally, the sidewalls of the feature, e.g., the wordline(s)/gate electrode(s) include relatively smooth surfaces.
摘要翻译：本发明包括使用镶嵌工艺制造这种装置的装置和方法。该方法包括图案化设置在衬底上的层以包括线和空间图案的步骤。层中的线和空间图案包括至少一个包含要形成的特征的宽度尺寸的空间。该特征可以是例如字线/栅极电极。另外，特征的侧壁，例如字线/栅电极包括相对光滑的表面。

3. 发明授权

US07091088B1 UV-blocking etch stop layer for reducing UV-induced charging of charge storage layer in memory devices in BEOL processing 有权
标题翻译：用于减少BEOL处理中的存储器件中的电荷存储层的UV诱导的充电的UV阻挡蚀刻停止层
公开(公告)号：US07091088B1
公开(公告)日：2006-08-15
申请号：US10861437
申请日：2004-06-03
申请人： Ning Cheng , Clarence B. Ferguson , Emmanuil H. Lingunis , Minh Van Ngo , Joerg Reiss , Jean Y. Yang , Jeffrey A. Shields , Cyrus Tabery
发明人： Ning Cheng , Clarence B. Ferguson , Emmanuil H. Lingunis , Minh Van Ngo , Joerg Reiss , Jean Y. Yang , Jeffrey A. Shields , Cyrus Tabery
IPC分类号： H01L21/336
CPC分类号： H01L23/53295 , H01L21/76829 , H01L27/115 , H01L27/11568 , H01L2924/0002 , Y10S438/954 , H01L2924/00
摘要： A method of protecting a charge trapping dielectric flash memory cell from UV-induced charging, including fabricating a charge trapping dielectric flash memory cell in a semiconductor device; depositing over the charge trapping dielectric flash memory cell at least one UV-protective layer; forming at least one layer over the at least one UV-protective layer; and etching the at least one layer to form an opening therein with an etchant species selective to stop on a layer below the at least one UV-protective layer, wherein the UV-protective layer comprises a substantially UV-opaque material.
摘要翻译：一种保护电荷捕获电介质闪速存储器单元免受UV感应充电的方法，包括在半导体器件中制造电荷俘获电介质闪存单元; 在电荷捕获电介质闪存单元上沉积至少一个UV保护层; 在所述至少一个UV保护层上形成至少一层; 以及蚀刻所述至少一个层以在其中形成具有选择性地停留在所述至少一个UV保护层下方的层上的蚀刻剂物质的开口，其中所述UV保护层包括基本上不透紫外线的材料。

4. 发明授权

US06905971B1 Treatment of dielectric material to enhance etch rate 有权
标题翻译：处理电介质材料以提高蚀刻速率
公开(公告)号：US06905971B1
公开(公告)日：2005-06-14
申请号：US10331938
申请日：2002-12-30
申请人： Cyrus Tabery , Chih-Yuh Yang , William G. En , Joong S. Jeon , Minh Van Ngo , Ming-Ren Lin
发明人： Cyrus Tabery , Chih-Yuh Yang , William G. En , Joong S. Jeon , Minh Van Ngo , Ming-Ren Lin
IPC分类号： H01L21/302 , H01L21/311 , H01L21/461
CPC分类号： H01L21/31116 , H01L21/31122
摘要： In one embodiment, the present invention relates to a method for pre-treating and etching a dielectric layer in a semiconductor device comprising the steps of: (A) pre-treating one or more exposed portions of a dielectric layer with a plasma in a plasma etching tool to increase removal rate of the one or more exposed portions upon etching; and (B) removing the one or more exposed portions of the dielectric layer in the same plasma etching tool of step (A) via plasma etching.
摘要翻译：在一个实施例中，本发明涉及一种用于在半导体器件中预处理和蚀刻电介质层的方法，包括以下步骤：（A）用等离子体中的等离子体预处理介电层的一个或多个暴露部分蚀刻工具，以在蚀刻时增加一个或多个暴露部分的去除速率; 和（B）通过等离子体蚀刻在步骤（A）的相同等离子体蚀刻工具中去除介电层的一个或多个暴露部分。

5. 发明授权

US07018868B1 Disposable hard mask for memory bitline scaling 有权
标题翻译：用于存储器位线缩放的一次性硬掩模
公开(公告)号：US07018868B1
公开(公告)日：2006-03-28
申请号：US10770245
申请日：2004-02-02
申请人： Jean Y. Yang , Jeff P. Erhardt , Cyrus Tabery , Weidong Qian , Mark T. Ramsbey , Jaeyong Park , Tazrien Kamal
发明人： Jean Y. Yang , Jeff P. Erhardt , Cyrus Tabery , Weidong Qian , Mark T. Ramsbey , Jaeyong Park , Tazrien Kamal
IPC分类号： H01L21/44
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11568
摘要： The invention is a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes buried bitlines in a semiconductor substrate. Additionally, doped regions are formed adjacent the buried bitlines. The doped regions adjacent the buried bitlines inhibit a leakage current between the buried bitlines.
摘要翻译：本发明是半导体器件和半导体器件的制造方法。半导体器件包括在半导体衬底中的掩埋位线。此外，掺杂区域形成在掩埋位线附近。与掩埋位线相邻的掺杂区域可以防止掩埋位线之间的漏电流。

6. 发明授权

US07118967B1 Protection of charge trapping dielectric flash memory devices from UV-induced charging in BEOL processing 有权
标题翻译：保护电荷捕获电介质闪存器件免受BEOL处理中的紫外线引起的充电
公开(公告)号：US07118967B1
公开(公告)日：2006-10-10
申请号：US10368696
申请日：2003-02-19
申请人： Minh V. Ngo , Ning Cheng , Jeff P. Erhardt , Clarence B. Ferguson , Cyrus Tabery , John Caffall , Tyagamohan Gottipati , Dawn Hopper
发明人： Minh V. Ngo , Ning Cheng , Jeff P. Erhardt , Clarence B. Ferguson , Cyrus Tabery , John Caffall , Tyagamohan Gottipati , Dawn Hopper
IPC分类号： H01L21/336
CPC分类号： H01L29/7923 , H01L29/66833 , Y10S438/954
摘要： A method of protecting a charge trapping dielectric flash memory cell from UV-induced charging, including fabricating a charge trapping dielectric flash memory cell including a charge trapping dielectric charge storage layer in a semiconductor device; and during processing steps subsequent to formation of the charge trapping dielectric charge storage layer, protecting the charge trapping dielectric flash memory cell from exposure to a level of UV radiation sufficient to deposit a non-erasable charge in the charge trapping dielectric flash memory cell. In one embodiment, the step of protecting is carried out by selecting processes in BEOL fabrication which do not include use, generation or exposure of the semiconductor device to a level of UV radiation sufficient to deposit the non-erasable charge.
摘要翻译：一种保护电荷捕获电介质闪存单元免受UV感应充电的方法，包括在半导体器件中制造包括电荷捕获介电电荷存储层的电荷捕获电介质闪存单元; 并且在形成电荷捕获介电电荷存储层之后的处理步骤期间，保护电荷捕获电介质闪速存储器单元暴露于足以在电荷俘获电介质闪存单元中沉积不可擦除电荷的UV辐射水平。在一个实施例中，保护步骤是通过选择不包括半导体器件的使用，产生或曝光到足以沉积不可擦除电荷的紫外线辐射的水平的BEOL制造中的工艺进行的。

7. 发明授权

US06987048B1 Memory device having silicided bitlines and method of forming the same 有权
标题翻译：具有硅化位线的存储器件及其形成方法
公开(公告)号：US06987048B1
公开(公告)日：2006-01-17
申请号：US10635781
申请日：2003-08-06
申请人： Ning Cheng , Hiroyuki Kinoshita , Jeff P. Erhardt , Mark T. Ramsbey , Cyrus Tabery , Jean Yee-Mei Yang
发明人： Ning Cheng , Hiroyuki Kinoshita , Jeff P. Erhardt , Mark T. Ramsbey , Cyrus Tabery , Jean Yee-Mei Yang
IPC分类号： H01L21/8247
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11568 , Y10S438/954
摘要： A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate, a bottom dielectric, a charge storing layer, and a top dielectric in a stacked gate configuration. Silicided buried bitlines, which function as a source and a drain, are formed within the substrate. The silicided bitlines have a reduced resistance, which greatly reduces the number of bitline contacts necessary in an array of memory devices.
摘要翻译：提供了存储器件和制造方法。存储器件包括半导体衬底，底部电介质，电荷存储层和堆叠栅极配置中的顶部电介质。用作源极和漏极的硅化掩埋位线形成在衬底内。硅化的位线具有降低的电阻，这大大减少了存储器件阵列中所需的位线接触的数量。

8. 发明申请

US20050104091A1 Self aligned damascene gate 有权
标题翻译：自对准镶嵌门
公开(公告)号：US20050104091A1
公开(公告)日：2005-05-19
申请号：US10699887
申请日：2003-11-04
申请人： Cyrus Tabery , Shibly Ahmed , Matthew Buynoski , Srikanteswara Dakshina-Murthy , Zoran Krivokapic , Haihong Wang , Chih-Yuh Yang , Bin Yu
发明人： Cyrus Tabery , Shibly Ahmed , Matthew Buynoski , Srikanteswara Dakshina-Murthy , Zoran Krivokapic , Haihong Wang , Chih-Yuh Yang , Bin Yu
IPC分类号： H01L21/336 , H01L29/786 , H01L29/745
CPC分类号： H01L29/785 , H01L29/66818 , H01L29/7842
摘要： A method for forming a metal-oxide semiconductor field-effect transistor (MOSFET) includes patterning a fin area, a source region, and a drain region on a substrate, forming a fin in the fin area, and forming a mask in the fin area. The method further includes etching the mask to expose a channel area of the MOSFET, etching the fin to thin a width of the fin in the channel area, forming a gate over the fin, and forming contacts to the gate, the source region, and the drain region.
摘要翻译：一种形成金属氧化物半导体场效应晶体管（MOSFET）的方法包括在衬底上构图翅片区域，源极区域和漏极区域，在翅片区域中形成鳍片，并在鳍片区域中形成掩模。该方法还包括蚀刻掩模以暴露MOSFET的沟道区域，蚀刻鳍以在沟道区域中减薄翅片的宽度，在鳍上方形成栅极，以及形成与栅极，源区和漏极区域。

9. 发明授权

US06835662B1 Partially de-coupled core and periphery gate module process 有权
标题翻译：部分解耦核心和周边门模块工艺
公开(公告)号：US06835662B1
公开(公告)日：2004-12-28
申请号：US10619797
申请日：2003-07-14
申请人： Jeff P. Erhardt , Hiroyuki Kinoshita , Cyrus Tabery
发明人： Jeff P. Erhardt , Hiroyuki Kinoshita , Cyrus Tabery
IPC分类号： H01L21302
CPC分类号： H01L27/11568 , H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L27/1052 , H01L27/115
摘要： The invention is an apparatus and a method of manufacturing a structure. The method includes the step of patterning a layer to include a line and space pattern. A space of the line and space pattern in a first region includes a first critical dimension less than achievable at a resolution limit of lithography. A line of the line and space pattern in a second region includes a second critical dimension achievable at a resolution limit of lithography. A sidewall spacer is formed on a line from a masking layer used in the formation of the structure. The method uses one critical masking step and two non-critical masking steps.
摘要翻译：本发明是一种制造结构的装置和方法。该方法包括图案化层以包括线和空间图案的步骤。在第一区域中的线和空间图案的空间包括在光刻的分辨率极限下小于可实现的第一临界尺寸。第二区域中的线和空间图案的线包括在光刻的分辨率极限下可实现的第二临界尺寸。在用于形成结构的掩模层的一条线上形成侧壁间隔物。该方法使用一个关键的屏蔽步骤和两个非关键的屏蔽步骤。

10. 发明授权

US06995437B1 Semiconductor device with core and periphery regions 有权
标题翻译：具有核心和外围区域的半导体器件
公开(公告)号：US06995437B1
公开(公告)日：2006-02-07
申请号：US10869774
申请日：2004-06-16
申请人： Hiroyuki Kinoshita , Yu Sun , Basab Banerjee , Christopher M. Foster , John R. Behnke , Cyrus Tabery
发明人： Hiroyuki Kinoshita , Yu Sun , Basab Banerjee , Christopher M. Foster , John R. Behnke , Cyrus Tabery
IPC分类号： H01L31/119
CPC分类号： H01L27/105 , H01L27/11568 , H01L27/11573
摘要： A method for forming a semiconductor device that includes a line and space pattern with variable pitch and critical dimensions in a layer on a substrate. The substrate includes a first region (e.g., a core region) and a second region (e.g., a periphery region). A first sub-line and space pattern in the first region comprises a space of a dimension (A) less than achievable by lithographic processes alone. Further, a second sub-line and space pattern in the second region comprises at least one line including a second critical dimension (B) achievable by lithography. The method uses two critical masking steps to form a hard mask that includes in the core region a critical dimension (A) less than achievable at a resolution limit of lithography. Further, the method uses a single etch step to transfer the pattern of the hard mask to the layer.
摘要翻译：一种用于形成半导体器件的方法，其包括在衬底上的层中具有可变节距和临界尺寸的线和间隔图案。衬底包括第一区域（例如芯区域）和第二区域（例如，周边区域）。第一区域中的第一子线和空间图案包括尺寸（A）的空间小于单独通过光刻工艺可实现的尺寸。此外，第二区域中的第二子线和空间图案包括至少一条线，其包括通过光刻可实现的第二临界尺寸（B）。该方法使用两个关键的掩模步骤来形成硬掩模，其在芯部区域中包括小于在光刻的分辨率极限下可实现的临界尺寸（A）。此外，该方法使用单个蚀刻步骤将硬掩模的图案转移到该层。

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