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1. 发明授权

US08368219B2 Buried silicide local interconnect with sidewall spacers and method for making the same 有权
标题翻译：埋入硅化物与侧壁间隔物的局部互连及其制造方法
公开(公告)号：US08368219B2
公开(公告)日：2013-02-05
申请号：US13281491
申请日：2011-10-26
申请人： Arvind Halliyal , Zoran Krivokapic , Matthew S. Buynoski , Nicholas H. Tripsas , Minh Van Ngo , Mark T. Ramsbey , Jeffrey A. Shields , Jusuke Ogura
发明人： Arvind Halliyal , Zoran Krivokapic , Matthew S. Buynoski , Nicholas H. Tripsas , Minh Van Ngo , Mark T. Ramsbey , Jeffrey A. Shields , Jusuke Ogura
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L21/28518 , H01L21/743 , H01L21/76895
摘要： A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.
摘要翻译：掩埋的局部互连和形成相同对策的掺杂衬底的区域以形成反向隔离区的方法。硬掩模在掺杂的衬底上形成和图案化，其中凹陷通过图案化的硬掩模被蚀刻到反向掺杂的区域中。在凹槽的侧壁上形成有电介质隔离件，凹部底部的一部分露出。然后将金属沉积在凹部中并在凹部的底部反应形成硅化物。凹槽里填充有抛光的填充材料。然后去除硬掩模以形成硅化物掩埋的局部互连。

2. 发明授权

US08362569B2 Semiconductor device and semiconductor device fabrication method 有权
标题翻译：半导体器件和半导体器件制造方法
公开(公告)号：US08362569B2
公开(公告)日：2013-01-29
申请号：US12761516
申请日：2010-04-16
申请人： Tomoyuki Kirimura , Jusuke Ogura
发明人： Tomoyuki Kirimura , Jusuke Ogura
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823871 , H01L21/823807 , H01L29/7843
摘要： A semiconductor device fabrication method including: forming a gate conductor including a gate for a transistor in the first region, and a gate for a transistor in the second region, and a first film over a first stress film for covering the transistors; etching the first film from the second region by using a mask layer and etching the first film under the mask layer in the direction parallel to the surface of the semiconductor substrate by a first width from an edge of the first mask layer, and the first stress film from the second region; forming a second stress film covering the first stress film and the first film; etching the second stress film so that a portion of the second stress film overlaps a portion of the first stress film and a portion of the first film; and forming a contact hole connected with the gate conductor.
摘要翻译：一种半导体器件制造方法，包括：形成包括第一区域中的晶体管的栅极和第二区域中的晶体管的栅极的栅极导体，以及用于覆盖晶体管的第一应力膜上的第一膜; 通过使用掩模层从所述第二区域蚀刻所述第一膜，并且在所述掩模层的下面沿着与所述半导体衬底的表面平行的方向从所述第一掩模层的边缘以第一宽度蚀刻所述第一膜，并且所述第一应力第二区电影; 形成覆盖所述第一应力膜和所述第一膜的第二应力膜; 蚀刻第二应力膜，使得第二应力膜的一部分与第一应力膜的一部分和第一膜的一部分重叠; 并形成与栅极导体连接的接触孔。

3. 发明申请

US20120208342A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120208342A1
公开(公告)日：2012-08-16
申请号：US13455633
申请日：2012-04-25
申请人： Jusuke OGURA , Hikaru KOKURA , Hideyuki KOJIMA , Toru ANEZAKI , Hiroyuki OGAWA , Junichi ARIYOSHI
发明人： Jusuke OGURA , Hikaru KOKURA , Hideyuki KOJIMA , Toru ANEZAKI , Hiroyuki OGAWA , Junichi ARIYOSHI
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , H01L21/823481 , H01L27/1052 , H01L27/11521
摘要： A method of manufacturing a semiconductor device includes forming an isolation region defining an active region in a semiconductor substrate, forming a first insulating film over the semiconductor substrate, forming a second insulating film having etching properties different from those of the first insulating film over the first insulating film, selectively removing the second insulating film from a first region over the active region and the isolation region by dry etching using a fluorocarbon-based etching gas, removing a residual film formed by the dry etching over the first insulating film by exposure in an atmosphere containing oxygen, and selectively removing the first insulating film from the first region by wet etching.
摘要翻译：制造半导体器件的方法包括在半导体衬底中形成限定有源区的隔离区，在半导体衬底上形成第一绝缘膜，形成第二绝缘膜，该第二绝缘膜具有与第一绝缘膜相同的蚀刻性能绝缘膜，通过使用基于碳氟化合物的蚀刻气体的干蚀刻从有源区域和隔离区域上的第一区域选择性地去除第二绝缘膜，通过在第一绝缘膜上暴露于第一绝缘膜上形成的残留膜含氧的气氛，通过湿式蚀刻从第一区域选择性地除去第一绝缘膜。

4. 发明授权

US08049334B1 Buried silicide local interconnect with sidewall spacers and method for making the same 有权
标题翻译：埋入硅化物与侧壁间隔物的局部互连及其制造方法
公开(公告)号：US08049334B1
公开(公告)日：2011-11-01
申请号：US12843131
申请日：2010-07-26
申请人： Arvind Halliyal , Zoran Krivokapic , Matthew S. Buynoski , Nicholas H. Tripsas , Minh Van Ngo , Mark T. Ramsbey , Jeffrey A. Shields , Jusuke Ogura
发明人： Arvind Halliyal , Zoran Krivokapic , Matthew S. Buynoski , Nicholas H. Tripsas , Minh Van Ngo , Mark T. Ramsbey , Jeffrey A. Shields , Jusuke Ogura
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L21/28518 , H01L21/743 , H01L21/76895
摘要： A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.
摘要翻译：掩埋的局部互连和形成相同对策的掺杂衬底的区域以形成反向隔离区的方法。硬掩模在掺杂的衬底上形成和图案化，其中凹陷通过图案化的硬掩模被蚀刻到反向掺杂的区域中。在凹槽的侧壁上形成有电介质隔离件，凹部底部的一部分露出。然后将金属沉积在凹部中并在凹部的底部反应形成硅化物。凹槽里填充有抛光的填充材料。然后去除硬掩模以形成硅化物掩埋的局部互连。

5. 发明授权

US07816206B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07816206B2
公开(公告)日：2010-10-19
申请号：US12318580
申请日：2008-12-31
申请人： Jusuke Ogura
发明人： Jusuke Ogura
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/105 , H01L27/11526 , H01L27/11543
摘要： The semiconductor device comprises a silicon substrate 14 having a step formed in the surface which makes the surface in a flash memory cell region 10 lower than the surface in a peripheral circuit region 12; a device isolation region 20a formed in a trench 18 in the flash memory cell region 10; a device isolation region 20c formed in a trench 24 deeper than the trench 18 in the peripheral circuit region 12; a flash memory cell 46 including a floating gate 32 and a control gate 40 formed on the device region defined by the device isolation region 20a; and transistors 62, 66 formed on the device regions defined by the device isolation region 20c.
摘要翻译：半导体器件包括硅衬底14，其具有在表面中形成的台阶，其使闪存单元区域10中的表面比外围电路区域12中的表面低; 形成在闪存单元区域10中的沟槽18中的器件隔离区域20a; 形成在比外围电路区域12中的沟槽18更深的沟槽24中的器件隔离区域20c; 闪存单元46包括形成在由器件隔离区域20a限定的器件区域上的浮动栅极32和控制栅极40; 以及形成在由器件隔离区域20c限定的器件区域上的晶体管62,66。

6. 发明申请

US20070205467A1 semiconductor device and process for producing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070205467A1
公开(公告)日：2007-09-06
申请号：US11649269
申请日：2007-01-04
申请人： Hiroshi Morioka , Jusuke Ogura , Sergey Pidin
发明人： Hiroshi Morioka , Jusuke Ogura , Sergey Pidin
IPC分类号： H01L29/76
CPC分类号： H01L21/76877 , H01L21/823807 , H01L21/823864 , H01L21/823871 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a contact structure is provided. The semiconductor device includes: a conductive region; a first film and a second film which are formed over the conductive region to realize a layer; and a contact electrode which extends through the layer to the conductive region, and is formed so as to replace a portion of the layer with a portion of the contact electrode, where the portion of the layer is constituted by only the first film, only the second film, or both of a portion of the first film and a portion of the second film, and the portion of the first film occupies a major part of the portion of the layer.
摘要翻译：提供具有接触结构的半导体器件。半导体器件包括：导电区域; 形成在所述导电区域上以实现层的第一膜和第二膜; 以及接触电极，该接触电极通过该层延伸到导电区域，并且形成为用该接触电极的一部分来代替该层的一部分，其中该部分仅由第一膜构成，只有第二膜或第一膜的一部分和第二膜的一部分两者，并且第一膜的部分占该层的该部分的主要部分。

7. 发明申请

US20060220097A1 Semiconductor device and method for fabricating the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060220097A1
公开(公告)日：2006-10-05
申请号：US11253739
申请日：2005-10-20
申请人： Jusuke Ogura
发明人： Jusuke Ogura
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/105 , H01L27/11526 , H01L27/11543
摘要： The semiconductor device comprises a silicon substrate 14 having a step formed in the surface which makes the surface in a flash memory cell region 10 lower than the surface in a peripheral circuit region 12; a device isolation region 20a formed in a trench 18 in the flash memory cell region 10; a device isolation region 20c formed in a trench 24 deeper than the trench 18 in the peripheral circuit region 12; a flash memory cell 46 including a floating gate 32 and a control gate 40 formed on the device region defined by the device isolation region 20a; and transistors 62, 66 formed on the device regions defined by the device isolation region 20c.
摘要翻译：半导体器件包括硅衬底14，其具有在表面中形成的台阶，其使闪存单元区域10中的表面比外围电路区域12中的表面低; 形成在闪存单元区域10中的沟槽18中的器件隔离区域20a; 形成在比外围电路区域12中的沟槽18更深的沟槽24中的器件隔离区域20c; 闪存单元46包括形成在由器件隔离区域20a限定的器件区域上的浮动栅极32和控制栅极40; 以及形成在由器件隔离区域20c限定的器件区域上的晶体管62,66。

8. 发明申请

US20060081915A1 Nonvolatile semiconductor memory device and method for fabricating the same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20060081915A1
公开(公告)日：2006-04-20
申请号：US11076063
申请日：2005-03-10
申请人： Jusuke Ogura , Hiroyuki Ogawa , Tatsuo Chijimatsu
发明人： Jusuke Ogura , Hiroyuki Ogawa , Tatsuo Chijimatsu
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/42324 , H01L29/4238 , H01L29/792
摘要： The nonvolatile semiconductor memory device comprises a channel region formed in a semiconductor substrate, a gate electrode formed over the channel region with a charge retaining insulating film interposed therebetween, a first pair of source/drain regions arranged in a first direction with the channel region formed therebetween, and a second pair of source/drain regions arranged in a second direction intersecting the first direction with the channel region formed therebetween. The channel region and the gate electrode are common between a first memory cell transistor including the first pair of source/drain regions and a second memory cell transistor including the second pair of source/drain regions.
摘要翻译：非易失性半导体存储器件包括形成在半导体衬底中的沟道区，栅电极，形成在沟道区上，其间具有电荷保持绝缘膜，第一对源极/漏极区沿第一方向排列，形成沟道区以及沿与第一方向相交的第二方向布置的第二对源/漏区，其间形成有沟道区。沟道区域和栅电极在包括第一对源极/漏极区域的第一存储单元晶体管和包括第二对源极/漏极区域的第二存储单元晶体管之间是共同的。

9. 发明授权

US06642148B1 RELACS shrink method applied for single print resist mask for LDD or buried bitline implants using chemically amplified DUV type photoresist 失效
标题翻译： RELACS收缩方法应用于使用化学放大DUV型光致抗蚀剂的LDD或埋入式位线植入物的单面抗蚀剂掩模
公开(公告)号：US06642148B1
公开(公告)日：2003-11-04
申请号：US10126326
申请日：2002-04-19
申请人： Kouros Ghandehari , Emmanuil H. Lingunis , Mark S. Chang , Angela Hui , Scott Bell , Jusuke Ogura
发明人： Kouros Ghandehari , Emmanuil H. Lingunis , Mark S. Chang , Angela Hui , Scott Bell , Jusuke Ogura
IPC分类号： H01L21302
CPC分类号： H01L29/6659 , H01L21/0274 , H01L21/31144 , H01L21/743 , H01L27/112 , H01L27/11521 , H01L27/11568
摘要： The present invention generally relates to a method of forming a graded junction within a semiconductor substrate. A first masking pattern having a first opening characterized by a first lateral dimension is formed over the semiconductor substrate. The semiconductor substrate is doped with a first dopant, using the first masking pattern as a doping mask, thereby forming a first dopant region in the semiconductor substrate underlying the first opening. The first masking pattern is swelled to decrease the first lateral dimension of the first opening to a second lateral dimension. The semiconductor substrate is then doped with a second dopant, using the swelled first masking pattern as a doping mask, thereby forming a second dopant region in the semiconductor substrate, and furthermore defining a graded junction within the semiconductor substrate.
摘要翻译：本发明一般涉及一种在半导体衬底内形成渐变结的方法。在半导体衬底上形成第一掩模图案，其具有由第一横向尺寸表征的第一开口。半导体衬底掺杂有第一掺杂剂，使用第一掩模图案作为掺杂掩模，由此在第一开口下面的半导体衬底中形成第一掺杂区域。第一掩模图案被膨胀以将第一开口的第一横向尺寸减小到第二横向尺寸。然后使用膨胀的第一掩模图案作为掺杂掩模，然后用半导体衬底掺杂第二掺杂剂，从而在半导体衬底中形成第二掺杂区，并且还限定半导体衬底内的渐变结。

10. 发明授权

US08749062B2 Semiconductor device and process for producing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08749062B2
公开(公告)日：2014-06-10
申请号：US11649269
申请日：2007-01-04
申请人： Hiroshi Morioka , Jusuke Ogura , Sergey Pidin
发明人： Hiroshi Morioka , Jusuke Ogura , Sergey Pidin
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L21/8238 , H01L29/78
CPC分类号： H01L21/76877 , H01L21/823807 , H01L21/823864 , H01L21/823871 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a contact structure is provided. The semiconductor device includes: a conductive region; a first film and a second film which are formed over the conductive region to realize a layer; and a contact electrode which extends through the layer to the conductive region, and is formed so as to replace a portion of the layer with a portion of the contact electrode, where the portion of the layer is constituted by only the first film, only the second film, or both of a portion of the first film and a portion of the second film, and the portion of the first film occupies a major part of the portion of the layer.
摘要翻译：提供具有接触结构的半导体器件。半导体器件包括：导电区域; 形成在所述导电区域上以实现层的第一膜和第二膜; 以及接触电极，该接触电极通过该层延伸到导电区域，并且形成为用该接触电极的一部分来代替该层的一部分，其中该部分仅由第一膜构成，只有第二膜或第一膜的一部分和第二膜的一部分两者，并且第一膜的部分占该层的该部分的主要部分。

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