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11. 发明公开

EP1394844A4 METHOD OF FABRICATING SEMICONDUCTOR DEVICE 有权
标题翻译： VERFAHREN ZUR HERSTELLUNG EINES HALBLEITERBAUEMENTS
公开(公告)号：EP1394844A4
公开(公告)日：2006-11-15
申请号：EP02730853
申请日：2002-05-31
申请人： TOKYO ELECTRON LTD
发明人： YOKOYAMA SHIN , NAKAJIMA ANRI , TADA YOSHIHIDE , NAKAMURA GENJI , IMAI MASAYUKI , YONEKAWA TSUKASA
IPC分类号： C23C16/30 , C23C16/34 , C23C16/44 , C23C16/455 , C23C16/56 , H01L21/314 , H01L21/316 , H01L21/318 , H01L21/321 , H01L21/8242 , H01L27/108 , H01L29/78
CPC分类号： H01L21/3185 , B82Y10/00 , B82Y30/00 , C23C16/30 , C23C16/345 , C23C16/45546 , C23C16/56 , H01L21/3144 , H01L21/3145 , H01L21/31612 , H01L21/31662 , H01L21/3211 , Y10S438/909
摘要： A method of fabricating a semiconductor device, capable of improving the in-plane uniformity of a silicon nitride film or a silicon oxynitride film to be formed, and increasing a production efficiency at the film forming. The method comprises the steps of forming on a silicon substrate a first film consisting of a silicon oxide film or a silicon oxynitride film, forming a second film consisting of one tetrachlorosilane monomolecular layer, and nitriding the second film to form a third film consisting of one silicon nitride monomolecular layer. The second film forming step and the third film forming steps are repeated specified number of times to form a silicon nitride film of a specified film thickness. A fabrication device comprises a plurality of silicon substrates disposed on shelf-shaped wafer ports, a process gas being supplied toward above a reaction pipe from a process gas supply pipe.
摘要翻译：一种制造半导体器件的方法，其能够改善待形成的氮化硅膜或氧氮化硅膜的面内均匀性，并提高成膜时的生产效率。该方法包括以下步骤：在硅衬底上形成由氧化硅膜或氮氧化硅膜组成的第一膜，形成由一个四氯硅烷单分子层组成的第二膜，以及氮化第二膜以形成由一个氮化硅单分子层。重复第二成膜步骤和第三成膜步骤规定次数以形成特定膜厚的氮化硅膜。一种制造装置包括设置在架状晶片端口上的多个硅衬底，工艺气体从工艺气体供应管朝向反应管上方供应。

12. 发明公开

EP1616042A2 SYSTEM AND METHOD FOR FORMING MULTI-COMPONENT DIELECTRIC FILMS 审中-公开
标题翻译：系统和方法的形成介电薄膜多组分
公开(公告)号：EP1616042A2
公开(公告)日：2006-01-18
申请号：EP04750402.2
申请日：2004-04-21
申请人： Aviza Technology, Inc.
发明人： SENZAKI, Yoshihide , PARK, Seung, G.
IPC分类号： C23C16/00
CPC分类号： C23C16/45531 , C23C16/029 , C23C16/308 , C23C16/401 , H01L21/3141 , H01L21/3142 , H01L21/3143 , H01L21/3145 , H01L21/31608 , H01L21/31612 , H01L21/31645
摘要： The present invention provides systems and methods for mixing vaporized precursors such that a mixture of vaporized precursors are present together in a chamber (102) during a single pulse step in an atomic layer deposition (ALD) process to form a multi-component film. The vaporized precursors are comprised of at least two different chemical components, and such different components will form a monolayer to produce a multi-component film. In a further aspect of the invention, a dielectric film having a composition gradient is provided.

13. 发明公开

EP1442476A1 DIELECTRIC FILM 有权
标题翻译：介质膜
公开(公告)号：EP1442476A1
公开(公告)日：2004-08-04
申请号：EP02766293.1
申请日：2002-09-17
申请人： Advion BioSciences, Inc.
发明人： LI, Jie , CORSO, Thomas, N. , SCHULTZ, Gary, A.
IPC分类号： H01L21/306 , H01L29/78 , H01L29/74 , H01L29/00 , B32B7/00 , G02B1/11
CPC分类号： H01B7/2825 , G01N27/44704 , G01N30/7266 , H01B3/10 , H01B3/12 , H01L21/3143 , H01L21/3145 , H01L21/3146
摘要： A dielectric film is provided which includes a base layer and a capping layer, preferably silicon oxynitride, wherein the film is an effective moisture and ion barrier when disposed between a conductive substrate and a liquid having an electrical potential different than the electrical potential of the substrate.

14. 发明公开

EP0975017A3 Silicon oxynitride cap for fluorinated silicate glass film in intermetal dielectric semiconductor fabrication 审中-公开
标题翻译：用于金属间半导体生产的氟化玻璃膜的氮氧化硅的保护膜
公开(公告)号：EP0975017A3
公开(公告)日：2003-03-26
申请号：EP99113533.6
申请日：1999-07-06
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Lee, Gill Yong
IPC分类号： H01L21/314
CPC分类号： H01L21/02131 , H01L21/0214 , H01L21/02211 , H01L21/02274 , H01L21/02304 , H01L21/02362 , H01L21/3145 , H01L21/31629 , H01L21/76801 , H01L21/76802 , H01L21/76829 , H01L23/3192 , H01L23/5329 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A semiconductor device and method of forming a patterned conductive layer on a semiconductor substrate are provided so as to prevent fluorine substance outflow from a fluorinated silicate glass (FSG) layer thereon and simultaneously so as to suppress back reflection of light waves into a photoresist layer during photolithographic processing. The substrate is coated in turn with a conductive layer, a dielectric (e.g., silicon dioxide) liner, a FSG layer, a silicon oxynitride layer preventing fluorine substance outflow therethrough from the FSG layer and also forming an antireflective coating (ARC), and a photoresist layer. The photoresist layer is exposed and developed to uncover pattern portions of the underlying silicon oxynitride layer. The uncovered pattern portions of the silicon oxynitride ARC layer and corresponding underlying portions of the FSG layer and dielectric liner are then removed, e.g., by,a single dry etching step, to expose pattern portions of the conductive layer for metallization. Upon metallization, the substrate is provided with a combination of the FSG layer and silicon oxynitride layer, in which the silicon oxynitride layer prevents fluorine substance outflow therethrough from the underlying FSG layer to an overlying conductive layer.

15. 发明公开

EP1282163A1 Semiconductor device and manufacturing method thereof 审中-公开
标题翻译： Halbleiterbauelement und Herstellungsverfahrendafür
公开(公告)号：EP1282163A1
公开(公告)日：2003-02-05
申请号：EP02016303.6
申请日：2002-07-24
申请人： Kabushiki Kaisha Toshiba
发明人： Watanabe, Kei, Intellectual Property Division , Nishiyama, Yukio, Intellectual Property Division
IPC分类号： H01L21/768
CPC分类号： H01L21/76832 , H01L21/02131 , H01L21/0214 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/3145 , H01L21/31629 , H01L21/76807 , H01L21/76828 , H01L21/76829 , H01L21/76834
摘要： A semiconductor device comprises a semiconductor substrate (13), an interlayer insulating layer (1) formed above the semiconductor substrate (13), a first metal interconnection (3) embedded in the interlayer insulating layer (1) with a surface thereof exposed to the same plane as a surface of the interlayer insulating layer (1), a diffusion preventive layer (4) formed on at least the first metal interconnection (3) to prevent diffusion of a metal included in the first metal interconnection (3), a nitrogen-doped silicon oxide layer (5) formed on the diffusion preventive layer (4), a fluorine-doped silicon oxide layer (6) formed on the nitrogen-doped silicon oxide layer (5), and a second metal interconnection (11) embedded in the fluorine-doped silicon oxide layer (6) with a surface thereof exposed to the same plane as a surface of the fluorine-doped silicon oxide layer (6), and electrically connected to the first metal interconnection (3).
摘要翻译：半导体器件包括半导体衬底（13），形成在半导体衬底（13）上方的层间绝缘层（1），嵌入在层间绝缘层（1）中的第一金属互连（3），其表面暴露于与层间绝缘层（1）的表面相同的平面，形成在至少第一金属互连（3）上的防扩散层（4），以防止第一金属互连（3）中包含的金属的扩散，形成在扩散防止层（4）上的掺杂氧化硅层（5），形成在氮掺杂氧化硅层（5）上的氟掺杂氧化硅层（6）和嵌入的第二金属互连在氟掺杂氧化硅层（6）中，其表面暴露于与氟掺杂氧化硅层（6）的表面相同的平面，并与第一金属互连（3）电连接。

16. 发明公开

EP1199743A2 Method of fabricating a stack consisting of a layer of Si3N4 topped by a layer of SiO2 on a semiconductor substrate 审中-公开
标题翻译：制造上的Halbleitersubtsrat层选自由氮化硅层的叠层和SiO 2层上覆方法
公开(公告)号：EP1199743A2
公开(公告)日：2002-04-24
申请号：EP01122519.0
申请日：2001-09-21
申请人： TEXAS INSTRUMENTS DEUTSCHLAND GMBH
发明人： Foglietti, Pietro , Staufer, Berthold , Artinger, Josef
IPC分类号： H01L21/314
CPC分类号： H01L21/02164 , C23C16/345 , C23C16/402 , H01L21/0217 , H01L21/022 , H01L21/02219 , H01L21/02271 , H01L21/3144 , H01L21/3145 , H01L21/31612 , H01L21/3185 , H01L21/8249
摘要： A method of fabricating a stack consisting of a layer of Si 3 N 4 topped by a layer of SiO 2 on a semiconductor substrate involves depositing the layer of Si 3 N 4 on the semiconductor substrate in a reactor in a NH 3 and bis(tert.-butylamino)silane atmosphere at a temperature of 600 to 650°C and a pressure of 40 to 53 Pa and then depositing the layer of SiO 2 on the layer of Si 3 N 4 in the same reactor in an O 2 and bis(tert.-butylamino)silane atmosphere at a temperature of 600 to 650°C and a pressure of 40 to 53 Pa.
摘要翻译：一种制造堆叠由...组成的Si3N4层的的方法，通过淋上SiO 2的层上的半导体衬底涉及在沉积氮化硅的在半导体基板上的层中的NH 3和双（叔丁基氨基）硅烷气氛中的反应器的温度600〜650℃和40〜53 Pa的压力，然后在600至温度沉积SiO 2的层的Si3N4层上在同一反应器中，在O 2和双（叔丁基氨基）硅烷的气氛 650℃和40〜53 Pa的压力。

17. 发明公开

EP1177574A1 ANTI-REFLECTIVE COATINGS AND METHODS REGARDING SAME 有权
标题翻译：过程中的集成电路部进行防反射涂层
公开(公告)号：EP1177574A1
公开(公告)日：2002-02-06
申请号：EP00928389.6
申请日：2000-04-25
申请人： Micron Technology, Inc.
发明人： HOLSCHER, Richard , YIN, Zhiping
IPC分类号： H01L21/027 , G03F7/09
CPC分类号： H01L21/0276 , G03F7/091 , H01L21/0337 , H01L21/3145
摘要： A method of forming an anti-reflective coating material layer in the fabrication of integrated circuits includes providing a substrate assembly having a surface and providing an inorganic anti-reflective coating material layer on the substrate assembly surface. The inorganic anti-reflective coating material layer has an associated first etch rate when exposed to an etchant. The method further includes thermally treating the inorganic anti-reflective coating material layer formed thereon such that the thermally treated anti-reflective coating material layer then has an associated second etch rate less than the first etch rate when exposed to the etchant, e.g. the second etch rate is less than 16 Å/minute, the second etch rate is less than 20 % of the first etch rate, etc.

18. 发明公开

EP1143502A1 METHOD FOR PRODUCING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：EP1143502A1
公开(公告)日：2001-10-10
申请号：EP99943289.1
申请日：1999-09-13
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： SUGAHARA, Gaku , SAITOH, Tohru , KUBO, Minoru , OHNISHI, Teruhito
IPC分类号： H01L21/324
CPC分类号： H01L29/66916 , H01L21/02164 , H01L21/02271 , H01L21/02381 , H01L21/0245 , H01L21/02529 , H01L21/02532 , H01L21/28512 , H01L21/28525 , H01L21/3145 , H01L21/31612 , H01L21/3185 , H01L21/823807 , H01L29/66242
摘要： The following process control is performed in the case of fabricating both a wafer for a device including a Ge-containing semiconductor film and a wafer for a SiCMOS device, for example, including no Ge-containing semiconductor film on a common fabrication line. When the wafer including the Ge-containing semiconductor film is to be subjected to high-temperature treatment at 700°C or more in the state of the Ge-containing semiconductor film being substantially exposed, the Ge-containing semiconductor film is covered with a cap layer made of Si or the like before the high-temperature treatment. The cap layer may be formed on the common fabrication line, but, if the formation of the cap layer itself involves high temperature of 700°C or more, it is performed on a fabrication line separate from the common fabrication line. Alternatively, the cap layer may be formed on a fabrication line separate from the common fabrication line and the high-temperature treatment at 700°C or more may also be performed on a separate fabrication line. Otherwise, it is enough to only perform the high-temperature treatment at 700°C or more on a separate line.
摘要翻译：在制造用于包括含Ge半导体膜的器件的晶片和用于SiCMOS器件的晶片（例如，在普通生产线上不包含含Ge半导体膜）的情况下执行以下处理控制。当在含Ge半导体膜基本上暴露的状态下，在700℃以上对包含含Ge半导体膜的晶片进行高温处理时，用盖覆盖含Ge半导体膜在高温处理之前由Si等制成的层。盖层可以形成在公共生产线上，但是如果盖层自身的形成涉及700℃或更高的高温，则在与公共生产线分开的生产线上进行。或者，盖层可以在与普通生产线分离的生产线上形成，并且700℃或更高的高温处理也可以在单独的生产线上进行。否则，仅在单独的生产线上进行700°C或更高温度的高温处理就足够了。

19. 发明公开

EP1135796A1 PROCESS FOR FORMING A SION/TEOS INTERLEVEL DIELECTRIC WITH AFTER-TREATMENT OF THE CVD SILICIUM OXYNITRIDE LAYER 有权
标题翻译：制造方法的SiON / SiO2介电中间层用硅氧氮化物的CVD的处置
公开(公告)号：EP1135796A1
公开(公告)日：2001-09-26
申请号：EP99930309.2
申请日：1999-06-16
申请人： ADVANCED MICRO DEVICES INC.
发明人： SUN, Sey-Ping , GARDNER, Mark, I. , NGO, Minh, Van
IPC分类号： H01L21/314 , H01L21/316 , H01L21/768
CPC分类号： H01L21/76801 , H01L21/3145 , H01L21/76828 , H01L21/76834
摘要： An interlevel dielectric including a tetraethyl orthosilicate (TEOS) oxide and a silicon oxynitride (SiON) etch stop layer is formed for use un integrated circuit fabrication. A SiON layer is deposited onto a semiconductor substrate which may include transistors and/or interconnect levels. The SiON layer is heated before deoposition of the TEOS layer. Heating of the SiON layer greatly reduces the number of defects formed during the TEOS deposition. A highly conformal, high-quality interlevel dielectric is thereby formed.

20. 发明公开

EP0942464A3 Surface passivation using silicon oxynitride 审中-公开
标题翻译：由氮氧化硅的装置的表面钝化
公开(公告)号：EP0942464A3
公开(公告)日：2000-07-26
申请号：EP99301756.5
申请日：1999-03-09
申请人： SIEMENS AKTIENGESELLSCHAFT , International Business Machines Corporation
发明人： Cote, Donna Rizzone , Cote, William Joseph , Nguyen, Son Van , Kirchhoff, Markus , Levy, Max G. , Hauf, Manfred
IPC分类号： H01L21/314 , C23C16/30
CPC分类号： H01L27/10873 , H01L21/28176 , H01L21/3003 , H01L21/3145 , H01L27/10861
摘要： A process for fabricating a device including the step of forming a structure for facilitating the passivation of surface states is disclosed. The structure comprises an oxynitride layer formed as part of the device structure. The oxynitride facilitates the passivation of surface states when heated.

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