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1. 发明授权

EP3208846B1 SEMICONDUCTOR DEVICE 有权
公开(公告)号：EP3208846B1
公开(公告)日：2018-09-12
申请号：EP17156454.5
申请日：2003-07-24
申请人： Socionext Inc.
发明人： Watanabe, Kenichi
IPC分类号： H01L23/522 , H01L23/532 , H01L23/58
CPC分类号： H01L21/76877 , H01L21/76804 , H01L21/76843 , H01L23/481 , H01L23/485 , H01L23/522 , H01L23/5226 , H01L23/5227 , H01L23/528 , H01L23/5283 , H01L23/53204 , H01L23/53223 , H01L23/53228 , H01L23/53266 , H01L23/5329 , H01L23/53295 , H01L23/562 , H01L23/58 , H01L23/585 , H01L29/0607 , H01L29/0611 , H01L29/0619 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device comprises: insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a, wherein the groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Whereby, the defective filling of the buried conductor is prevented, and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced, so that the step cannot be influential on the upper interconnection layers and insulating layers. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented, and resultantly the semiconductor device can have high water resistance and high interconnection reliability.

2. 发明公开

EP3336127A1 POLYARYLENE RESINS 审中-公开
公开(公告)号：EP3336127A1
公开(公告)日：2018-06-20
申请号：EP17205305.0
申请日：2017-12-04
申请人： Rohm and Haas Electronic Materials LLC
发明人： WANG, Qing Min , MICHAEL-SAPIA, Elizabeth K. , GILMORE, Christopher , DING, Ping , KIM, Young-Seok
IPC分类号： C08G61/10 , C08G61/12 , C09D165/02 , C08L65/02 , H01L23/532
CPC分类号： C08G61/128 , C08G61/10 , C08G61/12 , C08G2261/135 , C08G2261/1426 , C08G2261/228 , C08G2261/312 , C08G2261/46 , C08G2261/64 , C08G2261/65 , C08G2261/76 , C08L65/02 , C09D165/02 , H01L21/02118 , H01L21/02282 , H01L23/145 , H01L23/5329
摘要： Polyarylene polymers formed from an aromatic dialkyne monomer having a solubility enhancing moiety and having relatively high weight average molecular weights and a relatively low polydispersity show improved solubility in certain organic solvents and are useful in forming relatively thick dielectric material layers in a single coating step.

3. 发明公开

EP3146538A4 METHOD OF MANUFACTURING A MICRO-FABRICATED WAFER LEVEL INTEGRATED INDUCTOR OR TRANSFORMER FOR HIGH FREQUENCY SWITCH MODE POWER SUPPLIES 有权
公开(公告)号：EP3146538A4
公开(公告)日：2018-02-28
申请号：EP15795680
申请日：2015-05-26
申请人： TEXAS INSTRUMENTS INC
发明人： LEE DOK WON , FRENCH WILLIAM D , PAPOU ANDREI
IPC分类号： H01F27/28 , H01F17/00 , H01L21/02 , H01L23/00 , H01L23/522 , H01L23/532 , H01L25/10 , H01L49/02
CPC分类号： H01L28/10 , H01F17/0033 , H01F27/2804 , H01F2027/2809 , H01L23/5222 , H01L23/5226 , H01L23/5227 , H01L23/5329 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/17 , H01L24/33 , H01L24/80 , H01L25/105 , H01L2224/0345 , H01L2224/03622 , H01L2224/0401 , H01L2224/05548 , H01L2224/05567 , H01L2224/131 , H01L2224/1705 , H01L2224/30505 , H01L2224/80031 , H01L2224/80862 , H01L2225/1011 , H01L2924/01029 , H01L2924/06 , H01L2924/364 , H01L2924/00014 , H01L2924/014
摘要： A method of manufacturing an inductor on a wafer level process that can operate at 20 MHz with good efficiency and a high inductance density is disclosed, wherein the inductor design allows high frequency operation, low RDSON values and high efficiency.

4. 发明公开

EP3123499A4 THROUGH-BODY VIA FORMATION TECHNIQUES 有权
公开(公告)号：EP3123499A4
公开(公告)日：2017-11-22
申请号：EP14886882
申请日：2014-03-24
申请人： INTEL CORP
发明人： LEE KEVIN J
IPC分类号： H01L21/60 , H01L21/288 , H01L21/768 , H01L23/00 , H01L23/48 , H01L25/065
CPC分类号： H01L23/481 , H01L21/288 , H01L21/76829 , H01L21/76831 , H01L21/76873 , H01L21/76898 , H01L23/53209 , H01L23/53238 , H01L23/5329 , H01L24/02 , H01L24/05 , H01L25/0657 , H01L2224/02372 , H01L2224/05008 , H01L2224/05022 , H01L2224/05569 , H01L2225/06544
摘要： Techniques are disclosed for forming a through-body-via (TBV) in a semiconductor die. In accordance with some embodiments, a TBV provided using the disclosed techniques includes a polymer-based barrier layer and an electrically conductive seed layer formed by applying an electrically conductive ink directly to the barrier layer and then curing it in situ. In some embodiments, after curing, the resultant seed layer may be a thin, substantially conformal, electrically conductive metal film over which the TBV interconnect metal can be deposited. In some example cases, a polyimide, parylene, benzocyclobutene (BCB), and/or polypropylene carbonate (PPC) barrier layer and an ink containing copper (Cu) and/or silver (Ag), of nanoparticle-based or metal complex-based formulation, may be used in forming the TBV. In some instances, the disclosed techniques may be used to address poor step coverage, low run rate, and/or high cost issues associated with existing physical vapor deposition (PVD)-based far-back-end-of-line (FBEOL) processes.

5. 发明公开

EP3238245A1 MATERIALS AND DEPOSITION SCHEMES USING PHOTOACTIVE MATERIALS FOR INTERFACE CHEMICAL CONTROL AND PATTERNING OF PREDEFINED STRUCTURES 审中-公开
标题翻译：使用光敏材料进行界面化学控制和预定义结构图案的材料和沉积方案
公开(公告)号：EP3238245A1
公开(公告)日：2017-11-01
申请号：EP14909261.1
申请日：2014-12-24
申请人： Intel Corporation
发明人： HOURANI, Rami , LEESON, Michael J. , YOUNKIN, Todd R. , HAN, Eungnak , BRISTOL, Robert L.
IPC分类号： H01L21/768 , H01L21/60
CPC分类号： H01L21/76816 , G03F7/0035 , G03F7/165 , H01L21/0271 , H01L21/76808 , H01L21/76825 , H01L21/76831 , H01L21/76897 , H01L23/5226 , H01L23/528 , H01L23/5329
摘要： Embodiments of the invention include microelectronic devices and methods of forming such devices. In an embodiment, a microelectronic device, includes one or more pre-patterned features formed into a interconnect layer, with a conformal barrier layer formed over the first wall, and the second wall of one or more of the pre-patterned features. A photoresist layer may formed over the barrier layer and within one or more of the pre-patterned features and a conductive via may be formed in at least one of the pre-patterned features.
摘要翻译：本发明的实施例包括微电子器件和形成这种器件的方法。在一个实施例中，微电子器件包括形成到互连层中的一个或多个预先图案化的特征，具有形成在第一壁上方的共形阻挡层以及一个或多个预先图案化的特征的第二壁。可以在阻挡层上并且在一个或多个预先形成图案的特征内形成光致抗蚀剂层，并且可以在至少一个预先形成图案的特征中形成导电过孔。

6. 发明公开

EP3097582A4 METHODS FOR FORMING INTERCONNECT LAYERS HAVING TIGHT PITCH INTERCONNECT STRUCTURES 有权
公开(公告)号：EP3097582A4
公开(公告)日：2017-11-01
申请号：EP14879315
申请日：2014-12-09
申请人： INTEL CORP
发明人： JEZEWSKI CHRISTOPHER J , CHAWLA JASMEET S , SINGH KANWAL JIT , MYERS ALAN M , TAN ELIOT N , SCHENKER RICHARD E
IPC分类号： H01L21/768
CPC分类号： H01L21/7688 , H01L21/0337 , H01L21/31144 , H01L21/76808 , H01L21/76811 , H01L21/76816 , H01L21/76831 , H01L21/76886 , H01L21/76897 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Processes for forming interconnection layers having tight pitch interconnect structures within a dielectric layer, wherein trenches and vias used to form interconnect structures have relatively low aspect ratios prior to metallization. The low aspect ratios may reduce or substantially eliminate the potential of voids forming within the metallization material when it is deposited. Embodiments herein may achieve such relatively low aspect ratios through processes that allow for the removal of structures, which are utilized to form the trenches and the vias, prior to metallization.

7. 发明公开

EP3162868A1 THERMAL BASE GENERATOR, THERMOSETTING RESIN COMPOSITION, CURED FILM, CURED FILM MANUFACTURING METHOD, AND SEMICONDUCTOR DEVICE 有权转让
标题翻译：发电机热基板，热固性树脂组合物，固化膜，用于生产该固化膜与半导体元件的
公开(公告)号：EP3162868A1
公开(公告)日：2017-05-03
申请号：EP15812604
申请日：2015-06-26
申请人： FUJIFILM CORP
发明人： KOYAMA ICHIRO
IPC分类号： C09K3/00 , C08K5/17 , C08L101/00 , G03F7/004
CPC分类号： C08K5/19 , B05D3/007 , C08K5/17 , C08K5/18 , C08K5/3462 , C08L101/00 , C09D179/08 , C09D179/085 , C09K3/00 , G03F7/004 , H01L21/76834 , H01L23/5329 , H01L2224/16145 , H01L2224/16225 , H01L2924/15174
摘要： Provided are a thermal base generator which is capable of performing cyclization of a thermosetting resin at a low temperature and with which a thermosetting resin composition having excellent stability can be prepared, a thermosetting resin composition, a cured film, a cured film manufacturing method, and a semiconductor device. The thermal base generator includes at least one selected from an acidic compound which generates a base in a case of being heated to 40°C or higher, and an ammonium salt containing an anion having a pKa1 of 0 to 4 and an ammonium cation. The acidic compound is preferably an ammonium salt and/or a compound represented by the following General Formula (1), in which A 1 represents a p-valent organic group, R 1 represents a monovalent organic group, L 1 represents an (m+1)-valent organic group, m represents an integer of 1 or more, and p represents an integer of 1 or more.
摘要翻译：本发明提供一种热碱产生的所有其能够在低的温度，并用其中具有优异的稳定性的热固化性树脂组合物可以制备进行热固性树脂的环化的，热固性树脂组合物，固化电影，固化的薄膜的制造方法，和的半导体器件。所述热碱产生包括至少一个由在酸性化合物，其基因率被加热到40℃或更高的情况下的碱，并且铵盐阴离子的含具有0 pKa1的至4和阳离子铵。酸性化合物优选为（在铵盐和/或由下述通式（1），其中A 1 darstellt的p价有机基团，R 1 darstellt一价有机基团，L 1个M +的darstellt表示的化合物 1）价的有机基团，m darstellt到1以上的整数，并且p darstellt到1以上的整数。

8. 发明公开

EP3123499A1 THROUGH-BODY VIA FORMATION TECHNIQUES 有权
标题翻译： VERFAHREN ZUR BILDUNG VONKÖRPERDURCHGÄNGEN
公开(公告)号：EP3123499A1
公开(公告)日：2017-02-01
申请号：EP14886882.1
申请日：2014-03-24
申请人： Intel Corporation
发明人： LEE, Kevin, J.
IPC分类号： H01L21/60 , H01L23/48
CPC分类号： H01L23/481 , H01L21/288 , H01L21/76829 , H01L21/76831 , H01L21/76873 , H01L21/76898 , H01L23/53209 , H01L23/53238 , H01L23/5329 , H01L24/02 , H01L24/05 , H01L25/0657 , H01L2224/02372 , H01L2224/05008 , H01L2224/05022 , H01L2224/05569 , H01L2225/06544
摘要： Techniques are disclosed for forming a through-body-via (TBV) in a semiconductor die. In accordance with some embodiments, a TBV provided using the disclosed techniques includes a polymer-based barrier layer and an electrically conductive seed layer formed by applying an electrically conductive ink directly to the barrier layer and then curing it in situ. In some embodiments, after curing, the resultant seed layer may be a thin, substantially conformal, electrically conductive metal film over which the TBV interconnect metal can be deposited. In some example cases, a polyimide, parylene, benzocyclobutene (BCB), and/or polypropylene carbonate (PPC) barrier layer and an ink containing copper (Cu) and/or silver (Ag), of nanoparticle-based or metal complex-based formulation, may be used in forming the TBV. In some instances, the disclosed techniques may be used to address poor step coverage, low run rate, and/or high cost issues associated with existing physical vapor deposition (PVD)-based far-back-end-of-line (FBEOL) processes.
摘要翻译：公开了用于在半导体管芯中形成通孔通孔（TBV）的技术。根据一些实施例，使用所公开的技术提供的TBV包括基于聚合物的阻挡层和通过将导电油墨直接施加到阻挡层然后将其原位固化而形成的导电种子层。在一些实施例中，在固化之后，所得种子层可以是薄的，基本上共形的导电金属膜，TBV互连金属可以沉积在其上。在一些示例性实例中，基于纳米颗粒或基于金属络合物的聚酰亚胺，聚对二甲苯，苯并环丁烯（BCB）和/或聚丙烯碳酸酯（PPC）阻挡层和含有铜（Cu）和/或银（Ag）配方，可用于形成TBV。在一些情况下，所公开的技术可以用于解决与现有的基于物理气相沉积（PVD）的远端后端（FBEOL）过程相关联的差的步骤覆盖率，低运行速率和/或高成本问题。

9. 发明公开

EP2779244A3 Method of forming a HEMT semiconductor device and structure therefor 审中-公开
标题翻译：一种用于制造半导体HEMT装置及其结构的方法
公开(公告)号：EP2779244A3
公开(公告)日：2016-10-05
申请号：EP14158995.2
申请日：2014-03-11
申请人： Semiconductor Components Industries, LLC
发明人： Salih, Ali , Liu, Chun-Li , Grivna, Gordon
IPC分类号： H01L29/778 , H01L21/336 , H01L29/66 , H01L23/532 , H01L23/498 , H01L23/482 , H01L23/522 , H01L29/20 , H01L21/768 , H01L23/00 , H01L21/683
CPC分类号： H01L23/5226 , H01L21/6836 , H01L21/76898 , H01L21/78 , H01L23/4824 , H01L23/49827 , H01L23/53228 , H01L23/53242 , H01L23/5329 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/37 , H01L24/40 , H01L24/48 , H01L24/84 , H01L29/2003 , H01L29/66462 , H01L29/778 , H01L29/7787 , H01L2221/68327 , H01L2224/0345 , H01L2224/0346 , H01L2224/0347 , H01L2224/04034 , H01L2224/05111 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05639 , H01L2224/05647 , H01L2224/06181 , H01L2224/37012 , H01L2224/37013 , H01L2224/37124 , H01L2224/37147 , H01L2224/3716 , H01L2224/37187 , H01L2224/3719 , H01L2224/37639 , H01L2224/37644 , H01L2224/37647 , H01L2224/37655 , H01L2224/37664 , H01L2224/40499 , H01L2224/83801 , H01L2224/8385 , H01L2224/84801 , H01L2224/84815 , H01L2224/8485 , H01L2924/00014 , H01L2924/12032 , H01L2924/12042 , H01L2924/1305 , H01L2924/13063 , H01L2924/13064 , H01L2924/13091 , H01L2924/00 , H01L2924/01028 , H01L2924/014 , H01L2924/0105 , H01L2924/01047 , H01L2924/01082 , H01L2924/00012 , H01L2924/01029 , H01L2924/07811 , H01L2224/45099
摘要： In one embodiment, a method of forming a HEMT device may include plating a conductor or a plurality of conductors onto an insulator that overlies a plurality of current carrying electrodes of the HEMT device. The method may also include attaching a connector onto the conductor or attaching a plurality of connectors onto the plurality of conductors.

10. 发明公开

EP2951856A4 INTERCONNECTS THROUGH DIELECTRIC VIAS 审中-公开
标题翻译：介电经文交联
公开(公告)号：EP2951856A4
公开(公告)日：2016-09-21
申请号：EP13873334
申请日：2013-01-29
申请人： HEWLETT PACKARD DEVELOPMENT CO
发明人： DOOLEY KEVIN , MCQUAID ROGER , CHEEVERS LIAM , FITZPATRICK DAVID , BYRNE LORRAINE
IPC分类号： H01L23/522 , H01L21/28 , H01L21/768 , H01L23/532
CPC分类号： H01L23/5226 , H01L21/76802 , H01L21/76828 , H01L21/76877 , H01L23/528 , H01L23/5283 , H01L23/5329 , H01L27/1214 , H01L2924/0002 , H01L2924/00
摘要： A dielectric layer includes a reflow via. The reflow via is formed by reflow of the dielectric layer. An interconnect is in contact through the reflow via.

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