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1. 发明授权

EP4057326B1 HIGH RESISTIVITY SILICON-ON-INSULATOR SUBSTRATE HAVING ENHANCED CHARGE TRAPPING EFFICIENCY 有权
公开(公告)号：EP4057326B1
公开(公告)日：2024-10-09
申请号：EP22170810.0
申请日：2017-10-09
IPC分类号： H01L21/762 , H01L21/02 , H01L29/78 , H01L29/786
CPC分类号： H01L21/02516 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/02381 , H01L21/0245 , H01L21/76254 , H01L29/78603

2. 发明公开

EP4386812A1 PROCÉDÉ DE FABRICATION D'UN DISPOSITIF SEMICONDUCTEUR 审中-实审
公开(公告)号：EP4386812A1
公开(公告)日：2024-06-19
申请号：EP23215729.7
申请日：2023-12-12
申请人： Commissariat à l'énergie atomique et aux énergies alternatives
发明人： ACOSTA ALBA, Pablo , REBOH, Shay
IPC分类号： H01L21/02 , H01L21/8234 , H01L21/8238 , H01L29/10 , H01L29/78 , H01L21/268
CPC分类号： H01L29/1054 , H01L21/823821 , H01L21/823807 , H01L21/268 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02686
摘要： Un aspect de l'invention concerne un procédé de fabrication d'un dispositif semiconducteur comprenant une première zone semi-conductrice optimisée pour la conduction par électrons et une deuxième zone semi-conductrice optimisée pour la conduction par trous, le procédé comprenant les étapes suivantes :
- fournir une structure multicouches comprenant un substrat et une couche de silicium-germanium disposée sur le substrat ;
- définir dans la structure multicouches une première région destinée à contenir la première zone semi-conductrice et une deuxième région destinée à contenir la deuxième zone semi-conductrice ;
- soumettre la structure multicouches à un recuit laser de manière à modifier une portion de la structure multicouches située dans la deuxième région, ladite portion comprenant avant le recuit laser une partie de la couche de silicium-germanium, ladite portion présentant après le recuit laser un gradient de concentration en germanium avec une concentration en germanium qui augmente en direction d'une face supérieure de ladite portion.

3. 发明公开

EP4374417A1 METHODS OF FORMATION OF A SIGE/SI SUPERLATTICE 审中-实审
公开(公告)号：EP4374417A1
公开(公告)日：2024-05-29
申请号：EP22846606.6
申请日：2022-07-21
申请人： Applied Materials, Inc.
发明人： TOLLE, John , KIRSCHENHEITER, Thomas , MARGETIS, Joe , LIU, Patricia M. , ZHU, Zuoming , CHANG, Flora Fong-Song
IPC分类号： H01L21/02
CPC分类号： H01L21/02532 , H01L21/02381 , H01L21/02433 , H01L21/0245 , H01L21/02507 , H01L21/0262 , C23C16/24 , C23C16/45523 , C23C16/0209 , C30B25/02 , C30B29/68 , C30B29/06 , C30B25/165

5. 发明公开

EP3295484A1 METHOD FOR MAKING ENHANCED SEMICONDUCTOR STRUCTURES IN SINGLE WAFER PROCESSING CHAMBER WITH DESIRED UNIFORMITY CONTROL 有权
公开(公告)号：EP3295484A1
公开(公告)日：2018-03-21
申请号：EP16728814
申请日：2016-06-01
申请人： ATOMERA INCORPORATED
发明人： MEARS ROBERT J , CODY NYLES , STEPHENSON ROBERT JOHN
IPC分类号： H01L29/15
CPC分类号： H01L21/02507 , H01L21/0245 , H01L21/0262 , H01L29/0649 , H01L29/151 , H01L29/152
摘要： A method for processing a semiconductor wafer in a single wafer processing chamber may include heating the single wafer processing chamber to a temperature in a range of 650-700 DEG C, and forming atleast one superlattice on the semiconductor wafer within the heated single wafer processing chamber by depositing silicon and oxygen to form a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base silicon monolayers defining a base silicon portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions.Depositing the oxygen may include depositing the oxygen using an N2O gas flow.

6. 发明公开

EP3266038A1 METHOD OF DEPOSITING CHARGE TRAPPING POLYCRYSTALLINE SILICON FILMS ON SILICON SUBSTRATES WITH CONTROLLABLE FILM STRESS 有权转让
标题翻译：可控薄膜应力沉积硅基底多晶硅薄膜的方法
公开(公告)号：EP3266038A1
公开(公告)日：2018-01-10
申请号：EP16716946.5
申请日：2016-02-25
申请人： SunEdison Semiconductor Limited
发明人： LIBBERT, Jeffrey Louis , WANG, Gang , THOMAS, Shawn G. , PEIDOUS, Igor
IPC分类号： H01L21/02 , H01L21/763 , H01L21/762
CPC分类号： H01L21/76254 , H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02513 , H01L21/02532 , H01L21/02639 , H01L21/76251 , H01L21/763 , H01L27/1203
摘要： A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, a textured oxide, nitride, or oxynitride layer, a polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer. The multilayer structure is prepared in a manner that reduces wafer bow.

7. 发明公开

EP3265850A1 FOLIE AUS METALL ODER EINER METALLLEGIERUNG 审中-公开
标题翻译：金属或金属合金箔
公开(公告)号：EP3265850A1
公开(公告)日：2018-01-10
申请号：EP16720042.7
申请日：2016-03-07
申请人： Neutrino Deutschland GmbH
发明人： SCHUBART, Holger Thorsten
IPC分类号： G01T1/00
CPC分类号： H01M4/661 , G01T1/00 , H01L21/02425 , H01L21/02444 , H01L21/0245 , H01L21/02507 , H01L21/02527 , H01L21/02532 , H01L31/028 , H01L31/072 , H01L31/115 , H01M4/0423 , H01M4/134 , H01M4/366 , H01M4/386 , H01M4/583 , Y02E10/547
摘要： The invention relates to a film made of metal or a metal alloy, in particular a film made of aluminum or an aluminum alloy, a so-called neutrino or ntrino film (registered trademarks), to a method of production and to a use of a film made of metal or a metal alloy.

8. 发明公开

EP3243221A2 INTEGRATED PHOTONICS INCLUDING WAVEGUIDING MATERIAL 审中-实审
标题翻译：集成光子技术，包括波导材料
公开(公告)号：EP3243221A2
公开(公告)日：2017-11-15
申请号：EP16755999.6
申请日：2016-01-05
申请人： The Research Foundation for The State University of New York
发明人： COOLBAUGH, Douglas , ADAM, Thomas , LEAKE, Gerald L.
IPC分类号： H01L31/08 , H01L31/0288 , H01L31/0392 , H01L31/054 , H01L31/10
CPC分类号： G02B6/13 , G02B6/12002 , G02B6/132 , G02B6/1347 , G02B6/136 , G02B6/43 , G02B2006/121 , G02B2006/12104 , G02B2006/12123 , G02B2006/12169 , H01L21/02381 , H01L21/0245 , H01L21/02505 , H01L21/02532 , H01L21/02573 , H01L21/0262 , H01L21/02639 , H01L21/2033 , H01L21/2053 , H01L27/14625 , H01L27/14629 , H01L31/022408 , H01L31/0232 , H01L31/02327 , H01L31/028 , H01L31/105 , H01L31/1808 , Y02E10/52 , Y02E10/547
摘要： A photonic structure can include in one aspect one or more waveguides formed by patterning of waveguiding material adapted to propagate light energy. Such waveguiding material may include one or more of silicon (single-, poly-, or non-crystalline) and silicon nitride.

9. 发明公开

EP3050092A4 NON-SILICON DEVICE HETEROLAYERS ON PATTERNED SILICON SUBSTRATE FOR CMOS BY COMBINATION OF SELECTIVE AND CONFORMAL EPITAXY 审中-公开
标题翻译：之间。通过组合选择性，符合外延在硅衬底EYED FOR CMOS硅-FREE装置的各层
公开(公告)号：EP3050092A4
公开(公告)日：2017-05-03
申请号：EP13894917
申请日：2013-09-27
申请人： INTEL CORP
发明人： GOEL NITI , CHAU ROBERT S , KAVALIEROS JACK T , CHU-KUNG BENJAMIN , METZ MATTHEW V , MUKHERJEE NILOY , ZELICK NANCY M , DEWEY GILBERT , RACHMADY WILLY , RADOSAVLJEVIC MARKO , LE VAN H , PILLARISETTY RAVI , DASGUPTA SANSAPTAK
IPC分类号： H01L21/336 , H01L21/02 , H01L21/20 , H01L21/8238 , H01L21/8252 , H01L27/092 , H01L29/06 , H01L29/165 , H01L29/205 , H01L29/66 , H01L29/78
CPC分类号： H01L21/0245 , H01L21/02381 , H01L21/02461 , H01L21/02463 , H01L21/02502 , H01L21/02532 , H01L21/02543 , H01L21/02546 , H01L21/02598 , H01L21/02639 , H01L21/02647 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L21/8252 , H01L27/0922 , H01L27/0924 , H01L29/0649 , H01L29/1054 , H01L29/16 , H01L29/165 , H01L29/20 , H01L29/205 , H01L29/66795 , H01L29/785
摘要： A single fin or a pair of co-integrated n- and p- type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one or a pair of trenches formed between shallow trench isolation (STI) regions. The fin or fins are patterned and the STI regions are etched to form a height of the fin or fins extending above etched top surfaces of the STI regions. The fin heights may be at least 1.5 times their width. The exposed sidewall surfaces and a top surface of each fin is epitaxially clad with one or more conformal epitaxial materials to form device layers on the fin. Prior to growing the fins, a blanket buffer epitaxial material may be grown from the substrate surface; and the fins grown in STI trenches formed above the blanket layer. Such formation of fins reduces defects from material interface lattice mismatches.
摘要翻译：单鳍或一对的共整合n型和p型单晶电子装置翅片外延从表面基材在一个的底部或一对浅沟槽隔离（STI）区域之间形成的沟槽的生长。翅片或散热片被图案化和STI区域被蚀刻以形成上述的STI区的蚀刻顶表面延伸的翅片或翼片的高度。翅片高度可以是至少1.5倍的宽度。暴露的侧壁表面和每个翅片的顶表面上外延与一种或多种适形外延材料包覆，以形成在鳍的器件层。之前生长翅片，毯子缓冲外延材料可从表面衬底上生长; 和在STI生长翅片沟槽的覆盖层的上方形成。翅片的搜索形成降低从材料界面的晶格失配的缺陷。

10. 发明公开

EP3152780A1 MELT-GROWTH OF SINGLE-CRYSTAL ALLOY SEMICONDUCTOR STRUCTURES AND SEMICONDUCTOR ASSEMBLIES INCORPORATING SUCH STRUCTURES 有权
标题翻译：熔炼采用此构造增长-EINKRISTALLLEGIERUNGSHALBLEITERSTRUKTUREN和半导体安排
公开(公告)号：EP3152780A1
公开(公告)日：2017-04-12
申请号：EP15727645.2
申请日：2015-06-05
申请人： University Of Southampton
发明人： GARDES, Frederic Yannick , REED, Graham Trevor , LITTLEJOHNS, Callum George
IPC分类号： H01L21/20
CPC分类号： C30B29/52 , C30B13/14 , C30B13/22 , C30B13/34 , C30B29/06 , C30B29/08 , C30B29/18 , H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02532 , H01L21/02546 , H01L21/02587 , H01L21/02625 , H01L21/02647 , H01L21/02667 , H01L21/02675
摘要： A method of fabricating at least one single-crystal alloy semiconductor structure, comprising: forming at least one seed on a substrate for growth of at least one single-crystal alloy semiconductor structure, the at least one seed containing an alloying material; providing at least one structural form on the substrate which is crystallized to form the at least one single-crystal alloy semiconductor structure, the at least one structural form being formed of a host material and comprising a main body which extends from the at least one seed and a plurality of elements which are connected in spaced relation to the main body; heating the at least one structural form such that the material of the at least one structural form has a liquid state; and cooling the at least one structural form, such that the material of the at least one structural form nucleates at the least one seed and crystallizes as a single crystal to provide at least one single-crystal alloy semiconductor structure, with a growth front of the single crystal propagating in the main body of the respective structural form away from the respective seed; wherein the plurality of elements of each structural form provide reservoirs of the alloying material in liquid state, such that successive ones of the plurality of elements act to maintain, in liquid state, an available supply of the alloying material to the growth front of the single crystal in the main body of the respective structural form.
摘要翻译：单晶半导体合金结构或制造该包括方法：形成包含在基片3的合金化材料的种子7; 在基片上提供的基质材料的结构形状11全部是结晶以形成单晶合金半导体结构，所述结构形式，其包含从所述种子并连接成间隔关系的元素33的多元性延伸的主体31 主体; 施加热寻没结构形状具有液体状态; 和冷却检查没有在种子上的结构形式成核并结晶为单晶合金，以提供到半导体结构。在一个，实施例的元件的多元性提供在液体状态下的合金化材料的贮存器，谋求确实元件的多个相继作用在液体状态下保持在至生长前的单晶的合金化材料的可用供给在respectivement结构形式的主体。在一个实施方案中，主体材料可以是锗和合金化材料可以是硅树脂。

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