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1. 发明申请

WO2016068886A1 MEMCAPACITIVE CROSS-BAR ARRAY FOR DETERMINING A DOT PRODUCT 审中-公开
标题翻译：用于确定产品的备选十字架阵列
公开(公告)号：WO2016068886A1
公开(公告)日：2016-05-06
申请号：PCT/US2014/062694
申请日：2014-10-28
申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
发明人： GE, Ning , STRACHAN, John Paul , YANG, Jianhua , HU, Miao
IPC分类号： G11C11/24 , G11C11/34
CPC分类号： G11C11/24 , G06G7/16 , G11C11/34
摘要： A method of obtaining a dot product includes applying a programming signal to a number of capacitive memory devices coupled at a number of junctions formed between a number of row lines and a number of column lines. The programming signal defines a number of values within a matrix. The method further includes applying a vector signal. The vector signal defines a number of vector values to be applied to the capacitive memory devices.
摘要翻译：获得点积的方法包括将编程信号应用于多个电容存储器件，该多个电容存储器耦合在形成在多条行线和多条列线之间的多个结点处。编程信号定义矩阵内的数值。该方法还包括应用向量信号。向量信号定义要施加到电容性存储器件的多个矢量值。

2. 发明申请

WO2015155906A1 メモリの温度上昇を抑制するための装置およびプログラム审中-公开
标题翻译：用于抑制存储器温度升高的程序和设备
公开(公告)号：WO2015155906A1
公开(公告)日：2015-10-15
申请号：PCT/JP2014/079823
申请日：2014-11-11
申请人：株式会社フィックスターズ
发明人：米谷　聡 , 土山　了士 , 村瀬　正名 , 二木　紀行
IPC分类号： G06F12/16 , G06F12/00 , G06F12/06
CPC分类号： G11C7/1045 , G06F12/00 , G06F12/06 , G06F12/16 , G11C5/025 , G11C7/04 , G11C8/12 , G11C11/34 , G11C11/413
摘要：　本発明の課題は、積層された複数のメモリモジュールを備えるメモリが、データの読み書きに伴い高温となることを抑制することである。本発明の一実施形態にかかる記憶装置は積層された複数のメモリモジュールを備える。メモリコントローラとしての役割を果たすデータ処理装置は、データの書込要求を受けると、同時にデータが書き込まれるメモリモジュールが互いに隣接せず、また、一連の書込シーケンスにおいて、後続の書込タイミングでデータが書き込まれるメモリモジュールが、先行する書込タイミングでデータが書き込まれるメモリモジュールと隣接しないように、書込先のメモリモジュールを順次選択する。その結果、積層された複数のメモリモジュールにおける発熱箇所が分散され、高温化が低減される。
摘要翻译：本发明解决的问题在于存储器，其具有多个堆叠的存储器模块，由于读取/写入数据而被抑制到达到高温。在本发明的一个实施例中的存储装置设置有多个堆叠的存储器模块。当接收到数据写入请求时，满足存储器控制器的作用的数据处理装置顺序选择作为写入目的地的存储器模块，使得同时写入数据的存储器模块彼此不相邻，并且在一系列写入序列中，在随后的写入定时将数据写入的存储器模块与在前一个写入定时中写入数据的存储器模块不相邻。结果，多个层叠的存储器模块之间的发热位置分布，减少了温度的上升。

3. 发明申请

WO2011100138A2 CROSS-POINT MEMORY CELLS, NON-VOLATILE MEMORY ARRAYS, METHODS OF READING A MEMORY CELL, METHODS OF PROGRAMMING A MEMORY CELL, METHODS OF WRITING TO AND READING FROM A MEMORY CELL, AND COMPUTER SYSTEMS 审中-公开
标题翻译：交叉点存储器单元，非易失性存储器阵列，读取存储器单元的方法，编程存储器单元的方法，写入和读取存储器单元的方法和计算机系统
公开(公告)号：WO2011100138A2
公开(公告)日：2011-08-18
申请号：PCT/US2011/023190
申请日：2011-01-31
申请人： MICRON TECHNOLOGY, INC , MEADE, Roy, E.
发明人： MEADE, Roy, E.
IPC分类号： G11C11/00 , G11C7/10
CPC分类号： G11C11/24 , G11C8/08 , G11C11/34 , G11C11/56 , G11C11/565 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/0011 , G11C13/004 , G11C13/0061 , G11C13/0069 , H01L27/101 , H01L28/40 , H01L45/08 , H01L45/12 , H01L45/1233
摘要： Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, and methods of writing to and reading from a memory cell are described. In one embodiment, a cross-point memory cell includes a word line extending in a first direction, a bit line extending in a second direction different from the first direction, the bit line and the word line crossing without physically contacting each other, and a capacitor formed between the word line and the bit line where such cross. The capacitor comprises a dielectric material configured to prevent DC current from flowing from the word line to the bit line and from the bit line to the word line.
摘要翻译：描述了交叉点存储器单元，非易失性存储器阵列，读取存储器单元的方法，编程存储器单元的方法，以及写入存储器单元和从存储器单元读取的方法。在一个实施例中，交叉点存储单元包括在第一方向上延伸的字线，在与第一方向不同的第二方向上延伸的位线，位线和字线交叉而不物理接触，电容之间形成了字线与位线之间的交叉。电容器包括被配置为防止直流电流从字线流到位线和从位线到字线的电介质材料。

4. 发明申请

WO2016118229A1 PRE-PROGRAM DETECTION OF THRESHOLD VOLTAGES OF SELECT GATE TRANSISTORS IN A MEMORY DEVICE 审中-公开
标题翻译：预编程检测存储器件中选择栅极晶体管的阈值电压
公开(公告)号：WO2016118229A1
公开(公告)日：2016-07-28
申请号：PCT/US2015/061669
申请日：2015-11-19
申请人： SanDisk Technologies LLC
发明人： DUTTA, Deepanshu , MURAI, Shota , TOMIIE, Hideto , HIGASHITANI, Masaaki
IPC分类号： G11C29/02 , G11C11/56 , G11C16/34
CPC分类号： G11C16/34 , G11C11/34 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3418 , G11C16/349 , G11C29/028
摘要： A memory device includes memory cells arranged in NAND strings between select gate transistors. A threshold voltage (Vth) distribution of the select gate transistors is evaluated, such as in response to a program, erase or read command involving a block or sub-block of memory cells. For example, a lower tail and an upper tail of the Vth distribution can be evaluated using read voltages. If the Vth is out-of-range, such as due to read disturb, data retention loss or defects in the memory device, the block or sub-block is marked as being bad and previously-programmed data in the block or sub-block can be copied to another location. If the Vth is in range, the command can be executed. Also, a control gate voltage for the select gate transistors can be set based on a Vth metric which is obtained from the evaluation.
摘要翻译：存储器件包括布置在选择栅晶体管之间的NAND串中的存储器单元。评估选择栅极晶体管的阈值电压（Vth）分布，例如响应于涉及存储器单元的块或子块的程序，擦除或读取命令。例如，可以使用读取电压来评估Vth分布的下尾和上尾。如果Vth超出范围，例如由于读取干扰，数据保留损失或存储器件中的缺陷，则块或子块被标记为块或子块中的先前编程的数据可以复制到另一个位置。如果Vth在范围内，则可以执行命令。此外，可以基于从评估获得的Vth度量来设置用于选择栅极晶体管的控制栅极电压。

5. 发明申请

WO2015005636A1 메모리 시스템 및 메모리의 데이터 처리 방법 审中-公开
标题翻译：用于存储器的存储器系统和数据处理方法
公开(公告)号：WO2015005636A1
公开(公告)日：2015-01-15
申请号：PCT/KR2014/006099
申请日：2014-07-08
申请人： 주식회사 윌러스표준기술연구소
发明人： 오현오
IPC分类号： G11C16/10 , G11C16/34
CPC分类号： G11C11/5628 , G06F11/1072 , G06F11/34 , G06F12/0246 , G06F17/30 , G06F2212/7202 , G06F2212/7211 , G11C11/34 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/34 , G11C29/021 , Y02D10/13
摘要： 본 발명은 메모리 시스템 및 메모리의 데이터 처리 방법에 관한 것으로서, 더욱 상세하게는 데이터를 효율적으로 처리하기 위한 메모리 시스템 및 메모리의 데이터 처리 방법에 관한 것이다. 이를 위해 본 발명은, 메모리의 데이터 처리 방법으로서, 상기 메모리 내의 미리 결정된 위치의 파일럿 셀에 미리 결정된 노미널(nominal)값의 전압을 인가하여 데이터를 프로그래밍하는 단계; 상기 파일럿 셀의 기록된 전압 값을 판독하는 단계; 상기 판독된 파일럿 셀의 전압 값에 기초하여 상기 데이터에 대응하는 노미널 값을 교정하는 단계; 및 상기 교정된 노미널 값을 이용하여 상기 메모리의 데이터 셀에 상기 데이터를 프로그래밍 하는 단계; 를 포함하는 메모리의 데이터 처리 방법 및 이를 이용한 메모리 시스템을 제공한다.
摘要翻译：本发明涉及一种用于存储器的存储器系统和数据处理方法，更具体地，涉及一种存储器系统和用于有效处理数据的存储器的数据处理方法。为此，本发明提供了一种用于存储器和使用其的存储器系统的数据处理方法，该存储器的数据处理方法包括以下步骤：通过将预定标称值的电压施加到导频单元来编程数据在存储器内的预定位置处; 读取记录在导频小区中的电压值; 基于从导频小区读取的电压值对与数据对应的标称值进行校正; 并通过使用校正的标称值将数据编程到存储器的数据单元。

6. 发明申请

WO01084634A1 INFORMATION PROCESSING STRUCTURE 审中-公开
标题翻译：信息处理结构
公开(公告)号：WO01084634A1
公开(公告)日：2001-11-08
申请号：PCT/JP2001/002469
申请日：2001-03-27
IPC分类号： H01L21/8247 , G11C11/34 , H01L27/10 , H01L29/06 , H01L29/66 , H01L29/78 , H01L29/788 , H01L29/792
CPC分类号： B82Y10/00 , G11C11/34 , G11C2216/08 , H01L29/7613 , H01L29/7888
摘要： An information processing structure having a single-electron circuit stably operating at high speed by single-electron action is constituted by forming a plurality of quantum dots (13) of a nanometer-scale just above a gate electrode (12) of a microminiaturized MOSFET (11), constructing an energy barrier between the quantum dots and the gate electrode between which electrons can directly tunnel, and representing information by the total number of electrons migrating between the quantum dots and the gate electrode, wherein a power source electrode (14) which serves as a power source is provided in contact with the quantum dots between the quantum dots and the power source electrode (14) in such a way that an energy barrier through which electrons can directly tunnel is structure, two information electrodes (15) are formed in contact with a quantum dot in such a way that the quantum dot and the information electrode are capacitively coupled, and electrons migrate between the power source electrode and the gate electrode through the quantum dots by the Coulomb blockade phenomenon in accordance with the electric potential determined by the information electrodes.
摘要翻译：具有通过单电子作用高速稳定运行的单电子电路的信息处理结构通过在微型化的MOSFET的栅电极（12）的正上方形成纳米级的多个量子点（13）在量子点和栅电极之间构造能量阻挡层，电子可以直接隧穿，并且通过在量子点和栅电极之间迁移的电子的总数来表示信息，其中电源电极（14）用作与量子点和电源电极（14）之间的量子点接触的电源，使得电子可以直接隧道通过的能量势垒为结构，形成两个信息电极（15）以量子点和信息电极电容耦合的方式与量子点接触，并且电子在电源之间迁移电极和栅极通过量子点通过库仑阻塞现象根据由信息电极确定的电位。

7. 发明申请

WO98045847A1 DIGITAL INFORMATION STORAGE 审中-公开
标题翻译：数字信息存储
公开(公告)号：WO98045847A1
公开(公告)日：1998-10-15
申请号：PCT/AU1998/000247
申请日：1998-04-09
IPC分类号： C03C17/22 , G11C11/21 , G11C11/24 , G11C11/34
CPC分类号： H01L27/24 , C03C17/22 , C03C2217/282 , C03C2218/151 , G11C11/21 , G11C11/24 , G11C11/34
摘要： This information flows from the application of a newly found property of tetrahedral amorphous carbon. The invention relates to a digital information storage device useful in a range of applications. In a further aspect, the invention relates to a writable medium. The invention uses a layer of tetrahedral amorphous carbon and electrical means which are movable relative to each other. The electrical means are operable to reversibly change both the resistance and small signal capacitance of the tetrahedral amorphous carbon device in the region adjacent the electrical means. The principal advantage of using ta-C as a basis for digital information storage is its inherent inexpense, since it can be deposited very easily and cheaply over large areas. The material also has the potential for achieving higher storage densities than current non-volatile memories, and possibly higher than even DRAM. In terms of a design ta-C memories have the potential to be fabricated without the need for an access transistor. In this configuration memory arrays could be created simply by depositing a ta-C film in between perpendicular sets of conductive address lines, with a memory cell, or bit, at the intersection between crossing lines. Ta-C could also be used in place of the storage capacitor dielectric in a DRAM cell configuration, allowing long term memory storage by the ta-C memory effect, and providing against the possibility of soft errors through the use of an isolating access transistor. Alternatively, it is possible to write to the medium electrostatically with a simple point contact, or many point contacts in parallel.
摘要翻译：该信息来自应用新发现的四面体无定形碳的性质。本发明涉及在一系列应用中有用的数字信息存储装置。在另一方面，本发明涉及可写介质。本发明使用可相对于彼此移动的四面体非晶碳层和电气装置。电气装置可操作以在邻近电气装置的区域中可逆地改变四面体非晶碳装置的电阻和小信号电容。使用ta-C作为数字信息存储的基础的主要优点是其固有的廉价，因为它可以在大面积上非常容易且便宜地存放。该材料还具有实现比当前非易失性存储器更高存储密度的可能性，并且可能高于均匀的DRAM。在设计方面，ta-C存储器具有在不需要存取晶体管的情况下被制造的潜力。在这种配置中，存储器阵列可以简单地通过在交叉线之间的相交处的存储单元或位之间沉积导电地址线的垂直组之间沉积ta-C膜。也可以使用Ta-C代替DRAM单元配置中的存储电容器电介质，通过ta-C存储器效应允许长期存储器存储，并通过使用隔离存取晶体管提供软错误的可能性。或者，可以用简单的点接触或并联的许多点触点静电地写入介质。

8. 发明申请

WO2013120285A1 半导体存储器件及其访问方法审中-公开
公开(公告)号：WO2013120285A1
公开(公告)日：2013-08-22
申请号：PCT/CN2012/071713
申请日：2012-02-28
申请人：中国科学院微电子研究所 , 朱正勇 , 骆志炯
发明人：朱正勇 , 骆志炯
IPC分类号： H01L29/792 , G11C11/34
CPC分类号： G11C11/34 , H01L29/778
摘要：提供一种半导体存储器件及其访问方法，其中半导体存储器件包括氧化物异质结晶体管，所述氧化物异质结晶体管包括氧化物衬底；位于氧化物衬底上的氧化物薄膜，其中氧化物衬底和氧化物薄膜之间的界面层表现出二维电子气的特性；位于氧化物薄膜上并且与界面层电连接的源电极和漏电极；位于氧化物薄膜上的前栅；以及位于氧化物衬底下表面上的背栅，其中，氧化物异质结晶体管的源电极和漏电极分别与用于执行读取操作的第一字线和第一位线相连接，前栅和背栅分别与用于执行写入操作的第二字线和第二位线相连接。该半导体存储器件是1T配置的存储器件，其结构简单，并且提高了集成度。

9. 发明申请

WO2012138016A1 문턱전압 스위칭 물질을 이용한 비휘발성 메모리 소자 및 그 제조 방법 审中-公开
标题翻译：使用阈值电压切换材料的非易失性存储器件及其制造方法
公开(公告)号：WO2012138016A1
公开(公告)日：2012-10-11
申请号：PCT/KR2011/006034
申请日：2011-08-17
申请人： 고려대학교 산학협력단 , 김태근 , 안호명
发明人： 김태근 , 안호명
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： G11C11/34 , G11C13/0002 , H01L29/42332 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： 본 발명은 비휘발성 메모리 소자 및 그 제조 방법을 개시한다. 본 발명은 종래의 SONOS 구조의 비휘발성 메모리 소자의 블로킹 절연막을, 평상시에 고저항 상태를 유지하다가 문턱전압 이상의 전압이 인가되는 동안에만 저저항 상태로 변화되고 인가되는 전압을 제거하면 다시 고저항 상태로 환원되는 문턱전압 스위칭 물질로 대체하고, 게이트 전극층에 문턱 전압 이상의 전압 펄스를 인가하여, 게이트 전극층으로부터 문턱전압 스위칭 물질로 이루어진 절연막을 통해서 전하 포획층으로 전하를 주입하여 프로그램을 수행한다. 따라서, 본 발명의 비휘발성 메모리 소자는 프로그램시에 터널링을 이용하지 않을뿐만 아니라, 문턱전압 스위칭 물질의 저항 상태를 저저항 상태로 변환하여 프로그램을 수행한 후, 전하 포획층에 포획된 전하를 유지하기 위해서, 문턱전압 스위칭 물질의 저항 상태를 다시 고저항 상태로 변환하기 위한 별도의 전압 펄스를 인가하지 않아도 되므로, 종래의 SONOS 구조의 비휘발성 메모리 소자에 비해서 신속한 프로그램이 가능하다. 또한, 본 발명의 비휘발성 메모리 소자는 프로그램시에 터널링 방식을 이용하지 않으므로, 전하 포획층과 기판 사이의 절연막을 두께를 충분히 두껍게 형성하여 10년 이상의 데이터 보유 특성을 확보할 수 있으므로, 기존의 SONOS 구조의 비휘발성 메모리 소자에 비하여 신뢰성이 높다.
摘要翻译：非易失性存储器件及其制造方法技术领域本发明涉及非易失性存储器件及其制造方法。根据本发明，具有典型SONOS结构的非易失性存储器件的隔离绝缘层被阈值电压切换材料所替代，阈值电压切换材料仅在施加大于阈值电压的电压时变为低电阻状态，同时保持在正常条件下具有高电阻状态，并且当施加的电压被去除时返回到高电阻状态。本发明通过在向栅电极层施加大于阈值电压的电压脉冲之后，通过由阈值电压开关材料形成的绝缘层将电荷从栅电极层注入电荷陷阱层来执行程序。因此，本发明的非易失性存储器件在编程期间不使用隧道，并且将阈值电压切换材料的电阻状态改变为低电阻状态以便运行程序。此外，为了保持陷在电荷陷阱层中的电荷，不需要额外的电压脉冲，以将阈值电压切换材料的电阻状态再次转换为高电阻状态。因此，与具有典型SONOS结构的非易失性存储器件相比，快速编程是可能的。此外，由于本发明的非易失性存储器件在编程期间不使用隧道法，所以可以通过在绝缘层和基片之间形成足够的厚度来获得最少10年的数据保持。因此，与具有典型SONOS结构的非易失性存储器件相比，可以进一步提高可靠性。

10. 发明申请

WO2010077371A1 MEMRISTIVE DEVICE BASED ON CURRENT MODULATION BY TRAPPED CHARGES 审中-公开
标题翻译：基于电流调节的电磁感应装置
公开(公告)号：WO2010077371A1
公开(公告)日：2010-07-08
申请号：PCT/US2009/030122
申请日：2009-01-05
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , STRUKOV, Dmitri Borisovich
发明人： STRUKOV, Dmitri Borisovich
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/10 , B82Y10/00 , G11C11/34 , G11C13/0002 , G11C2213/15 , G11C2213/33 , G11C2213/77 , G11C2213/81
摘要： A memristive device (200) includes a first electrode (104); a second electrode (102); a junction (106) between the first electrode (104) and the second electrode (102), the junction (106) including a semiconductor matrix (230) and particles (240) embedded in the semiconductor matrix (230), the particles (240) being configured to hold a selectable level of electrical charge, the electrical charge controlling the amount of current flowing through the junction (106) for a given reading voltage. A method for using a memristive device (200) includes: applying a first voltage across a memristive junction (106), the memristive junction (106) including a semiconductor matrix (230) and particles (240) embedded in the semiconductor matrix (230); electrical charges introduced into the semiconductor matrix (230) by the first programming voltage being trapped within the particles (240); applying a reading voltage across the memristive junction (106); and measuring a current across the junction (106), the current being reduced proportionally to the electrical charges trapped within the potential wells, the current being used to determine a state of the junction (106).
摘要翻译：忆阻器（200）包括第一电极（104）; 第二电极（102）; 在第一电极（104）和第二电极（102）之间的结（106），结（106）包括半导体矩阵（230）和嵌入在半导体矩阵（230）中的颗粒（240））被配置为保持可选择的电荷电平，所述电荷控制在给定读取电压下流过所述结（106）的电流量。一种使用忆阻器件（200）的方法包括：跨越忆阻接头（106）施加第一电压，所述忆阻接头（106）包括半导体矩阵（230）和埋在半导体矩阵（230）中的颗粒（240） ; 由第一编程电压引入半导体矩阵（230）的电荷被捕获在颗粒（240）内; 在忆阻结（106）上施加读取电压; 并且测量跨越所述结（106）的电流，所述电流与被俘获在所述势阱内的电荷成比例地减小，所述电流用于确定所述结（106）的状态。

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