专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2008118084A1 CHARGE STORAGE NANOSTRUCTURE 审中-公开
标题翻译：充电储存纳米结构
公开(公告)号：WO2008118084A1
公开(公告)日：2008-10-02
申请号：PCT/SE2008/050334
申请日：2008-03-26
申请人： QUNANO AB , SAMUELSON, Lars , THELANDER, Claes
发明人： SAMUELSON, Lars , THELANDER, Claes
IPC分类号： H01L29/775 , G11C11/412
CPC分类号： H01L29/7881 , B82Y10/00 , G11C13/025 , G11C2213/16 , H01L27/11521 , H01L27/1156 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/66477 , H01L29/7888 , H01L29/792 , H01L29/7926 , Y10S977/936 , Y10S977/937 , Y10S977/938
摘要： The present invention relates to a nanostructured device for charge storage. In particular the invention relates to a charge storage device that can be used for memory applications. According to the invention the device comprise a first nanowire with a first wrap gate arranged around a portion of its length, and a charge storing terminal connected to one end, and a second nanowire with a second wrap gate arranged around a portion of its length. The charge storing terminal is connected to the second wrap gate, whereby a charge stored on the charge storing terminal can affect a current in the second nanowire. The current can be related to written (charged) or unwritten (no charge) state, and hence a memory function is established.
摘要翻译：本发明涉及一种用于电荷存储的纳米结构装置。特别地，本发明涉及一种可用于存储器应用的电荷存储装置。根据本发明，该装置包括第一纳米线，其具有围绕其一部分长度布置的第一卷绕栅极和连接到一端的电荷存储端子，以及在其长度的一部分周围布置的具有第二卷绕栅极的第二纳米线。电荷存储端子连接到第二卷绕栅极，由此存储在电荷存储端子上的电荷可以影响第二纳米线中的电流。电流可以与写入（充电）或未写入（无电荷）状态有关，因此建立了记忆功能。

2. 发明申请

WO01057927A1 SILICON NANOPARTICLE FIELD EFFECT TRANSISTOR AND TRANSISTOR MEMORY DEVICE 审中-公开
标题翻译：硅纳米晶场效应晶体管和晶体管存储器件
公开(公告)号：WO01057927A1
公开(公告)日：2001-08-09
申请号：PCT/US2001/003479
申请日：2001-02-02
IPC分类号： H01L29/06 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L27/15 , H01L29/423 , H01L29/66 , H01L29/78 , H01L29/788 , H01L29/792
CPC分类号： H01L29/42332 , B82Y10/00 , H01L29/7883 , H01L29/7888
摘要： A silicon nanoparticle (18) transistor (30, 32, 34) and transistor memory device. The transistor of the invention has silicon nanoparticles (18), dimensioned on the order of 1nm, in a gate area (34) of a field effect transistor (30, 32, 34). The resulting transistor is a transistor in which single electron flow controls operation of the transistor. Room temperature operation is possible with the novel transistor structure by radiation assistance, with radiation being directed toward the silicon nanoparticles to create necessary holes in the quantum structure for the flow of an electron. The transistor of the invention also forms the basis for a memory device. The device is a flash memory device which will store electrical charge instead of magnetic effects.
摘要翻译：硅纳米颗粒（18）晶体管（30,32,34）和晶体管存储器件。本发明的晶体管在场效应晶体管（30,32,34）的栅极区域（34）中具有大小为1nm的硅纳米颗粒（18）。所得晶体管是其中单个电子流控制晶体管的操作的晶体管。利用辐射辅助的新型晶体管结构可以进行室温操作，其中辐射被引向硅纳米颗粒，以在电子流中的量子结构中产生必要的空穴。本发明的晶体管还构成了存储器件的基础。该装置是一种闪存装置，其将存储电荷而不是磁效应。

3. 发明申请

WO2010083056A1 QUANTUM DOT TRANSISTOR 审中-公开
标题翻译：量子点晶体管
公开(公告)号：WO2010083056A1
公开(公告)日：2010-07-22
申请号：PCT/US2010/000114
申请日：2010-01-15
申请人： THE BOARD OF TRUSTEES OF THE LELAND STANFORD JUNIOR UNIVERSITY , HOLME, Timothy, P. , PRINZ, Friedrich, B. , TIAN, Xu
发明人： HOLME, Timothy, P. , PRINZ, Friedrich, B. , TIAN, Xu
IPC分类号： H01L29/76 , H01L29/10 , H01L29/12
CPC分类号： H01L29/7613 , B82Y10/00 , H01L29/107 , H01L29/127 , H01L29/7888 , H01L49/006
摘要： One or more quantum dots are used to control current flow in a transistor. Instead of being disposed in a channel between source and drain, the quantum dot (or dots) are vertically separated from the source and drain by an insulating layer. Current can tunnel between the source/drain electrodes and the quantum dot (or dots) by tunneling through the insulating layer. Quantum dot energy levels can be controlled with one or more gate electrodes capacitively coupled to some or all of the quantum dot(s). Current can flow between source and drain if a quantum dot energy level is aligned with the energy of incident tunneling electrons. Current flow between source and drain is inhibited if no quantum dot energy level is aligned with the energy of incident tunneling electrons. Here energy level alignment is understood to have a margin of about the thermal energy (e.g., 26 meV at room temperature).
摘要翻译：一个或多个量子点用于控制晶体管中的电流。代替设置在源极和漏极之间的沟道中，量子点（或点）通过绝缘层与源极和漏极垂直分离。通过穿过绝缘层，电流可以在源/漏电极和量子点（或点）之间隧穿。可以通过电容耦合到一些或全部量子点的一个或多个栅电极来控制量子点能级。如果量子点能级与入射隧道电子的能量对准，电流可以在源极和漏极之间流动。如果没有量子点能级与入射隧道电子的能量对准，则源极和漏极之间的电流将被抑制。这里，能级对准被理解为具有大约热能的余量（例如，在室温下为26meV）。

4. 发明申请

WO2004054922A3 NANOSTRUCTURE, ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：纳米结构，电子器件及其制造方法
公开(公告)号：WO2004054922A3
公开(公告)日：2005-04-28
申请号：PCT/JP0315948
申请日：2003-12-12
申请人： CANON KK , DEN TOHRU , FUKUTANI KAZUHIKO
发明人： DEN TOHRU , FUKUTANI KAZUHIKO
IPC分类号： B82B1/00 , B82B3/00 , C30B29/60 , H01L21/8247 , H01L27/115 , H01L29/06 , H01L29/423 , H01L29/788 , H01L29/792 , H01L39/22 , H01L39/24 , H01L51/30
CPC分类号： C30B29/60 , B82Y10/00 , B82Y30/00 , H01L29/42332 , H01L29/7888 , H01L2924/0002 , Y10S977/762 , Y10S977/893 , H01L2924/00
摘要： Cylinders having Al as a major constituent are orderly arrayed in an (Si, Ge) matrix. In a nanostructure in the form of a mixture film having a plurality of cylinders having Al as a major constituent, and a matrix region surrounding the plurality of cylinders and having Si and/or Ge as a major constituent, the total amount of Si and Ge is contained in a proportion in the range from 20 to 70 atomic % in the mixture film, the cylinders are orderly arrayed, the diameter of the cylinders is in the range from 1 to 30 nm, and the interval between the cylinders is 30 nm or smaller.
摘要翻译：具有Al作为主要成分的气缸有序排列在（Si，Ge）基体中。在具有以Al为主要成分的多个圆柱体的混合物膜的形式的纳米结构体和围绕多个圆筒的基体区域中，具有Si和/或Ge作为主要成分的Si和Ge的总量在混合膜中以20〜70原子％的比例含有，气缸排列顺序，气缸的直径为1〜30nm，气缸间的间隔为30nm，小。

5. 发明申请

WO02065507A3 DYNAMIC MEMORY BASED ON SINGLE ELECTRON STORAGE 审中-公开
标题翻译：基于单电子存储的动态记忆
公开(公告)号：WO02065507A3
公开(公告)日：2003-05-22
申请号：PCT/US0202761
申请日：2002-02-01
申请人： MICRON TECHNOLOGY INC
发明人： FORBES LEONARD , AHN KIE Y
IPC分类号： H01L20060101 , H01L21/00 , H01L21/335 , H01L21/336 , H01L21/8236 , H01L21/8238 , H01L21/8242 , H01L27/108 , H01L27/12 , H01L27/148 , H01L29/76 , H01L29/788
CPC分类号： B82Y10/00 , G11C2216/08 , H01L21/266 , H01L27/108 , H01L27/1203 , H01L29/7888 , Y10S438/947
摘要： A method for forming edge-defined structures with sub-lithographic dimensions which are used to further form conduction channels and/or storage structures in memory cells. Sacrificial silicon nitride islands 20 are deposited at low temperatures and then patterned and etched by high resolution etching techniques. Polysilicon 22 is next deposited over the sacrificial silicon nitride islands and directionally etched to form edge-defined polysilicon dot and strip structures 24 which are about one tenth the minimum feature size. The edge-defined polysilicon strips and dots are formed between the source and drain region of an NMOS device. Subsequent to the removal of the sacrificial silicon nitride islands, the edge-defined polysilicon strips and dots are used to mask a threshold voltage implantation in a conventional CMOS process. A conduction channel 87 and two adjacent potential minimum dots 89 are formed after the removal of the edge-defined polysilicon strips and dots.
摘要翻译：用于形成具有亚光刻尺寸的边缘限定结构的方法，其用于在存储器单元中进一步形成传导通道和/或存储结构。牺牲的氮化硅岛20在低温下沉积，然后通过高分辨率蚀刻技术被图案化和蚀刻。接着将多晶硅22沉积在牺牲氮化硅岛上并定向蚀刻以形成约为最小特征尺寸的十分之一的边缘限定的多晶硅点和带结构24。边界定义的多晶硅条带和点形成在NMOS器件的源极和漏极区域之间。在除去牺牲性氮化硅岛之后，边缘限定的多晶硅条和点用于掩蔽常规CMOS工艺中的阈值电压注入。在去除边界限定的多晶硅条纹和点之后形成导电通道87和两个相邻的电位最小点89。

6. 发明申请

WO2002065507A2 DYNAMIC MEMORY BASED ON SINGLE ELECTRON STORAGE 审中-公开
标题翻译：基于单电子存储的动态记忆
公开(公告)号：WO2002065507A2
公开(公告)日：2002-08-22
申请号：PCT/US2002/002761
申请日：2002-02-01
申请人： MICRON TECHNOLOGY, INC.
发明人： FORBES, Leonard , AHN, Kie, Y.
IPC分类号： H01L
CPC分类号： B82Y10/00 , G11C2216/08 , H01L21/266 , H01L27/108 , H01L27/1203 , H01L29/7888 , Y10S438/947
摘要： A method for forming edge-defined structures with sub-lithographic dimensions which are used to further form conduction channels and/or storage structures in memory cells. Sacrificial silicon nitride islands are deposited at low temperatures and then patterned and etched by high resolution etching techniques. Polysilicon is next deposited over the sacrificial silicon nitride islands and directionally etched to form edge-defined polysilicon dot and strip structures which are about one tenth the minimum feature size. The edge-defined polysilicon strips and dots are formed between the source and drain region of an NMOS device. Subsequent to the removal of the sacrificial silicon nitride islands, the edge-defined polysilicon strips and dots are used to mask a threshold voltage implantation in a conventional CMOS process. A conduction channel and two adjacent potential minimum dots are formed after the removal of the edge-defined polysilicon strips and dots.
摘要翻译：用于形成具有亚光刻尺寸的边缘限定结构的方法，其用于在存储器单元中进一步形成传导通道和/或存储结构。牺牲的氮化硅岛在低温下沉积，然后通过高分辨率蚀刻技术被图案化和蚀刻。随后将多晶硅沉积在牺牲氮化硅岛上并定向蚀刻以形成约为最小特征尺寸的十分之一的边界限定的多晶硅点和带结构。边界定义的多晶硅条带和点形成在NMOS器件的源极和漏极区域之间。在去除牺牲性氮化硅岛之后，边缘限定的多晶硅条和点用于掩蔽常规CMOS工艺中的阈值电压注入。在去除边界限定的多晶硅条纹和点之后，形成传导通道和两个相邻的电位最小点。

7. 发明申请

WO01084634A1 INFORMATION PROCESSING STRUCTURE 审中-公开
标题翻译：信息处理结构
公开(公告)号：WO01084634A1
公开(公告)日：2001-11-08
申请号：PCT/JP2001/002469
申请日：2001-03-27
IPC分类号： H01L21/8247 , G11C11/34 , H01L27/10 , H01L29/06 , H01L29/66 , H01L29/78 , H01L29/788 , H01L29/792
CPC分类号： B82Y10/00 , G11C11/34 , G11C2216/08 , H01L29/7613 , H01L29/7888
摘要： An information processing structure having a single-electron circuit stably operating at high speed by single-electron action is constituted by forming a plurality of quantum dots (13) of a nanometer-scale just above a gate electrode (12) of a microminiaturized MOSFET (11), constructing an energy barrier between the quantum dots and the gate electrode between which electrons can directly tunnel, and representing information by the total number of electrons migrating between the quantum dots and the gate electrode, wherein a power source electrode (14) which serves as a power source is provided in contact with the quantum dots between the quantum dots and the power source electrode (14) in such a way that an energy barrier through which electrons can directly tunnel is structure, two information electrodes (15) are formed in contact with a quantum dot in such a way that the quantum dot and the information electrode are capacitively coupled, and electrons migrate between the power source electrode and the gate electrode through the quantum dots by the Coulomb blockade phenomenon in accordance with the electric potential determined by the information electrodes.
摘要翻译：具有通过单电子作用高速稳定运行的单电子电路的信息处理结构通过在微型化的MOSFET的栅电极（12）的正上方形成纳米级的多个量子点（13）在量子点和栅电极之间构造能量阻挡层，电子可以直接隧穿，并且通过在量子点和栅电极之间迁移的电子的总数来表示信息，其中电源电极（14）用作与量子点和电源电极（14）之间的量子点接触的电源，使得电子可以直接隧道通过的能量势垒为结构，形成两个信息电极（15）以量子点和信息电极电容耦合的方式与量子点接触，并且电子在电源之间迁移电极和栅极通过量子点通过库仑阻塞现象根据由信息电极确定的电位。

8. 发明申请

WO2008127293A2 HIGH DENSITY NANODOT NONVOLATILE MEMORY 审中-公开
标题翻译：高密度纳坦诺非易失性存储器
公开(公告)号：WO2008127293A2
公开(公告)日：2008-10-23
申请号：PCT/US2007022167
申请日：2007-10-17
申请人： MICRON TECHNOLOGY INC , BHATTACHARYYA ARUP , FARNWORTH WARREN M , FARRAR PAUL A
发明人： BHATTACHARYYA ARUP , FARNWORTH WARREN M , FARRAR PAUL A
IPC分类号： H01L21/28 , G11C13/02 , G11C16/04 , H01L21/027 , H01L21/768 , H01L21/8247 , H01L27/115 , H01L27/28 , H01L29/06 , H01L29/423 , H01L29/788 , H01L51/00 , H01L51/05 , H01L51/10
CPC分类号： H01L21/28273 , B82Y10/00 , G11C13/025 , H01L21/76838 , H01L21/76885 , H01L23/53276 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/7613 , H01L29/7881 , H01L29/7888 , H01L51/0048 , H01L2221/1094 , H01L2924/0002 , H01L2924/00
摘要： A nanodot nonvolatile memory element comprises a substrate having a source and a drain region formed therein, and an insulating layer formed on the substrate. The insulating layer contains a nanocrystalline floating gate of approximately three -to six nanometers in diameter formed at a distance of approximately two to five nanometers from the substrate, and a carbon nanotube control gate having a diameter of approximately six nanometers or less is formed at a distance of approximately 10-15 nanometers from the substrate.
摘要翻译：纳米级非易失性存储元件包括其中形成有源区和漏区的衬底，以及形成在衬底上的绝缘层。绝缘层包含大约三至六纳米直径的纳米晶体浮栅，其形成距离衬底大约二至五纳米的距离，并且在一个直径约六纳米或更小的碳纳米管控制栅极上形成距衬底约10-15纳米。

9. 发明申请

WO2004054922A2 NANOSTRUCTURE, ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：纳米结构，电子器件及其制造方法
公开(公告)号：WO2004054922A2
公开(公告)日：2004-07-01
申请号：PCT/JP2003/015948
申请日：2003-12-12
申请人： CANON KABUSHIKI KAISHA , DEN, Tohru , FUKUTANI, Kazuhiko
发明人： DEN, Tohru , FUKUTANI, Kazuhiko
IPC分类号： B82B
CPC分类号： C30B29/60 , B82Y10/00 , B82Y30/00 , H01L29/42332 , H01L29/7888 , H01L2924/0002 , Y10S977/762 , Y10S977/893 , H01L2924/00
摘要： Cylinders having Al as a major constituent are orderly arrayed in an (Si, Ge) matrix. In a nanostructure in the form of a mixture film having a plurality of cylinders having Al as a major constituent, and a matrix region surrounding the plurality of cylinders and having Si and/or Ge as a major constituent, the total amount of Si and Ge is contained in a proportion in the range from 20 to 70 atomic % in the mixture film, the cylinders are orderly arrayed, the diameter of the cylinders is in the range from 1 to 30 nm, and the interval between the cylinders is 30 nm or smaller.
摘要翻译：具有Al作为主要成分的气缸有序排列在（Si，Ge）基体中。在具有以Al为主要成分的多个圆柱体的混合物膜的形式的纳米结构体和围绕多个圆筒的基体区域中，具有Si和/或Ge作为主要成分的Si和Ge的总量在混合膜中以20〜70原子％的比例含有，气缸排列顺序，气缸的直径为1〜30nm，气缸间的间隔为30nm，小。

10. 发明申请

WO01006570A1 NON-VOLATILE SEMICONDUCTOR MEMORY CELL AND METHOD FOR PRODUCING THE SAME 审中-公开
标题翻译： NOT性半导体存储单元和方法生产同样
公开(公告)号：WO01006570A1
公开(公告)日：2001-01-25
申请号：PCT/DE2000/001732
申请日：2000-05-29
IPC分类号： H01L21/28 , H01L29/788
CPC分类号： B82Y10/00 , H01L21/28273 , H01L29/7887 , H01L29/7888
摘要： The invention relates to a non-volatile semiconductor memory cell, comprising a transistor component (2, 3, 6) which is located on a substrate (1) and a memory node which determines the control state of the transistor component (2, 3, 6) and which is located in the vicinity of a control gate electrode (8). The memory node has a group of vertically orientated stack structures (7), comprising at least two semiconductor layer zones (10) and an insulating layer zone (11) which lies between the latter.
摘要翻译：一种非易失性半导体存储单元，其包括一个基底（1）上形成的晶体管装置（2，3，6），并且所述晶体管器件的开关状态（2，3，6）被确定，并且在控制栅电极的附近（8）被布置在存储节点，存储节点具有一组具有至少两个半导体层区域（10）和中间绝缘层区（11）垂直定向的柱结构（7）的。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式