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1. 发明申请

WO2017210143A1 METHOD, APPARATUS, AND SYSTEM FOR CACHE COHERENCY USING A COARSE DIRECTORY 审中-公开
标题翻译：用于使用粗略目录的高速缓存一致性的方法，装置和系统
公开(公告)号：WO2017210143A1
公开(公告)日：2017-12-07
申请号：PCT/US2017/034889
申请日：2017-05-28
申请人： INTEL CORPORATION
发明人： BLANKENSHIP, Robert G. , STEELY, Simon C. , SURY, Samantika S.
IPC分类号： G06F12/02
CPC分类号： G06F3/0605 , G06F3/0625 , G06F3/0659 , G06F3/0673 , G06F12/0808 , G06F12/0811 , G06F12/0815 , G06F12/0824 , G06F12/0826 , G06F12/0831 , G06F12/0842 , G06F2212/1028 , G06F2212/1048 , Y02D10/13
摘要： Systems, methods, and apparatuses are directed to requesting access to a memory address; storing an identification of the memory address in a data structure; receiving a first request for access to the memory address, the request comprising a reference to a second processor core; storing the reference to the second processor in the data structure; receiving a second request for access to the memory address, the second request comprising a reference to a third processor core; determining, based on the data structure, that the third processor core is different from the second processor core; and responding to the second request without buffering the second request.
摘要翻译：系统，方法和设备涉及请求访问存储器地址; 将存储器地址的标识存储在数据结构中; 接收访问所述存储器地址的第一请求，所述请求包括对第二处理器核心的引用; 将对第二处理器的引用存储在数据结构中; 接收访问所述存储器地址的第二请求，所述第二请求包括对第三处理器核心的引用; 基于所述数据结构确定所述第三处理器核不同于所述第二处理器核; 并在不缓冲第二个请求的情况下响应第二个请求。

2. 发明申请

WO2017196614A1 SELECTIVE DATA PERSISTENCE IN COMPUTING SYSTEMS 审中-公开
标题翻译：计算系统中的选择性数据持久性
公开(公告)号：WO2017196614A1
公开(公告)日：2017-11-16
申请号：PCT/US2017/030939
申请日：2017-05-04
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： GABRYJELSKI, Henry
IPC分类号： G06F12/02
CPC分类号： G06F3/0619 , G06F3/0647 , G06F3/0659 , G06F3/067 , G06F3/0685 , G06F12/0246 , G06F2212/1028 , G06F2212/7208 , Y02D10/13
摘要： Embodiments of selective data persistence in computing devices and associated methods of operations are disclosed therein. In one embodiment, a method includes receiving a command to initiate persistence of data currently contained in a volatile memory module to a non-volatile memory module of a hybrid memory device. The method also includes determining whether the data in the volatile memory module is valid data. In response to determining that the data currently contained in the volatile memory module is valid data, causing the data to be copied from the volatile memory module to the non-volatile memory module. in response to determining that the data is not valid data, discarding the data currently contained in the volatile memory module.
摘要翻译：其中公开了计算设备和相关操作方法中的选择性数据持久性的实施例。在一个实施例中，一种方法包括：接收用于启动当前包含在易失性存储器模块中的数据到混合存储器装置的非易失性存储器模块的持久性的命令。该方法还包括确定易失性存储器模块中的数据是否是有效数据。响应于确定当前包含在易失性存储器模块中的数据是有效数据，导致将数据从易失性存储器模块复制到非易失性存储器模块。响应于确定该数据不是有效数据，丢弃当前包含在易失性存储器模块中的数据。

3. 发明申请

WO2017134224A1 CACHE AND METHOD 审中-公开
标题翻译：缓存和方法
公开(公告)号：WO2017134224A1
公开(公告)日：2017-08-10
申请号：PCT/EP2017/052383
申请日：2017-02-03
申请人： SWARM64 AS
发明人： MARTINEZ DE LA TORRE, Alfonso , LILAND, Eivind , RICHTER, Thomas
IPC分类号： G06F12/0864 , G06F12/0895 , G06F12/0897
CPC分类号： G06F12/0864 , G06F12/0804 , G06F12/0895 , G06F12/0897 , G06F2212/1028 , Y02D10/13
摘要： A level-'n' cache and method are disclosed. The level-'n' cache method comprises: in response to a data access request identifying an address of a data block to be accessed, interrogating an address cache of the level-'n' cache arranged to store address portions for a sub-set of data blocks stored in a main cache of the level-'n' cache to determine whether a cache hit occurs within the address cache for the address. In this way, providing the address cache which is separate from the main cache, with the address cache storing address portions relating to data blocks stored in the main cache, the amount of data required to be stored in the address cache is reduced, and decouples the size of the address cache from that of the main cache which enables the address cache to be sized independent of the size of the data blocks stored in the main cache. This provides for a cache of addresses which can be significantly smaller, faster and easily locatable with other components of a data processing apparatus, whilst allowing the data to be stored elsewhere in the main cache which can be larger, slower and more remotely-located from the other components of the data processing apparatus.
摘要翻译：公开了一种级别“n”缓存和方法。级别“n”高速缓存方法包括：响应于标识要访问的数据块的地址的数据访问请求，询问被设置为存储用于子集的地址部分的级别“n”高速缓存的地址高速缓存存储在级别“n”高速缓存的主高速缓存中的数据块，以确定地址高速缓存中是否发生高速缓存命中。以这种方式，提供与主高速缓存分离的地址高速缓存，其中地址高速缓存存储与存储在主高速缓存中的数据块相关的地址部分，减少了需要存储在地址高速缓存中的数据量，并且解耦地址高速缓存的大小与主高速缓存的地址高速缓存的大小相关，这使得地址高速缓存的大小可以独立于主高速缓存中存储的数据块的大小。这提供了可以与数据处理装置的其他组件相比更小，更快和容易定位的地址缓存，同时允许将数据存储在主缓存中的其他地方，该缓存可以更大，更慢和更远距离定位数据处理设备的其他组件。

4. 发明申请

WO2017053087A1 MAINTAINING CACHE COHERENCY USING CONDITIONAL INTERVENTION AMONG MULTIPLE MASTER DEVICES 审中-公开
标题翻译：使用多个主设备的条件干预维护高速缓存
公开(公告)号：WO2017053087A1
公开(公告)日：2017-03-30
申请号：PCT/US2016/050987
申请日：2016-09-09
申请人： QUALCOMM INCORPORATED
发明人： XU, Kun , TRUONG, Thuong, Quang , SUBRAMANIAM GANASAN, Jaya, Prakash , LE, Hien, Minh , RAMIREZ, Cesar, Aaron
IPC分类号： G06F12/0831
CPC分类号： G06F12/0815 , G06F12/0831 , G06F2212/1024 , G06F2212/1028 , G06F2212/621 , Y02D10/13
摘要： Maintaining cache coherency using conditional intervention among multiple master devices is disclosed. In one aspect, a conditional intervention circuit is configured to receive intervention responses from multiple snooping master devices. To select a snooping master device to provide intervention data, the conditional intervention circuit determines how many snooping master devices have a cache line granule size the same as or larger than a requesting master device. If one snooping master device has a same or larger cache line granule size, that snooping master device is selected. If more than one snooping master device has a same or larger cache line granule size, a snooping master device is selected based on an alternate criteria. The intervention responses provided by the unselected snooping master devices are canceled by the conditional intervention circuit, and intervention data from the selected snooping master device is provided to the requesting master device.
摘要翻译：公开了使用多个主设备之间的条件干预来维护高速缓存一致性。在一个方面，条件干预电路被配置为从多个窥探主设备接收干预响应。为了选择窥探主设备来提供干预数据，条件干预电路确定有多少个窥探主设备具有与请求主设备相同或更大的高速缓存线粒度大小。如果一个侦听主设备具有相同或更大的缓存线粒度大小，则选择该窥探主设备。如果多个侦听主设备具有相同或更大的缓存线粒度大小，则会根据备用标准选择侦听主设备。由未选择的窥探主设备提供的干预响应由条件干预电路取消，并且来自所选窥探主设备的干预数据被提供给请求主设备。

5. 发明申请

WO2017014924A1 CONCURRENT ACCESS TO MEMORY SPACE BY MULTIPLE INTERFACES 审中-公开
标题翻译：通过多个接口同时访问存储空间
公开(公告)号：WO2017014924A1
公开(公告)日：2017-01-26
申请号：PCT/US2016/039665
申请日：2016-06-27
申请人： QUALCOMM INCORPORATED
发明人： BAROT, Nitinkumar , LI, Yifan
IPC分类号： G06F13/16 , G06F12/02 , G06F9/50
CPC分类号： G06F3/0611 , G06F3/0644 , G06F3/0685 , G06F9/50 , G06F12/00 , G06F12/02 , G06F12/023 , G06F12/0623 , G06F13/16 , G06F2212/1016 , G06F2212/1028 , G06F2212/205 , G06F2212/601
摘要： System, methods and apparatus are described that facilitate access to a memory device. A memory space within the memory device is divided into a plurality of storage bank domains. Thereafter, application interface circuits configured to access the memory space are classified into a plurality of interface groups based on one or more application usage requirements. Each interface group of the plurality of interface groups is assigned to a corresponding storage bank domain from the plurality of storage bank domains. Access between each interface group and the corresponding storage bank domain is then provided, wherein a first application interface circuit of a first interface group accesses a first corresponding storage bank domain while a second application interface circuit of a second interface group accesses a second corresponding storage bank domain.
摘要翻译：描述了便于访问存储器件的系统，方法和装置。存储器装置内的存储器空间被分成多个存储库域。此后，基于一个或多个应用使用要求将被配置为访问存储器空间的应用接口电路分类为多个接口组。多个接口组中的每个接口组从多个存储库域分配给相应的存储库域。然后提供每个接口组与相应的存储区域之间的接入，其中第一接口组的第一应用接口电路访问第一对应的存储区域，而第二接口组的第二应用接口电路访问第二对应存储体域。

6. 发明申请

WO2016209348A1 THERMAL THROTTLING OF ELECTRONIC DEVICES 审中-公开
标题翻译：电子设备的热转折
公开(公告)号：WO2016209348A1
公开(公告)日：2016-12-29
申请号：PCT/US2016/028849
申请日：2016-04-22
申请人： INTEL CORPORATION
发明人： KAM, Timothy Y. , AHUJA, Sandeep , AGARWAL, Rajat , SODANI, Avinash , SUH, Jinho , CHINTHAMANI, Meenakshisundaram
IPC分类号： G06F1/20
CPC分类号： G06F1/206 , G06F1/3206 , G06F1/3225 , G06F1/3234 , G06F1/324 , G06F1/3275 , G06F2212/1028 , Y02D10/126 , Y02D10/14 , Y02D10/16
摘要： Disclosed herein is a computing device configured to implement thermal throttling of a component of the computing device. The computing device includes an electronic component and a temperature sensor thermally coupled to the electronic component. The computing device also includes a thermal management controller to receive a temperature measurement from the temperature sensor and generate a throttling factor for the electronic component. If the temperature measurement is greater than a specified threshold, the throttling factor is to reduce performance of the electronic component to be at least the performance guarantee for the electronic component.
摘要翻译：这里公开了一种被配置为实现计算设备的部件的热调节的计算设备。计算设备包括热耦合到电子部件的电子部件和温度传感器。计算设备还包括热管理控制器，用于从温度传感器接收温度测量并产生电子部件的节流因子。如果温度测量值大于指定的阈值，则节流因素是将电子元件的性能降至至少为电子元件的性能保证。

7. 发明申请

WO2016175959A1 METHODS AND APPARATUSES FOR MEMORY POWER REDUCTION 审中-公开
标题翻译：用于存储器功率降低的方法和装置
公开(公告)号：WO2016175959A1
公开(公告)日：2016-11-03
申请号：PCT/US2016/024569
申请日：2016-03-28
申请人： QUALCOMM INCORPORATED
发明人： TAHA, Ali , CHUN, Dexter Tamio
IPC分类号： G06F1/32
CPC分类号： G06F1/3275 , G06F1/3287 , G06F2212/1028 , G06F2212/205 , G11C11/406 , G11C14/0009 , G11C14/0054 , Y02D10/13 , Y02D10/14
摘要： Methods and apparatuses for memory power reduction are provided. The apparatus determines whether to store data into a DRAM or an NVRAM during an idle state of a processor based on power consumption by the DRAM in association with refreshing the data in the DRAM and use of the data stored in the DRAM by the processor, based on power consumption by the NVRAM in association with use of the data stored in the NVRAM by the processor, and based on a duty cycle associated with current drawn in a first power state and a second power state in association with the data. The NVRAM is a type of non-volatile random-access memory other than flash memory. The processor stores the data into one of the DRAM or the NVRAM based on the determination whether to store the data in the DRAM or the NVRAM.
摘要翻译：提供了用于存储器功率降低的方法和装置。该设备基于DRAM的功耗与DRAM中的数据相关联以及处理器中存储在DRAM中的数据的使用，确定在处理器的空闲状态期间是否将数据存储到DRAM或NVRAM中关于由处理器使用存储在NVRAM中的数据以及与数据相关联的与第一功率状态和第二功率状态相关联的电流相关联的占空比，NVRAM的功耗。 NVRAM是除闪存之外的一种非易失性随机存取存储器。根据是否将数据存储在DRAM或NVRAM中，处理器将数据存储到DRAM或NVRAM中的一个中。

8. 发明申请

WO2016175842A1 RETRIEVE DATA BLOCK FROM DETERMINED DEVICES 审中-公开
标题翻译：从确定的设备检索数据块
公开(公告)号：WO2016175842A1
公开(公告)日：2016-11-03
申请号：PCT/US2015/028576
申请日：2015-04-30
申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
发明人： BALASUBRAMONIAN, Rajeev , FARABOSCHI, Paolo , LESARTRE, Gregg B. , MURALIMANOHAR, Naveen
IPC分类号： G06F12/06 , G06F12/08
CPC分类号： G06F3/064 , G06F3/061 , G06F3/0656 , G06F3/0683 , G06F11/1048 , G06F11/1068 , G06F12/0238 , G06F12/1408 , G06F2212/1028 , G06F2212/1044 , G06F2212/401 , G06F2212/7208 , G11C29/52 , Y02D10/13
摘要： Techniques for retrieving data blocks from memory devices are provided. In one aspect, a request to retrieve a block of data may be received. The block of data may be in a line in a rank of memory. The rank of memory may include multiple devices. The devices used to store the line in the rank of memory may be determined. The determined devices may be read.
摘要翻译：提供了从存储器件检索数据块的技术。在一个方面，可以接收到检索数据块的请求。数据块可能处于存储器等级的行中。存储器的等级可以包括多个设备。可以确定用于将行存储在存储器等级中的装置。可以读取所确定的设备。

9. 发明申请

WO2016122657A1 ORDERING UPDATES FOR NONVOLATILE MEMORY ACCESSES 审中-公开
标题翻译：订购非易失性存储器访问的更新
公开(公告)号：WO2016122657A1
公开(公告)日：2016-08-04
申请号：PCT/US2015/013958
申请日：2015-01-30
申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
发明人： NALLI, Sanketh , VOLOS, Haris , KEETON, Kimberly
IPC分类号： G06F12/08
CPC分类号： G06F12/0238 , G06F12/0804 , G06F12/0868 , G06F2212/1028 , G06F2212/1032 , G06F2212/7203 , Y02D10/13
摘要： Examples relate to ordering updates for nonvolatile memory accesses. In some examples, a first update that is propagated from a write-through processor cache of a processor is received by a write ordering buffer, where the first update is associated with a first epoch. The first update is stored in a first buffer entry of the write ordering buffer. At this stage, a second update that is propagated from the write-through processor cache is received, where the second update is associated with a second epoch. A second buffer entry of the write ordering buffer is allocated to store the second update. The first buffer entry and the second buffer entry can then be evicted to non-volatile memory in epoch order.
摘要翻译：示例涉及非易失性存储器访问的排序更新。在一些示例中，由处理器的直写处理器高速缓存传播的第一更新由写入顺序缓冲器接收，其中第一更新与第一历元相关联。第一更新被存储在写顺序缓冲器的第一缓冲器条目中。在此阶段，接收从直通处理器高速缓存传播的第二更新，其中第二更新与第二时期相关联。分配写入顺序缓冲器的第二缓冲器条目以存储第二更新。第一个缓冲区条目和第二个缓冲区条目可以按照时序顺序移交给非易失性存储器。

10. 发明申请

WO2016114961A1 SYSTEMS AND METHODS FOR PROVIDING DYNAMIC CACHE EXTENSION IN A MULTI-CLUSTER HETEROGENEOUS PROCESSOR ARCHITECTURE 审中-公开
标题翻译：用于在多集群异构处理器架构中提供动态缓存扩展的系统和方法
公开(公告)号：WO2016114961A1
公开(公告)日：2016-07-21
申请号：PCT/US2016/012374
申请日：2016-01-06
申请人： QUALCOMM INCORPORATED
发明人： PARK, Hee Jun , VANKA, Krishna Vsssr , AMBAPURAM, Sravan Kumar , AGARWAL, Shirish Kumar , NAMJOSHI, Ashvinkumar , BHUTADA, Harshad
IPC分类号： G06F9/50 , G06F12/08
CPC分类号： G06F12/084 , G06F9/4856 , G06F9/5016 , G06F11/34 , G06F11/3433 , G06F12/0806 , G06F12/0811 , G06F12/0833 , G06F12/0842 , G06F2212/1021 , G06F2212/1028 , G06F2212/601 , Y02D10/13
摘要： A dynamic cache extension in a multi-cluster heterogeneous processor architecture is described: a system includes a first processor cluster having a first level two (L2) cache and a second processor cluster having a second L2 cache. The system further comprises a controller in communication with the first and second L2 caches. The controller receives a processor workload input and a cache workload input from the first processor cluster. Based on processor workload input and the cache workload input, the cache controller determines whether a current task associated with the first processor cluster is limited by a size threshold of the first L2 cache or a performance threshold of the first processor cluster. If the current task is limited by the size threshold of the first L2 cache, the controller uses at least a portion of the second L2 cache as an extension of the first L2 cache.
摘要翻译：描述了在多集群异构处理器架构中的动态高速缓存扩展：系统包括具有第一级（L2）高速缓存的第一处理器集群和具有第二L2高速缓存的第二处理器集群。该系统还包括与第一和第二L2高速缓存通信的控制器。控制器从第一处理器集群接收处理器工作负载输入和高速缓存工作负载输入。基于处理器工作负载输入和缓存工作负荷输入，高速缓存控制器确定与第一处理器集群相关联的当前任务是否受到第一L2高速缓存的大小阈值或第一处理器集群的性能阈值的限制。如果当前任务受到第一L2高速缓存的大小阈值的限制，则控制器使用第二L2高速缓存的至少一部分作为第一L2高速缓存的扩展。

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