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    • 2. 发明申请
    • SOFTWARE-DEFINED POWER MANAGEMENT FOR NETWORK RESOURCES
    • 用于网络资源的软件定义的电源管理
    • WO2017009689A1
    • 2017-01-19
    • PCT/IB2015/055362
    • 2015-07-15
    • TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)ERICSSON TELECOMUNICACOES S.A.
    • MEIROSU, CatalinMELO DE BRITO CARVALHO, Tereza CristinaRIEKSTIN, Ana CarolinaRODRIGUES, Bruno BastosTAVARES NASCIMENTO, Viviane
    • G06F1/32H04L12/24
    • G06F1/3203G06F1/3209G06F1/3234G06F1/3278H04L41/0833Y02D10/157
    • A method of power management in a compute environment (200) having a compute part and a network part. The method includes a step of defining various energy policies (gp) for the network part, the energy policies having assigned a different amount of virtual currency; a step of assigning, in a virtual power controller (320), based on an energy policy selected by a user (301), a service function (342) required by the user, and network resources (408) to be consumed by the service function, a corresponding amount of virtual currency; a step of configuring a set of energy saving capabilities to be deployed on the network resources (408) based on the energy policy selected by the user and the corresponding amount of virtual currency; a step of monitoring power consumption of the service function (342) with a policy enforcement utility (332) that is aware of the selected energy policy; and a step of adjusting an amount of actual electric power used by network resources (408) that support the service function (342) depending on a result of the monitoring step.
    • 一种具有计算部分和网络部分的计算环境(200)中的电力管理方法。 该方法包括为网络部分定义各种能量策略(gp)的步骤,能量策略已经分配了不同量的虚拟货币; 在虚拟功率控制器(320)中基于由用户(301)选择的能量策略,用户所需的服务功能(342)以及服务所消耗的网络资源(408)在虚拟功率控制器(320) 功能,相应量的虚拟货币; 基于由用户选择的能量策略和相应量的虚拟货币,配置要部署在网络资源(408)上的一组节能功能的步骤; 通过知道所选择的能量策略的策略执行实用程序(332)监视服务功能(342)的功耗的步骤; 以及根据监视步骤的结果调整支持服务功能(342)的网络资源(408)使用的实际电力量的步骤。
    • 3. 发明申请
    • POWER-GOOD DETECTOR FOR ULTRA-WIDE BAND TRANSMITTER WITH EMPHASIS ON LOW POWER CONSUMPTION
    • 用于超低功耗的超宽带发射机的优质探测器
    • WO2016176492A1
    • 2016-11-03
    • PCT/US2016/029858
    • 2016-04-28
    • MAXIM INTEGRATED PRODUCTS, INC.
    • MUTHALI, Harish, S.PAHLAVAN, KouroshVAUHKONEN, Ari
    • H04B1/04H04B1/62
    • H04B1/04G01R31/31725G06F1/3234H04B1/0475H04B1/71632H04B1/7174
    • Systems, devices and methods are disclosed using a transmitter architecture to keep the transmitter in a deep sleep mode before activation/enabling. The transmitter tag comprises a power- good-detector, a first regulator and a second regulator. The power-good-detector includes a power- good-latch, a ring oscillator and a ripple counter. Upon disconnecting a GPIO pin from the ground, the power-good-latch sends a Bias_EN signal to the regulator. Upon receipt of the Bias_EN signal, the first regulator transmits a wakeup signal to the ring oscillator, which then starts sending the clock signals to the ripple counter. When the counted clock signals reach a a threshold value, the ripple counter sends the power-good-digital signal to the flip flops. When the tag is in the reset mode, the power-good-digital signal is also low. When the power-good-digital signal goes from low to high, the tag is out of the reset mode.
    • 使用发射机架构公开了系统,设备和方法,以在激活/启用之前保持发射机处于深度睡眠模式。 发射器标签包括功率良好检测器,第一调节器和第二调节器。 电源良好检测器包括电源锁存器,环形振荡器和纹波计数器。 在将GPIO引脚与地线断开连接后,电源锁存器会向调节器发送一个Bias_EN信号。 当接收到Bias_EN信号时,第一调节器向环形振荡器发送一个唤醒信号,然后该振荡器开始向纹波计数器发送时钟信号。 当计数的时钟信号达到阈值时,纹波计数器将电源良好数字信号发送到触发器。 当标签处于复位模式时,电源良好数字信号也很低。 当电源良好数字信号从低电平变为高电平时,标签不在复位模式。
    • 4. 发明申请
    • SELECTIVE COUPLING OF POWER RAILS TO A MEMORY DOMAIN(S) IN A PROCESSOR-BASED SYSTEM
    • 电力轨道的选择性耦合到基于处理器的系统中的存储器域
    • WO2016168238A1
    • 2016-10-20
    • PCT/US2016/027197
    • 2016-04-13
    • QUALCOMM INCORPORATED
    • KOLLA, Yeshwant, NagarajNATEKAR, Neel, Shashank
    • G06F1/32G11C5/14G06F1/26
    • G06F1/3234G06F1/263G06F1/3287G11C5/063G11C5/147Y02D10/171
    • Selective coupling of power rails to memory domain(s) in processor-based system, such as to reduce or avoid the need to provide intentional decoupling capacitance in logic domain(s) is disclosed. To avoid or reduce providing additional intentional decoupling capacitance in logic domain to mitigate voltage droops on logic power rail, power rail selection circuit is provided. The power rail selection circuit is configured to couple memory domain to a logic power rail when the logic power rail can satisfy a minimum operating voltage of memory arrays. The additional intrinsic decoupling capacitance of the memory arrays is coupled to the logic power rail. However, if the operating voltage of the logic power rail is scaled down below the minimum operating voltage of the memory arrays when the logic domain does not need higher operation functionality, the power rail selection circuit is configured to couple the memory domain to separate memory power rail.
    • 公开了将电源轨与基于处理器的系统中的存储器域的选择性耦合,例如减少或避免在逻辑域中提供有意的去耦电容的需要。 为了避免或减少在逻辑域中提供额外的故意去耦电容以减轻逻辑电源轨上的电压下降,提供了电力轨道选择电路。 电源轨选择电路被配置为当逻辑电源轨可以满足存储器阵列的最小工作电压时将存储器域耦合到逻辑电源轨。 存储器阵列的附加固有解耦电容耦合到逻辑电源轨。 然而,如果当逻辑域不需要更高的操作功能时,如果逻辑电源轨的工作电压按比例缩小到存储器阵列的最小工作电压以下,则电源轨选择电路被配置为将存储器域耦合到分离的存储器电源 轨。
    • 6. 发明申请
    • PROCESSOR INCLUDING MULTIPLE DISSIMILAR PROCESSOR CORES
    • 处理器包括多个二极管加工器
    • WO2016081089A1
    • 2016-05-26
    • PCT/US2015/054993
    • 2015-10-09
    • APPLE INC.
    • WILLIAMSON, David, J.WILLIAMS, Gerard, R., III
    • G06F1/32
    • G06F1/3293G06F1/3206G06F1/3234G06F1/3287G06F1/3296G06F9/461Y02B70/123Y02D10/172Y02D10/30
    • In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. For example, a core may be implemented for high performance, but may have higher minimum voltage. Another core may be implemented at a lower maximum performance, but may be optimized for efficiency and may operate correctly at a lower minimum voltage. The processor may support multiple processor states (PStates). Each PState may specify an operating point and may be mapped to one of the processor cores. During operation, one of the cores is active: the core to which the current PState is mapped. If a new PState is selected and is mapped to a different core, the processor may automatically context switch the processor state to the newly-selected core and may begin execution on that core.
    • 在一个实施例中,集成电路可以包括一个或多个处理器。 每个处理器可以包括多个处理器核心,并且每个核心具有不同的设计/实现和性能水平。 例如,可以实现用于高性能的核,但是可以具有较高的最小电压。 另一个核心可以以较低的最大性能来实现,但是可以针对效率进行优化,并且可以在较低的最小电压下正确地操作。 处理器可以支持多种处理器状态(PState)。 每个PState可以指定一个工作点并且可以映射到一个处理器核心。 在运行期间,其中一个核心是活动的:当前PState映射到的核心。 如果选择新的PState并将其映射到不同的核心,则处理器可以自动地将处理器状态切换到新选择的核心,并且可以在该核心上开始执行。
    • 7. 发明申请
    • THERMAL MITIGATION BASED ON PREDICATED TEMPERATURES
    • 基于预测温度的热减压
    • WO2016073088A1
    • 2016-05-12
    • PCT/US2015/053593
    • 2015-10-01
    • QUALCOMM INCORPORATED
    • CHANDRA, Rajit
    • G06F1/20G06F1/32
    • G06F1/206G05B13/048G06F1/3234
    • An apparatus is presented. The apparatus includes a first circuit configured to predict temperatures of a location for a plurality of time instances based on measured temperatures and a second circuit configured to schedule a thermal mitigation function based on the predicted temperatures. A method of operating an apparatus is presented. The method includes measuring temperatures on an integrated circuit, predicting temperatures of a location for a plurality of time instances based on the measured temperatures, and scheduling a thermal mitigation function based on the predicted temperatures. An apparatus is presented. The apparatus includes means for measuring temperatures on an integrated circuit, means for predicting temperatures of a location for a plurality of time instances based on measured temperatures, and means for scheduling a thermal mitigation function based on the predicted temperatures.
    • 提出了一种装置。 该装置包括第一电路,其被配置为基于测量的温度来预测多个时间实例的位置的温度,以及第二电路,其被配置为基于预测的温度调度热缓解功能。 提出了一种操作装置的方法。 该方法包括测量集成电路上的温度,基于测量的温度预测多个时间段的位置的温度,以及基于预测的温度调度热减缓功能。 提出了一种装置。 该装置包括用于测量集成电路上的温度的装置,用于基于测量的温度预测多个时间实例中的位置的温度的装置,以及用于基于预测温度调度热缓解功能的装置。