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1. 发明申请

WO2022226486A1 PROCESSOR SUPPORT FOR USING MEMORY PAGE MARKINGS AS LOGGING CUES TO SIMULTANEOUSLY RECORD PLURAL EXECUTION CONTEXTS INTO INDEPENDENT EXECUTION TRACES 审中-公开
公开(公告)号：WO2022226486A1
公开(公告)日：2022-10-27
申请号：PCT/US2022/071782
申请日：2022-04-18
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： MOLA, Jordi
IPC分类号： G06F12/02 , G06F11/34 , G06F11/36 , G06F12/0842 , G06F12/0864 , G06F12/0895 , G06F12/126
摘要： Using memory markings to record plural execution contexts into independent traces. A processor detects a memory operation and identifies an associated memory marking from among a first marking indicating that a first memory region is logged for the first context, and a second marking indicating that a second memory region is logged for a second context. Based on identifying the memory marking as the second marking, and based the first context causing the memory operation, the processor performs at least one of: when the memory operation causes an influx into a cache, logging the influx to a second trace associated with the second context; when the memory operation is a read, logging the read to a first trace associated with the first context; or when the memory operation is a write, performing one of logging the write to the second trace, or evicting a target cache line.

2. 发明申请

WO2021021489A1 CACHE SYSTEMS AND CIRCUITS FOR SYNCING CACHES OR CACHE SETS 审中-公开
公开(公告)号：WO2021021489A1
公开(公告)日：2021-02-04
申请号：PCT/US2020/042852
申请日：2020-07-21
申请人： MICRON TECHNOLOGY, INC.
发明人： WALLACH, Steven Jeffrey
IPC分类号： G06F12/0864 , G06F12/0831 , G06F12/0875 , G06F12/0897 , G06F9/38
摘要： A cache system, having a first cache, a second cache, and a logic circuit coupled to control the first cache and the second cache according to an execution type of a processor. When an execution type of a processor is a first type indicating non-speculative execution of instructions and the first cache is configured to service commands from a command bus for accessing a memory system, the logic circuit is configured to copy a portion of content cached in the first cache to the second cache. The cache system can include a configurable data bit. The logic circuit can be coupled to control the caches according to the bit. Alternatively, the caches can include cache sets. The caches can also include registers associated with the cache sets respectively. The logic circuit can be coupled to control the cache sets according to the registers.

3. 发明申请

WO2020131434A1 DATA INTEGRITY PROTECTION FOR RELOCATING DATA IN A MEMORY SYSTEM 审中-公开
公开(公告)号：WO2020131434A1
公开(公告)日：2020-06-25
申请号：PCT/US2019/064986
申请日：2019-12-06
申请人： MICRON TECHNOLOGY, INC.
发明人： BISSEY, Lucien J.
IPC分类号： G06F21/64 , G06F21/78 , G06F12/02 , G06F12/0864 , G06F12/14
摘要： Methods, apparatuses, and systems related to data management and security in a memory device are described. Data may be stored in a memory system, and as part of an operation to move data from one region to another in the memory system, the data may be validated using one or more hash functions. For example, a memory device may compute a hash value of some stored data, and use the hash value to validate another version of that stored data in the process of writing the other version stored data to a region of the memory system. The memory device may store another hash that is generated from the hash of the stored data and a record of transactions such that transactions are identifiable; the sequence of transactions within the memory system may also be identifiable. Hashes of transactions may be stored throughout the memory system or among memory systems.

4. 发明申请

WO2019138206A1 SPECULATIVE CACHE STORAGE REGION 审中-公开
公开(公告)号：WO2019138206A1
公开(公告)日：2019-07-18
申请号：PCT/GB2018/052449
申请日：2018-08-30
申请人： ARM LIMITED
发明人： GRISENTHWAITE, Richard Roy
IPC分类号： G06F12/0888 , G06F12/0897 , G06F12/126 , G06F12/0804 , G06F12/0846 , G06F12/0864 , G06F12/14 , G06F12/0862 , G06F9/38 , G06F21/57 , G06F21/75 , G06F12/0815
摘要： An apparatus (2) comprises processing circuitry (4) to perform speculative execution of instructions;a main cache storage region (30);a speculative cache storage region (32); and cache control circuitry (34) to allocate an entry, for which allocation is caused by a speculative memory access triggered by the processing circuitry, to the speculative cache storage region instead of the main cache storage region while the speculative memory access remains speculative.This can help protect against potential security attacks which exploit cache timing side-channels to gain information about allocations into the cache caused by speculative memory accesses.

5. 发明申请

WO2018063916A1 AREA EFFICIENT ARCHITECTURE FOR MULTI WAY READ ON HIGHLY ASSOCIATIVE CONTENT ADDRESSABLE MEMORY (CAM) ARRAYS 审中-公开
标题翻译：高度协作的内容可寻址存储器（CAM）阵列多区域读取的区域高效体系结构
公开(公告)号：WO2018063916A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/052752
申请日：2017-09-21
申请人： QUALCOMM INCORPORATED
发明人： SHANKAR, Harish , GARG, Manish
IPC分类号： G06F12/0864 , G06F12/0895 , G11C15/04
摘要： Aspects disclosed herein relate to techniques and an efficient architecture for enabling multi-way reads on highly associative content addressable memory (CAM) arrays. For example, a method for performing a tag search of a tag array can include reading a first subset of stored tag bits from multiple entries of the tag array, and comparing a second subset of stored tag bits from a one or more entries of the tag array against a search-tag to produce one or more possible way hit signals.
摘要翻译：这里公开的方面涉及用于在高度关联内容可寻址存储器（CAM）阵列上启用多路读取的技术和高效体系结构。例如，用于执行标签阵列的标签搜索的方法可以包括：从标签阵列的多个条目中读取存储的标签位的第一子集，以及比较来自标签的一个或多个条目的存储的标签位的第二子集数组与搜索标记进行比较，以产生一种或多种可能的方式点击信号。

6. 发明申请

WO2017134224A1 CACHE AND METHOD 审中-公开
标题翻译：缓存和方法
公开(公告)号：WO2017134224A1
公开(公告)日：2017-08-10
申请号：PCT/EP2017/052383
申请日：2017-02-03
申请人： SWARM64 AS
发明人： MARTINEZ DE LA TORRE, Alfonso , LILAND, Eivind , RICHTER, Thomas
IPC分类号： G06F12/0864 , G06F12/0895 , G06F12/0897
CPC分类号： G06F12/0864 , G06F12/0804 , G06F12/0895 , G06F12/0897 , G06F2212/1028 , Y02D10/13
摘要： A level-'n' cache and method are disclosed. The level-'n' cache method comprises: in response to a data access request identifying an address of a data block to be accessed, interrogating an address cache of the level-'n' cache arranged to store address portions for a sub-set of data blocks stored in a main cache of the level-'n' cache to determine whether a cache hit occurs within the address cache for the address. In this way, providing the address cache which is separate from the main cache, with the address cache storing address portions relating to data blocks stored in the main cache, the amount of data required to be stored in the address cache is reduced, and decouples the size of the address cache from that of the main cache which enables the address cache to be sized independent of the size of the data blocks stored in the main cache. This provides for a cache of addresses which can be significantly smaller, faster and easily locatable with other components of a data processing apparatus, whilst allowing the data to be stored elsewhere in the main cache which can be larger, slower and more remotely-located from the other components of the data processing apparatus.
摘要翻译：公开了一种级别“n”缓存和方法。级别“n”高速缓存方法包括：响应于标识要访问的数据块的地址的数据访问请求，询问被设置为存储用于子集的地址部分的级别“n”高速缓存的地址高速缓存存储在级别“n”高速缓存的主高速缓存中的数据块，以确定地址高速缓存中是否发生高速缓存命中。以这种方式，提供与主高速缓存分离的地址高速缓存，其中地址高速缓存存储与存储在主高速缓存中的数据块相关的地址部分，减少了需要存储在地址高速缓存中的数据量，并且解耦地址高速缓存的大小与主高速缓存的地址高速缓存的大小相关，这使得地址高速缓存的大小可以独立于主高速缓存中存储的数据块的大小。这提供了可以与数据处理装置的其他组件相比更小，更快和容易定位的地址缓存，同时允许将数据存储在主缓存中的其他地方，该缓存可以更大，更慢和更远距离定位数据处理设备的其他组件。

7. 发明申请

WO2021021445A1 CACHE WITH SET ASSOCIATIVITY HAVING DATA DEFINED CACHE SETS 审中-公开
公开(公告)号：WO2021021445A1
公开(公告)日：2021-02-04
申请号：PCT/US2020/042168
申请日：2020-07-15
申请人： MICRON TECHNOLOGY, INC.
发明人： WALLACH, Steven Jeffrey
IPC分类号： G06F12/0864 , G06F12/0897 , G06F9/38 , G06F12/0831
摘要： A cache system, having: a first cache set; a second cache set; and a logic circuit coupled to a processor to control the caches based on at least respective first and second registers. When a connection to an address bus receives a memory address from the processor, the logic circuit is configured to: generate a set index from at least the address; and determine whether the generated set index matches with a content stored in the first register or with a content stored in the second register. And, the logic circuit is configured to implement a command via the first cache set in response to the generated set index matching with the content stored in the first register and via the second cache set in response to the generated set index matching with the content stored in the second register.

8. 发明申请

WO2020068669A1 HOST-RESIDENT TRANSLATION LAYER VALIDITY CHECK TECHNIQUES 审中-公开
公开(公告)号：WO2020068669A1
公开(公告)日：2020-04-02
申请号：PCT/US2019/052435
申请日：2019-09-23
申请人： MICRON TECHNOLOGY, INC.
发明人： GROSZ, Nadav
IPC分类号： G06F3/06 , G06F12/02 , G06F12/0864 , G06F12/1018
摘要： Devices and techniques are disclosed herein for verifying host generated physical addresses at a memory device during a host-resident FTL mode of operation to ameliorate erroneous or potentially malicious access to the memory device by receiving an operation command comprising a first signature and a PBA from host device at a memory device, generating a second signature, comparing the first signature with the second signature, executing the operation when a match result indicates the first signature is the same as the second signature, and not executing the operation using the PBA when the match result indicates the first signature does not match the second signature.

9. 发明申请

WO2019245445A1 MEMORY ALLOCATION IN A HIERARCHICAL MEMORY SYSTEM 审中-公开
公开(公告)号：WO2019245445A1
公开(公告)日：2019-12-26
申请号：PCT/SE2019/050596
申请日：2019-06-20
申请人： TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
发明人： ROOZBEH, Amir , KOSTIC, Dejan , MAGUIRE JR, Gerald Q , FARSHIN, Alireza
IPC分类号： G06F12/084 , G06F12/0864
摘要： A memory allocator in a computer system comprising a plurality of CPU cores (5101-5104) and a first (530) and a second (5120) memory unit having different data access times and wherein each one of the first and the second memory units is divided into memory portions wherein each memory portion (SLICE 0-3) in the second memory unit is associated with at least one memory portion (A- G) in the first memory unit, and wherein each memory portion in the second memory unit is associated with a CPU core. If at least a predetermined number of memory portions in the first memory unit being part of the available requested memory is associated with the memory portion in the second memory unit that is associated with the CPU core on which the requesting application is running, the requested available memory is allocated to the requesting application.

10. 发明申请

WO2019067937A1 METHOD FOR READING DATA STORED IN A NON-VOLATILE CACHE USING RDMA 审中-公开
公开(公告)号：WO2019067937A1
公开(公告)日：2019-04-04
申请号：PCT/US2018/053487
申请日：2018-09-28
申请人： ORACLE INTERNATIONAL CORPORATION
发明人： TAO, Zuoyo , SHI, Jia , UMAMAGESWARAN, Kothanda , LOAIZA, Juan R.
IPC分类号： G06F12/0864 , G06F12/0868
摘要： Data blocks are cached in a persistent cache ("NV cache") allocated from as non-volatile RAM ("NVRAM"). The data blocks may be accessed in place in the NV cache of a "source" computing element by another "remote" computing element over a network using remote direct memory access ("RMDA"). In order for a remote computing element to access the data block in NV cache on a source computing element, the remote computing element needs the memory address of the data block within the NV cache. For this purpose, a hash table is stored and maintained in RAM on the source computing element. The hash table identifies the data blocks in the NV cache and specifies a location of the cached data block within the NV cache.

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