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1. 发明申请

WO03032187A2 MULTIPLY-ACCUMULATE (MAC) UNIT FOR SINGLE-INSTRUCTION/MULTIPLE-DATA (SIMD) INSTRUCTIONS 审中-公开
标题翻译：用于单指令/多数据（SIMD）指令的多累加（MAC）单元
公开(公告)号：WO03032187A2
公开(公告)日：2003-04-17
申请号：PCT/US0231412
申请日：2002-10-03
申请人： INTEL CORP
发明人： STRAZDUS STEPHEN , LIAO YUYUN , JEBSON ANTHONY , PAVER NIGEL , DENG DELI
IPC分类号： G06F17/10 , G06F7/52 , G06F7/53 , G06F7/533 , G06F7/544 , G06F15/78
CPC分类号： G06F7/5443 , G06F7/5318 , G06F7/5324 , G06F7/5338 , G06F2207/382 , G06F2207/3828 , G06F2207/3884
摘要： A tightly coupled dual 16-bit multiply-accumulate (MAC) unit for performing single-instruction/multiple-data (SIMD) operations may forward an intermediate result to another operation in a pipeline to resolve an accumulating dependency penalty. The MAC unit may also be used to perform 32-bit X 32-bit operations.
摘要翻译：用于执行单指令/多数据（SIMD）操作的紧密耦合的双16位乘法累加（MAC）单元可以将中间结果转发到管道中的另一操作以解决累积依赖性惩罚。 MAC单元也可用于执行32位X 32位操作。

2. 发明申请

WO2002071246A2 AN APPARATUS FOR CONTROLLING ACCESS IN A DATA PROCESSOR 审中-公开
标题翻译：用于控制数据处理器中的访问的装置
公开(公告)号：WO2002071246A2
公开(公告)日：2002-09-12
申请号：PCT/CA2002/000299
申请日：2002-03-04
申请人： ATSANA SEMICONDUCTOR CORP. , STEWART, Malcolm , GIERNALCZYK, Eric , BERIAULT, Richard
发明人： STEWART, Malcolm , GIERNALCZYK, Eric , BERIAULT, Richard
IPC分类号： G06F15/173
CPC分类号： G06F7/575 , G06F9/30036 , G06F13/1663 , G06F15/17337 , G06F15/17375 , G06F15/8015 , G06F2207/382 , G06F2207/3828
摘要： A data processor comprises an array of processor elements and a memory accessible by each processor element. An array of switching elements is provided, each associated with a processor element, the switching elements being interconnected to enable data to be transferred between different segments of memory associated with different processor elements or between different processor elements in the array.
摘要翻译：数据处理器包括处理器元件的阵列和每个处理器元件可访问的存储器。提供了一组开关元件，每个开关元件与处理器元件相关联，所述开关元件互连以使数据能够在与不同处理器元件相关联的不同存储器段之间或在阵列中的不同处理器元件之间传送。

3. 发明申请

WO0045251A3 FLOATING AND PARALLEL FIXED POINT SQUARE ROOT AND RECIPROCAL POINT SQUARE COMPUTATION UNIT IN A PROCESSOR 审中-公开
标题翻译：浮动和平行固定点平方根和加工点的圆点计算单元
公开(公告)号：WO0045251A3
公开(公告)日：2000-12-14
申请号：PCT/US0001578
申请日：2000-01-24
申请人： SUN MICROSYSTEMS INC
发明人： SHANKAR RAVI , SUDHARSANAN SUBRAMANIA I
IPC分类号： G06F1/035 , G06F7/552 , G06F9/30 , G06F9/302 , G06F9/38
CPC分类号： G06F9/30014 , G06F1/0356 , G06F7/483 , G06F7/5525 , G06F9/30036 , G06F9/30098 , G06F9/3012 , G06F9/3838 , G06F9/3853 , G06F9/3877 , G06F9/3885 , G06F2101/08 , G06F2207/3824 , G06F2207/3828 , G06F2207/5521
摘要： A parallel fixed-point square root and reciprocal square root computation uses the same coefficient tables as the floating point square root and reciprocal square root computation by converting the fixed-point numbers into a floating-point structure with a leading implicit 1. The value of a number X is stored as two fixed-point numbers. In one embodiment, the fixed-point numbers are converted to the special floating-point structure using a leading zero detector and a shifter. Following the square root computation or the reciprocal square root computation, the floating point result is shifted back into the two-entry fixed-point format. The shift count is determined by the number of leaded zeros detected during the conversion from fixed-point to floating-point format.
摘要翻译：平行定点平方根和倒数平方根计算使用与浮点平方根和倒数平方根计算相同的系数表，将固定点数转换成具有前导隐含的浮点结构。数字X被存储为两个定点数。在一个实施例中，使用前导零检测器和移位器将定点数转换为特殊浮点结构。在平方根计算或倒数平方根计算之后，浮点结果被移回到双入口定点格式。移位计数由在从定点到浮点格式的转换期间检测到的引导零的数量来确定。

4. 发明申请

WO9944329A2 ENCRYPTION PROCESSOR WITH SHARED MEMORY INTERCONNECT 审中-公开
标题翻译：具有共享内存互连的加密处理器
公开(公告)号：WO9944329A2
公开(公告)日：1999-09-02
申请号：PCT/CA9900176
申请日：1999-02-26
申请人： MOSAID TECHNOLOGIES INC
发明人： JONES DAVID E , O'CONNELL CORMAC M
IPC分类号： G06F13/36 , G06F7/50 , G06F7/52 , G06F7/72 , G09C1/00 , H04L9/00 , H04L9/06 , H04L9/30
CPC分类号： G06F7/5324 , G06F7/49931 , G06F7/5052 , G06F7/72 , G06F7/722 , G06F2207/382 , G06F2207/3828 , H04L9/14 , H04L2209/125
摘要： An encryption chip is programmable to process a variety of secret key and public key encryption algorithms. The chip includes a pipeline of processing elements, each of which can process a round within a secret key algorithm. Data is transferred between the processing elements through dual port memories. A central processing unit allows for processing of very wide data words from global memory in single cycle operations. An adder circuit is simplified by using plural relatively small adder circuits with sums and carries looped back in plural cycles. Multiplier circuitry can be shared between the processing elements and the central processor by adapting the smaller processing element multipliers for concatenation as a very wide central processor multiplier.
摘要翻译：加密芯片是可编程的，用于处理各种秘密密钥和公钥加密算法。该芯片包括处理元件的流水线，每个处理元件可以在秘密密钥算法内处理一轮。通过双端口存储器在处理元件之间传送数据。中央处理单元允许在单周期操作中处理来自全局存储器的非常宽的数据字。通过使用多个具有和的相对较小的加法器电路来简化加法器电路，并在多个周期中循环运行。乘法器电路可以通过将较小的处理单元乘法器适配为级联，作为非常宽的中央处理器乘法器，在处理元件和中央处理器之间共享。

5. 发明申请

WO02071246A3 AN APPARATUS FOR CONTROLLING ACCESS IN A DATA PROCESSOR 审中-公开
标题翻译：用于控制数据处理器中的访问的装置
公开(公告)号：WO02071246A3
公开(公告)日：2003-05-15
申请号：PCT/CA0200299
申请日：2002-03-04
申请人： ATSANA SEMICONDUCTOR CORP , STEWART MALCOLM , GIERNALCZYK ERIC , BERIAULT RICHARD
发明人： STEWART MALCOLM , GIERNALCZYK ERIC , BERIAULT RICHARD
IPC分类号： G06F3/00 , G06F7/575 , G06F9/302 , G06F13/16 , G06F15/173 , G06F15/80
CPC分类号： G06F7/575 , G06F9/30036 , G06F13/1663 , G06F15/17337 , G06F15/17375 , G06F15/8015 , G06F2207/382 , G06F2207/3828
摘要： A data processor comprises an array of processor elements and a memory accessible by each processor element. An array of switching elements is provided, each associated with a processor element, the switching elements being interconnected to enable data to be transferred between different segments of memory associated with different processor elements or between different processor elements in the array.
摘要翻译：数据处理器包括处理器元件的阵列和每个处理器元件可访问的存储器。提供了一组开关元件，每个开关元件与处理器元件相关联，所述开关元件互连以使数据能够在与不同处理器元件相关联的不同存储器段之间或在阵列中的不同处理器元件之间传送。

6. 发明申请

WO2003029954A2 SPLIT MULTIPLIER FOR EFFICIENT MIXED-PRECISION DSP 审中-公开
标题翻译：有效的混合精密DSP的分路器
公开(公告)号：WO2003029954A2
公开(公告)日：2003-04-10
申请号：PCT/IB2002/004035
申请日：2002-09-30
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V.
发明人： BURNS, Geoffrey, F.
IPC分类号： G06F7/00
CPC分类号： G06F7/5324 , G06F2207/382 , G06F2207/3828
摘要： A method and architecture with which to achieve efficient sub-word parallelism for multiplication resources is presented. In a preferred embodiment, a dual two's complement multiplier is presented, such that an n bit operandB can be split, and each portion of the operand B multiplied with another operand A in parallel. The intermediate products are combined in an adder with a compensation vector to correct any false negative sign on the two's complement sub-product from the multiplier handling the least significant, or lower, p bits of the split operand B, or B[p-1:0], where p=n/2. The compensation vector C is derived from the A and B operands using a simple circuit. The technique is easily extendible to 3 or more parallel multipliers, over which an n bit operand D can be split and multiplied with operand A in parallel. The compensation vector C' is similarly derived from the D and A operands inan analogous manner to the dual two's complement multiplier embodiment.
摘要翻译：提出了一种用于实现乘法资源的有效子字并行的方法和架构。在优选实施例中，呈现双二进制补码乘法器，使得可以拆分n位操作数B，并且操作数B的每个部分并行地与另一个操作数A相乘。中间产品在具有补偿向量的加法器中组合，以从处理分割操作数B的最低有效位或更低p位的乘数来校正二进制补码子乘积上的任何假负号，或者B [p-1 ：0]，其中p = n / 2。补偿矢量C使用简单的电路从A和B操作数导出。该技术可以容易地扩展到3个或更多个并行乘法器，通过该乘法器可以并行地将n位操作数D分割并与操作数A相乘。补偿矢量C'类似地从双二进制补码乘法器实施例中衍生自D和A操作数。

7. 发明申请

WO02071239A3 DATA PROCESSING APPARATUS AND SYSTEM AND METHOD FOR CONTROLLING MEMORY ACCESS 审中-公开
标题翻译：数据处理设备和控制存储器访问的系统和方法
公开(公告)号：WO02071239A3
公开(公告)日：2003-04-10
申请号：PCT/CA0200278
申请日：2002-03-04
申请人： ATSANA SEMICONDUCTOR CORP , GIERNALCZYK ERIC , STEWART MALCOM , NITA ADRIAN G , WONG DENNY , STEWART ANDREW , HO TUAN , LE THINH M
发明人： GIERNALCZYK ERIC , STEWART MALCOM , NITA ADRIAN G , WONG DENNY , STEWART ANDREW , HO TUAN , LE THINH M
IPC分类号： G06F3/00 , G06F7/575 , G06F9/302 , G06F13/16 , G06F15/173 , G06F15/80 , G06F13/42
CPC分类号： G06F7/575 , G06F9/30036 , G06F13/1663 , G06F15/17337 , G06F15/17375 , G06F15/8015 , G06F2207/382 , G06F2207/3828
摘要： A data processor comprises a memory having storage elements arranged in columns and a number of column decoders, each having a memory access port. The data processor has a plurality of processing elements, and each of the memory ports is coupleable to at least a respective one of the processor elements, such that each processor element is capable of accessing at least one column of storage elements.
摘要翻译：数据处理器包括具有以列排列的存储元件和多个列解码器的存储器，每个列解码器具有存储器访问端口。数据处理器具有多个处理元件，并且每个存储器端口可耦合到至少相应的一个处理器元件，使得每个处理器元件能够访问至少一列存储元件。

8. 发明申请

WO02029553A1 SINGLE INSTRUCTION MULTIPLE DATA PROCESSING 审中-公开
标题翻译：单指令多数据处理
公开(公告)号：WO02029553A1
公开(公告)日：2002-04-11
申请号：PCT/GB2001/003744
申请日：2001-08-21
IPC分类号： G06F7/00 , G06F7/50 , G06F7/505 , G06F7/74 , G06F7/76 , G06F9/30 , G06F9/302 , G06F9/305 , G06F9/315 , G06F9/38
CPC分类号： G06F7/505 , G06F7/49931 , G06F9/30014 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F2207/3828
摘要： A data processing system is provided with an instruction (ADD8T016) that unpacks non-adjacent portions of a data word using sign or zero extension and combines this with a single-instruction-multiple-data type arithmetic operation, such as an add, performed in response to the same instruction. The instruction is well suited to use within systems having a data path (2) including a shifting circuit (6) upstream of an arithmetic circuit (8).
摘要翻译：数据处理系统具有使用符号或零扩展来解开数据字的非相邻部分的指令（ADD8T016），并将其与单指令多数据类型算术运算（例如，在对同一指令的回应。该指令非常适合于在具有在运算电路（8）上游的移位电路（6）的数据路径（2）的系统内使用。

9. 发明申请

WO00077624A1 PROGRAM-CONTROLLED UNIT 审中-公开
标题翻译：程控UNIT
公开(公告)号：WO00077624A1
公开(公告)日：2000-12-21
申请号：PCT/EP2000/005434
申请日：2000-06-13
IPC分类号： G06F7/57 , G06F9/302 , G06F9/315 , G06F9/318 , G06F9/38 , G06F15/78 , G06F7/48
CPC分类号： G06F7/57 , G06F9/3001 , G06F9/30032 , G06F9/30072 , G06F9/3017 , G06F9/3808 , G06F9/381 , G06F9/3853 , G06F9/3885 , G06F9/3897 , G06F15/7867 , G06F2207/3828
摘要： The invention relates to a program-controlled unit that is characterized in that instructions that pertain to different groups of instructions are executed in different components of the program-controlled unit. The invention is further characterized in that subsequent instructions of an instruction sequence that have to be executed in different components are executed simultaneously and/or that the program-controlled unit converts the instructions read out from the program and/or data memory, simultaneously with their sequential processing, to macro-instructions that comprise several instructions and stores them internally.
摘要翻译：的可编程单元，其特征在于命令属于的指令不同的基团在程控单元的不同组件被执行，并且一个命令序列的该连续指令以在不同的组件来执行，同时和/或在于所述程序控制单元进行从除了相同的顺序处理程序和/或数据存储命令反应读入多个包含宏命令并在内部存储的命令。

10. 发明申请

WO99044329A3 ENCRYPTION PROCESSOR WITH SHARED MEMORY INTERCONNECT 审中-公开
标题翻译：具有共享内存互连的加密处理器
公开(公告)号：WO99044329A3
公开(公告)日：2000-03-02
申请号：PCT/CA1999/000176
申请日：1999-02-26
IPC分类号： G06F13/36 , G06F7/50 , G06F7/52 , G06F7/72 , G09C1/00 , H04L9/00 , H04L9/06 , H04L9/30 , G06F15/80
CPC分类号： G06F7/5324 , G06F7/49931 , G06F7/5052 , G06F7/72 , G06F7/722 , G06F2207/382 , G06F2207/3828 , H04L9/14 , H04L2209/125
摘要： An encryption chip is programmable to process a variety of secret key and public key encryption algorithms. The chip includes a pipeline of processing elements, each of which can process a round within a secret key algorithm. Data is transferred between the processing elements through dual port memories. A central processing unit allows for processing of very wide data words from global memory in single cycle operations. An adder circuit is simplified by using plural relatively small adder circuits with sums and carries looped back in plural cycles. Multiplier circuitry can be shared between the processing elements and the central processor by adapting the smaller processing element multipliers for concatenation as a very wide central processor multiplier.
摘要翻译：加密芯片是可编程的，用于处理各种秘密密钥和公钥加密算法。该芯片包括处理元件的流水线，每个处理元件可以在秘密密钥算法内处理一轮。通过双端口存储器在处理元件之间传送数据。中央处理单元允许在单周期操作中处理来自全局存储器的非常宽的数据字。通过使用多个具有和的相对较小的加法器电路来简化加法器电路，并以多个周期进行循环。乘法器电路可以通过将较小的处理单元乘法器适配为级联，作为非常宽的中央处理器乘法器而在处理元件和中央处理器之间共享。

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