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1. 发明申请

WO01044921A3 CIRCULAR ADDRESS REGISTER 审中-公开
标题翻译：通讯地址寄存器
公开(公告)号：WO01044921A3
公开(公告)日：2001-11-08
申请号：PCT/EP2000/012394
申请日：2000-12-05
IPC分类号： G06F9/30 , G06F7/50 , G06F7/505 , G06F9/32 , G06F9/355 , G06F9/38 , G06F12/02
CPC分类号： G06F7/5055 , G06F7/49931 , G06F9/3552 , G06F9/3879
摘要： A device and corresponding programming instructions are provided that facilitate a circular addressing process. The device is configured to provide an address output that is constrained to lie within specified bounds. When a "circular increment" or "circular decrement" instruction is executed that would cause the address to exceed a bound, the address is reset to the other bound. In a preferred embodiment, the programming instruction also sets condition flags that indicate when the address is at each bound. By providing these "bounds" flags in conjunction with the circular addressing operation, multiple-word data items can be processed efficiently. A base-address of N contiguous words in a memory is loaded into the circular register, and a circular addressing instruction is used to access each word of the N contiguous words in sequence; a bounds flag is set when the last word of the multi-word data item is accessed. This bounds flag may thus be used to signal the end of processing of N words of a multi-word data item, and can be used to trigger a load of a next multi-word data item, or to trigger a next operation on the current data-item, and so on. Other condition flags are also provided to facilitate the processing of multi-word data-items.
摘要翻译：本发明涉及一种有助于循环寻址过程的装置和相应的编程指令。该器件旨在提供受限制的输出地址以保持在特定的限制范围内。当 / =或 / =的指令被执行时，地址将返回到另一个限制。在优选实施例中，编程指令还实现指示地址何时达到极限的状态标志。这些 / =标志和循环寻址操作可以有效处理多字数据元素。包括存储器中N个连续字的基地址存储在循环寄存器中，循环寻址指令用于访问N个连续字序列中的每个字; 当达到多字数据项的最后一个字时，设置限制标志。因此该限制标记可用于指示多字数据项的N个字的处理的结束，并且可用于触发下一个多字数据项的记录或触发操作。接下来在当前数据元素上，依此类推。本发明还涉及用于便于处理多字数据项的其他状态指示符。

2. 发明申请

WO8905010A3 DUAL MODE ADDER CIRCUITRY 审中-公开
标题翻译：双模式ADDER电路
公开(公告)号：WO8905010A3
公开(公告)日：1989-08-10
申请号：PCT/US8803817
申请日：1988-11-03
申请人： TECHNOLOGY INC 64
发明人： PATTI MICHAEL FRANCIS , FEDELE NICOLA JOHN , HARNEY KEVIN , SIMON ALLEN HENRY
IPC分类号： G06F7/50 , G06F7/505 , G06F7/506 , H04N7/26
CPC分类号： G06F7/505 , G06F7/49921 , G06F9/30036 , G06F2207/3828
摘要： A video signal processor includes circuitry which may be conditioned by a mode control signal to operate as a single 16-bit adder or as two eight-bit adders. The circuitry includes two eight-bit adders, each of which has a carry-in input terminal and a carry-out output terminal. The carry-out output terminal of one of the adders is selectively coupled, via an AND gate, to the carry-in input terminal of the other adder. The AND gate is controlled by the mode control signal. In the mode where the circuitry operates as two eight-bit adders, additional circuitry is included to detect output values which may exceed the zero to 255 range of valid values and to saturate these invalid values either at zero or 255.

3. 发明申请

WO2023020984A1 MASKED SHIFTED ADD OPERATION 审中-公开
公开(公告)号：WO2023020984A1
公开(公告)日：2023-02-23
申请号：PCT/EP2022/072749
申请日：2022-08-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM DEUTSCHLAND GMBH
发明人： RAO, Rajat
IPC分类号： G06F7/505 , G06F7/53 , G06F7/76
摘要： A computer-implemented method includes receiving, by a processing unit, an instruction to perform a masked shift add operation with a set of operands. A logical AND operation is performed on a first pair of operands from the set of operands to obtain a first intermediate result. The first intermediate result is shifted by a first shift amount that is based on a first operand from the first pair of operands. A logical AND operation is performed on a second pair of operands from the set of operands to obtain a second intermediate result. The second intermediate result is shifted by a second shift amount that is based on a first operand from the second pair of operands. The shifted first intermediate result is added with the shifted second intermediate result. The method further includes outputting, as a result of the masked shift add operation, an output of the adding.

4. 发明申请

WO2020088005A1 一种基于忆阻器阵列潜流路径的内嵌快速加法器装置及计算方法审中-公开
公开(公告)号：WO2020088005A1
公开(公告)日：2020-05-07
申请号：PCT/CN2019/097848
申请日：2019-07-26
申请人：上海交通大学
发明人：景乃锋 , 李桃中 , 李彤 , 王琴 , 蒋剑飞 , 贺光辉 , 毛志刚
IPC分类号： G06F7/505
摘要：本发明是一种基于忆阻阵列潜流路径的加法器装置，相比于现阶段通过逻辑迭代进行加法计算的忆阻器加法器而言，本发明的特点在于：1分离加法运算的串并行部分，即串行进位和并行求和；2针对串行进位，构造相应的潜流路径并定制化其中的进位传播潜流路径，利用电流传播模拟进位行为，从而极大加快进位计算；3得到各比特位的进位后，利用现阶段忆阻器逻辑计算方式及交叉阵列并行结构特点同时完成所有比特位的求和计算。

5. 发明申请

WO0190881A3 Asynchronous completion prediction 审中-公开
标题翻译：异步完成预测
公开(公告)号：WO0190881A3
公开(公告)日：2002-04-25
申请号：PCT/US0117271
申请日：2001-05-25
申请人： SUN MICROSYSTEMS INC
发明人： RIDGWAY STUART ALEXANDER
IPC分类号： G06F7/50 , G06F7/505 , G06F9/38 , G07F7/50
CPC分类号： G06F7/5052 , G06F9/3871
摘要： A stage of a multi-stage, self-timed datapath circuit calculates one or more data outputs as a function of one or more data inputs. Data outputs are calculated by multiple logical elements that operate simultaneously and produce internal results as inputs to other logical elements within a stage. An internal completion signal generator detects completion of a predetermined set of the internal results calculation and, in response, generates an completion signal for each internal result detected. A done signal generator receives the completion signals and, in response to one or more preselected combinations of the completion signals, provides a done signal. The done signal is generated with a predetermined delay such that the delay is at least as long as a time it takes for the stage to calculate a final result.

6. 发明申请

WO2021088291A1 基于三值逻辑运算器的MSD并行加法器及其构造方法审中-公开
公开(公告)号：WO2021088291A1
公开(公告)日：2021-05-14
申请号：PCT/CN2020/079172
申请日：2020-03-13
申请人：上海大学
发明人：金翊 , 沈云付 , 欧阳山 , 彭俊杰 , 张俊杰 , 王宏健
IPC分类号： G06F7/505
摘要：本发明提供了一种基于三值逻辑运算器的MSD并行加法器的构造方法，采用符合MSD加法充分条件的5个三值逻辑运算器构造MSD并行加法器。在排列三值逻辑运算器时：可采用如下任意方法：每次将n位的三值运算器重构成一种三值逻辑运算器，经过5次重构实现；每次在n位的三值运算器上重构出输入相同的两个三值逻辑运算器，经过3次重构实现；在n位的三值运算器上同时重构出5个三值逻辑运算器，经过1次重构实现；用不可重构的各相应三值逻辑运算器取代上述重构过程；各三值逻辑运算器通过存储器传递中间数据，或将前一级三值逻辑运算器的输出端直接连接下一级三值逻辑运算器的输入端来传递中间数据。同时提供了一种基于三值逻辑运算器的MSD并行加法器。

7. 发明申请

WO2006088085A1 加算器、およびその合成装置、合成方法、合成プログラム、合成プログラム記録媒体审中-公开
标题翻译：添加剂，其合成装置，合成方法，合成方案和含有合成程序的记录介质
公开(公告)号：WO2006088085A1
公开(公告)日：2006-08-24
申请号：PCT/JP2006/302720
申请日：2006-02-16
申请人：松下電器産業株式会社 , 永野孝一
发明人：永野孝一
IPC分类号： G06F7/53 , G06F7/505
CPC分类号： G06F7/509 , G06F7/5318
摘要：　従来の多入力加算器は、演算ブロックの段数と半加算器および全加算器の個数のどちらか一方しか少なくできないという課題があった。　従来技術における課題を解決するため、演算ブロック（２ａ）の下位の２入力の桁の箇所、演算ブロックの最終段（２ｄ）より３つ前段での５入力で下位から２桁上がりの箇所、演算ブロックの最終段（２ｄ）より１つ前段の箇所でのみ半加算器（ＨＡ２０１，ＨＡ２０３，ＨＡ２０４，ＨＡ２０２，ＨＡ２０５）を用いる構成とした。
摘要翻译：常规的多输入加法器具有可以减少计算块的数量或仅减少半加法器和整个加法器的数量的问题。为了解决这个问题，仅在计算块（2a）的最低2输入数字的位置处使用半加法器（HA201，HA203，HA204，HA202，HA205），在最后的三个位置（2d）和来自计算块的最低位置的5输入第二数字，以及在计算块的最后阶段（2d）之前的一个位置。

8. 发明申请

WO0144921A2 CIRCULAR ADDRESS REGISTER 审中-公开
标题翻译：圆形地址寄存器
公开(公告)号：WO0144921A2
公开(公告)日：2001-06-21
申请号：PCT/EP0012394
申请日：2000-12-05
申请人： KONINKL PHILIPS ELECTRONICS NV
发明人： OSTLER FARRELL L , DAGHER ANTOINE F
IPC分类号： G06F9/30 , G06F7/50 , G06F7/505 , G06F9/32 , G06F9/355 , G06F9/38 , G06F12/02 , G06F9/00
CPC分类号： G06F7/5055 , G06F7/49931 , G06F9/3552 , G06F9/3879
摘要： A device and corresponding programming instructions are provided that facilitate a circular addressing process. The device is configured to provide an address output that is constrained to lie within specified bounds. When a "circular increment" or "circular decrement" instruction is executed that would cause the address to exceed a bound, the address is reset to the other bound. In a preferred embodiment, the programming instruction also sets condition flags that indicate when the address is at each bound. By providing these "bounds" flags in conjunction with the circular addressing operation, multiple-word data items can be processed efficiently. A base-address of N contiguous words in a memory is loaded into the circular register, and a circular addressing instruction is used to access each word of the N contiguous words in sequence; a bounds flag is set when the last word of the multi-word data item is accessed. This bounds flag may thus be used to signal the end of processing of N words of a multi-word data item, and can be used to trigger a load of a next multi-word data item, or to trigger a next operation on the current data-item, and so on. Other condition flags are also provided to facilitate the processing of multi-word data-items.
摘要翻译：提供了一种便于循环寻址过程的设备和相应的编程指令。该设备被配置为提供被限制在指定范围内的地址输出。当执行会导致地址超过限制的“循环增量”或“循环递减”指令时，地址将重置为另一个绑定。在优选实施例中，编程指令还设置指示何时在每个绑定处的地址的条件标志。通过结合循环寻址操作提供这些“边界”标志，可以有效地处理多个字的数据项。存储器中N个连续字的基址被加载到循环寄存器中，并且使用循环寻址指令来顺序地访问N个连续字的每个字; 当访问多字数据项的最后一个字时，设置边界标志。因此，这个边界标志可以用于指示多字数据项的N个字的处理的结束，并且可以用于触发下一个多字数据项的负载，或触发对当前的多字数据项的下一个操作数据项等。还提供了其他条件标志以便于处理多字数据项。

9. 发明申请

WO99012212A2 LONE-ELECTRON CIRCUIT ARRANGEMENT, OPERATING MODE, AND APPLICATION FOR ADDING BINARY NUMBERS 审中-公开
标题翻译：电路各个电子部件，操作方法有关步骤的加法二进制数的应用
公开(公告)号：WO99012212A2
公开(公告)日：1999-03-11
申请号：PCT/DE1998/002521
申请日：1998-08-26
IPC分类号： G06F7/501 , G06F7/50 , G06F7/505 , H01L29/66 , H03K17/00 , H03K19/02 , H01L29/76
CPC分类号： G06F7/505 , G06F7/502 , G06F2207/4828 , H03K19/02 , Y10S977/89 , Y10S977/937 , Y10S977/94
摘要： A circuit arrangement with lone-electron components has at least one lone-electron transistor, which is placed between a first main node and a second main node. The first node is capacitive betweeen a first operating voltage tap and a second operating voltage tap. The gate electrode of the lone-electron transistor is connected to a control voltage tap. The circuit arrangement concerned is suited for the logical combination of binary numbers, the positions of which are recorded in the first and second main nodes.
摘要翻译：在具有单电子部件的电路布置中，至少一个单电子晶体管，其连接第一主节点和第二主节点之间。第一主节点是第一电源电压端子和第二操作电压端子之间连接的电容。单电子晶体管的栅电极被连接到控制电压端子。该电路装置适合于二进制数，其数字被存储在第一和第二主节点的逻辑连接。

10. 发明申请

WO2021102382A1 DATA PROCESSING SYSTEM CONFIGURED FOR SEPARATED COMPUTATIONS FOR POSITIVE AND NEGATIVE DATA 审中-公开
公开(公告)号：WO2021102382A1
公开(公告)日：2021-05-27
申请号：PCT/US2020/061685
申请日：2020-11-20
申请人： MENTIUM TECHNOLOGIES INC.
发明人： BAYAT, Farnood, Merrikh
IPC分类号： G06F7/42 , G06F7/485 , G06F7/505
摘要： Operations may include obtaining input data and separating the input data into a first subset of input data and a second subset of input data, the first subset of input data including positive input data and the second subset of input data including negative input data. The operations may include performing positive computations on the first subset of input data to determine one or more first results and performing negative computations on the second subset of input data to determine one or more second results. The operations may include aggregating the one or more first results and the one or more second results to determine a solution based on the aggregating. The operations may include executing an application using a machine learning model or a deep neural network based on the determined solution.

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