专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO0045251A3 FLOATING AND PARALLEL FIXED POINT SQUARE ROOT AND RECIPROCAL POINT SQUARE COMPUTATION UNIT IN A PROCESSOR 审中-公开
标题翻译：浮动和平行固定点平方根和加工点的圆点计算单元
公开(公告)号：WO0045251A3
公开(公告)日：2000-12-14
申请号：PCT/US0001578
申请日：2000-01-24
申请人： SUN MICROSYSTEMS INC
发明人： SHANKAR RAVI , SUDHARSANAN SUBRAMANIA I
IPC分类号： G06F1/035 , G06F7/552 , G06F9/30 , G06F9/302 , G06F9/38
CPC分类号： G06F9/30014 , G06F1/0356 , G06F7/483 , G06F7/5525 , G06F9/30036 , G06F9/30098 , G06F9/3012 , G06F9/3838 , G06F9/3853 , G06F9/3877 , G06F9/3885 , G06F2101/08 , G06F2207/3824 , G06F2207/3828 , G06F2207/5521
摘要： A parallel fixed-point square root and reciprocal square root computation uses the same coefficient tables as the floating point square root and reciprocal square root computation by converting the fixed-point numbers into a floating-point structure with a leading implicit 1. The value of a number X is stored as two fixed-point numbers. In one embodiment, the fixed-point numbers are converted to the special floating-point structure using a leading zero detector and a shifter. Following the square root computation or the reciprocal square root computation, the floating point result is shifted back into the two-entry fixed-point format. The shift count is determined by the number of leaded zeros detected during the conversion from fixed-point to floating-point format.
摘要翻译：平行定点平方根和倒数平方根计算使用与浮点平方根和倒数平方根计算相同的系数表，将固定点数转换成具有前导隐含的浮点结构。数字X被存储为两个定点数。在一个实施例中，使用前导零检测器和移位器将定点数转换为特殊浮点结构。在平方根计算或倒数平方根计算之后，浮点结果被移回到双入口定点格式。移位计数由在从定点到浮点格式的转换期间检测到的引导零的数量来确定。

2. 发明申请

WO0045253A9 DIVISION UNIT IN A PROCESSOR USING A PIECE-WISE QUADRATIC APPROXIMATION TECHNIQUE 审中-公开
标题翻译：处理器中的分类单元使用一个三维四分法近似技术
公开(公告)号：WO0045253A9
公开(公告)日：2002-05-02
申请号：PCT/US0001780
申请日：2000-01-24
申请人： SUN MICROSYSTEMS INC
发明人： SHANKAR RAVI , SUDHARSANAN SUBRAMANIA I
IPC分类号： G06F7/499 , G06F7/52 , G06F7/535 , G06F9/302
CPC分类号： G06F7/535 , G06F7/4873 , G06F7/49947 , G06F7/49957 , G06F7/49963 , G06F9/30014 , G06F2207/3884
摘要： A computation unit computes a division operation Y/X by determining the value of a divisir reciprocal l/X and multiplying the reciprocal by a numerator Y. The reciprocal l/X value is determined using a quadratic approximation having a form: Ax +Bx+C, where coefficients A, B, and C are constants that are stored in a storage or memory such as a read-only memory (ROM). The bit length of the coefficient determines the error in a final result. Storage size is reduced through use of "least mean square error" techniques in the determination of the coefficients that are stored in the coefficient storage. During the generation of partial products x , Ax , and Bx, the process of rounding is eliminated, thereby reducing the computational logic to implement the division functionality.
摘要翻译：计算单元通过确定二进制倒数l / X的值并将倒数乘以分子Y来计算除法运算Y / X。使用具有以下形式的二次近似来确定倒数l / X值：Ax <2> + Bx + C，其中系数A，B和C是存储在诸如只读存储器（ROM）的存储器或存储器中的常数。系数的位长决定最终结果中的误差。在确定系数存储器中存储的系数时，通过使用“最小均方误差”技术来减少存储大小。在部分乘积x 2，Ax 2和B x的产生期间，舍入的过程被消除，从而减少了实现分割功能的计算逻辑。

3. 发明申请

WO0193595A3 VIDEO DECODER WITH PIPELINED VARIABLE LENGTH DECODING AND INVERSE QUANTIZATION 审中-公开
标题翻译：具有可变长度解码和反相量化的视频解码器
公开(公告)号：WO0193595A3
公开(公告)日：2002-04-11
申请号：PCT/US0116552
申请日：2001-05-21
申请人： SUN MICROSYSTEMS INC
发明人： SUDHARSANAN SUBRAMANIA I , SRIRAM PARTHASARATHY , GULATI AMIT
IPC分类号： G06T9/00 , H03M7/42 , H04N7/26 , H04N7/50
CPC分类号： H03M7/425 , H04N19/42 , H04N19/61 , H04N19/91
摘要： A method for pipelining variable length decode and inverse quantization operations in a hybrid motion-compensated and transform coded video decoder includes the step of mapping a new code word to a look-up table to retrieve a code word length, a zero-run length, and a quantized level. A new linear, zig-zagged position of a current coefficient is identified from the zero-run length and a previous zero-run length. The code word length is added to a current bitstream position to yield a new bitstream position. A quantization matrix coefficient from the new linear, zig-zagged position of the current coefficient is selected. The quantized level is multiplied by a predetermined value to produce a quantization product. In the case of inter block processing, a quantized level sign value is added to the quantization product. In the case of intra block processing, the quantization product does not include the quantization level sign. The quantization product is multiplied by a quantization matrix coefficient to form a derived quantization value. The derived quantization value is divided by a predetermined word length to produce a final quantization value. The new linear, zig-zagged position of the current coefficient is converted to a two-dimensional display position. The final quantization value is written at the display position.
摘要翻译：用于在混合运动补偿和变换编码视频解码器中流水线可变长度解码和逆量化操作的方法包括将新码字映射到查找表以检索码字长度，零游程长度，和量化水平。从零游程长度和以前的零游程长度来识别当前系数的新的线性，Z字形位置。码字长度被添加到当前比特流位置以产生新的比特流位置。选择来自当前系数的新的线性，Z字形位置的量化矩阵系数。量化电平乘以预定值以产生量化乘积。在块间处理的情况下，将量化的电平符号值加到量化乘积上。在块内处理的情况下，量化乘积不包括量化等级符号。量化乘积乘以量化矩阵系数以形成导出的量化值。导出的量化值被预定的字长除以产生最终的量化值。电流系数的新的线性，Z字形位置被转换为二维显示位置。最终量化值被写入显示位置。

4. 发明申请

WO0045254A9 FLOATING POINT SQUARE ROOT AND RECIPROCAL SQUARE ROOT COMPUTATION UNIT IN A PROCESSOR 审中-公开
标题翻译：处理器中的浮点和平方根计算单元
公开(公告)号：WO0045254A9
公开(公告)日：2001-09-07
申请号：PCT/US0001896
申请日：2000-01-24
申请人： SUN MICROSYSTEMS INC
发明人： SHANKAR RAVI , SUDHARSANAN SUBRAMANIA I
IPC分类号： G06F7/552 , G06F9/302
CPC分类号： G06F9/30014 , G06F7/5525 , G06F2207/5521
摘要： A method of computing a square root or a reciprocal square root of a number in a computing device uses a piece-wise quadratic approximation of the number. The square root computation uses the piece-wise quadratic approximation in the form: squareroot(X) = A ix + B ix + C i, in each interval i. The reciprocal square root computation uses the piece-wise quadratic approximation in the form: 1/squareroot(X)= Aix + Bix + Ci, in each interval i. The coefficients Ai, Bi, and Ci, and Ai, Bi and Ci are derived for the square root operation and for the reciprocal square root operation to reduce the least mean square error using a least squares approximation of a plurality of equally-spaced points within an interval. In one embodiment, 256 equally-spaced intervals are defined to represent the 23 bits of the mantissa. The coefficients are stored in a storage and accessed during execution of the square root or reciprocal square root computation instruction.
摘要翻译：在计算装置中计算数字的平方根或倒数平方根的方法使用数字的分段二次近似。平方根计算使用以下形式的分段二次近似：squareroot（X）= ix ix ix ix ix ix ix ix ix ix ix ix o o >我，在每个间隔我。相互平方根计算使用在每个间隔i中的形式为1 / squareroot（X）= Aix 2 + Bix + Ci的分段二次近似。对于平方根操作和平方根操作，导出系数Ai，Bi和Ci以及Ai，Bi和Ci，以便使用多个等间隔点内的最小平方近似来减小最小均方误差一个间隔在一个实施例中，256个等间隔的间隔被定义为表示尾数的23位。系数存储在存储器中，并在执行平方根或倒数平方根计算指令期间访问。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式