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1. 发明申请

WO02017494A2 NON-POWER-OF-TWO GREY-CODE COUNTER SYSTEM HAVING BINARY INCREMENTER WITH COUNTS DISTRIBUTED WITH BILATERAL SYMMETRY 审中-公开
标题翻译：具有二进制增值税的非双重灰色代码计数器系统，具有双向对称性分布
公开(公告)号：WO02017494A2
公开(公告)日：2002-02-28
申请号：PCT/EP2001/009573
申请日：2001-08-17
IPC分类号： G06F5/12 , G06F5/10 , G06F5/14 , H03K23/00 , H03K23/66 , H03M7/16
CPC分类号： G06F5/14 , G06F2205/102 , G06F2205/106 , H03K23/005
摘要： A gray-code counter system (AP1) for a RAM-based FIFO comprises a read pointer (10), a write pointer (20), and a detector (30). The read pointer includes a gray-code decoder (11), a binary incrementer (12), a gray-code encoder (13), and a register (14) that holds the pointer count). The binary incrementer increments by 1 except when the input is 0110 (decimal 6) or 1110 (decimal 14); in these cases, it increments by 3. The result is a 4-bit modulo-12 gray-code sequence with the twelve allowed gray-code values being distributed among the sixteen possible 4-bit gray code values with translational and reflective bilateral symmetry. The write pointer is similar. Because of the translational symmetry, detectors that work with counters with modulo numbers that are power of two work with the corresponding non-power-of-two counter to provide "full" and "empty" indications. When read and write counts differ at the two most-significant bit positions but are equal at the remaining bit positions, the detector provides a "full" indication for a 6-count FIFO. The gray-code counter design is scaleable to any non-power-of-two modulo number divisible by four.
摘要翻译：用于基于RAM的FIFO的灰度计数器系统（AP1）包括读指针（10），写指针（20）和检测器（30）。读指针包括灰码解码器（11），二进制递增器（12），灰码编码器（13）和保存指针计数的寄存器（14）。二进制递增器递增1，除非输入为0110（十进制6）或1110（十进制14）; 在这些情况下，它增加3.结果是4位模12灰度序列，其中十二个允许的灰度值分布在具有平移和反射双边对称性的十六个可能的4位灰色码值中。写指针是类似的。由于平移对称性，使用具有模数的计数器的检测器是两个功能的计数器，与相应的非二功能计数器相结合来提供“完全”和“空”指示。当读和写计数在两个最高有效位位置不同但在其余位位置相等时，检测器为6位FIFO提供“满”指示。灰度计数器设计可以扩展到可以被四个整除的任何非二次幂模数。

2. 发明申请

WO2003104968A2 SPACECAKE COPROCESSOR COMMUNICATION 审中-公开
标题翻译： SPACECAKE COPROCESSOR通信
公开(公告)号：WO2003104968A2
公开(公告)日：2003-12-18
申请号：PCT/IB2003/002282
申请日：2003-05-21
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , HOOGERBRUGGE, Jan , STRAVERS, Paul
发明人： HOOGERBRUGGE, Jan , STRAVERS, Paul
IPC分类号： G06F5/06
CPC分类号： G06F5/12 , G06F2205/106 , G06F2205/123
摘要： The invention is based on the idea to maintain two counters for an input or output port of a FIFO. A device for writing data elements from a coprocessor into a FIFO memory is provided. Said device is embedded in a multiprocessing environment comprising at least one coprocessor, a FIFO memory and a controller. Said device comprises a first counter for counting the available room in said FIFO memory, and a second counter for counting the number of data elements written into said FIFO memory. Said device further comprises a control means for checking said first counter for available room in said FIFO memory, and for checking said second counter whethera predetermined number N of data elements have been written into said FIFO memory. Said control means decrements the count of said first counter and increments the count of said second counter, after a data element has been written into said FIFO memory. Said device finally comprises an output means for outputting data elements to said FIFO memory. Said control means issues a first message when the count of said second counter has reached said predetermined number N and issues a first call for available room in said FIFO memory to said controller. Said output means forwards said first message and/or said first call to said controller.
摘要翻译：本发明基于为FIFO的输入或输出端口维护两个计数器的想法。提供了用于将数据元素从协处理器写入FIFO存储器的装置。所述设备嵌入在包括至少一个协处理器，FIFO存储器和控制器的多处理环境中。所述设备包括用于对所述FIFO存储器中的可用房间进行计数的第一计数器和用于对写入所述FIFO存储器中的数据元素的数量进行计数的第二计数器。所述设备还包括一个控制装置，用于检查所述第一计数器在所述FIFO存储器中的可用空间，并且用于检查所述第二计数器是否已将预定数量的数据元素N写入所述FIFO存储器。所述控制装置在将数据元素写入所述FIFO存储器之后，递减所述第一计数器的计数并递增所述第二计数器的计数。所述装置最终包括用于将数据元素输出到所述FIFO存储器的输出装置。所述控制装置在所述第二计数器的计数达到所述预定数量N时发出第一消息，并向所述控制器发出所述FIFO存储器中的可用空间的第一呼叫。所述输出装置将所述第一消息和/或所述第一呼叫转发到所述控制器。

3. 发明申请

WO2007097008A1 データ受信装置及びデータ送信装置审中-公开
标题翻译：数据接收设备和数据传输设备
公开(公告)号：WO2007097008A1
公开(公告)日：2007-08-30
申请号：PCT/JP2006/303498
申请日：2006-02-24
申请人：富士通株式会社 , 中川哲志
发明人：中川哲志
IPC分类号： H04L7/04 , H04L7/00
CPC分类号： G06F1/12 , G06F5/06 , G06F2205/106 , H04L7/005
摘要：　データ伝送におけるクロックステップ実行機能の信頼性を向上させる。　ライトポインタ生成部２３４－１、…、２３４－ｍは、ＦＩＦＯ回路２１３－１、２１３－ｍを構成している複数のバッファのうちから、送信側ＬＳＩ１００から送られてきたデータを格納する格納先とするものを順次切り替えて指示する。クロックステップ用リングバッファ２４３は、動作の停止を指示するゲートストップ信号を遅延させる。ライトポインタ生成部２３４－１、…、２３４－ｍは、クロックステップ用リングバッファ２４３で遅延させたゲートストップ信号を受け取ると格納先の指示の切り替えを停止させる。
摘要翻译：提高了数据传输中跨步执行功能的可靠性。写入指针生成单元（234-1），...，（234-m）从组成FIFO电路的多个缓冲器（213-1），（213-m）中依次改变并指定数据存储，其中发送的数据（LSI100）。用于时钟步长的环形缓冲器（243）延迟门停止信号以指示操作停止。当写指针产生单元（234-1），...（234-m）接收到由时钟步长由环形缓冲器（243）延迟的门停止信号时，它们停止存储器的切换指令。

4. 发明申请

WO2007048133A3 POINTER COMPUTATION METHOD AND SYSTEM FOR A SCALABLE, PROGRAMMABLE CIRCULAR BUFFER 审中-公开
标题翻译：指针计算方法和系统，用于可扩展的可编程循环缓冲器
公开(公告)号：WO2007048133A3
公开(公告)日：2007-08-02
申请号：PCT/US2006060133
申请日：2006-10-20
申请人： QUALCOMM INC , PLONDKE ERICH , CODRESCU LUCIAN , AHMED MUHAMMAD , ZENG MAO , JAMIL SUJAT , ANDERSON WILLIAM C
发明人： PLONDKE ERICH , CODRESCU LUCIAN , AHMED MUHAMMAD , ZENG MAO , JAMIL SUJAT , ANDERSON WILLIAM C
IPC分类号： G06F9/355 , G06F5/06
CPC分类号： G06F5/10 , G06F9/3552 , G06F9/3851 , G06F2205/106
摘要： Techniques for processing digital signals for a variety of applications, including in a communications (e.g. , CDMA) system. A pointer location within a circular buffer is determined by establishing a length of the circular buffer, a start address that is aligned to a power of 2, and an end address located distant from the start address by the length and less than a power of 2 greater than the length. The method and system determine a current pointer location for an address within the circular buffer, a stride value of bits between the start address and the end address, a new pointer location within the circular buffer by adding the current pointer location to the stride value. An adjusted pointer location is within the circular buffer by an arithmetic operation of the new pointer location with the length.
摘要翻译：用于处理包括在通信（例如CDMA）系统中的各种应用的数字信号的技术。循环缓冲器中的指针位置通过建立循环缓冲器的长度，与2的幂对齐的起始地址和远离起始地址长度并小于2的幂的结束地址来确定大于长度。该方法和系统确定循环缓冲器内的地址的当前指针位置，起始地址和结束地址之间的比特的步幅值，通过将当前指针位置添加到步幅值，循环缓冲器内的新指针位置。通过具有长度的新指针位置的算术运算，调整的指针位置在循环缓冲器内。

5. 发明申请

WO1979000035A1 APPARATUS FOR USE WITH A DATA PROCESSOR FOR DEFINING A CYCLIC DATA BUFFER 审中-公开
标题翻译：与用于定义循环数据缓冲区的数据处理器一起使用的设备
公开(公告)号：WO1979000035A1
公开(公告)日：1979-02-08
申请号：PCT/US1978000017
申请日：1978-06-22
申请人： WESTERN ELECTRIC CO INC
发明人： WESTERN ELECTRIC CO INC , SHIVELY R
IPC分类号： G11C19/28
CPC分类号： G06F5/14 , G06F7/72 , G06F13/00 , G06F2205/106 , G11C7/00 , H03H17/06
摘要： Apparatus for designating contiguous memory locations (e.g., locations 1000-1004) in a data memory (90) as a circular data buffer. A limit register defines the topmost buffer (L, e.g., location 1004) and a modulus register (40) defines the length (M) of the buffer. Circuitry (60) detects violations of the upper boundary (L) of the buffer and subtracts the buffer length (M) from the address. Boundary violation circuitry also controls execution of a data processor (10) instruction which conditionally subtracts the buffer length from the address.
摘要翻译：用于将数据存储器（90）中的连续存储器位置（例如，位置1000-1004）指定为循环数据缓冲器的装置。限制寄存器定义最上面的缓冲器（L，例如，位置1004），并且模数寄存器（40）定义缓冲器的长度（M）。电路（60）检测违反缓冲区的上边界（L），并从地址中减去缓冲区长度（M）。边界违规电路还控制从地址中有条件地减去缓冲器长度的数据处理器（10）指令的执行。

6. 发明申请

WO2012030667A2 A CIRCULAR BUFFER IN A REDUNDANT VIRTUALIZATION ENVIRONMENT 审中-公开
标题翻译：冗余虚拟化环境中的循环缓冲
公开(公告)号：WO2012030667A2
公开(公告)日：2012-03-08
申请号：PCT/US2011049442
申请日：2011-08-26
申请人： INTEL CORP , DONG YAO ZU EDDIE , TIAN KUN , JIANG YUNHONG
发明人： DONG YAO ZU EDDIE , TIAN KUN , JIANG YUNHONG
IPC分类号： G06F12/00 , G06F9/06
CPC分类号： G06F5/10 , G06F2205/106
摘要： Embodiments of systems, apparatuses, and methods for a circular buffer in a redundant virtualization environment are disclosed. In one embodiment, an apparatus includes a head indicator storage location, an outgoing tail indicator storage location, a buffer tail storage location, and fetch hardware. The head indicator, outgoing tail indicators, and buffer tail indicators are to indicate a head, outgoing tail, and buffer tail, respectively, of a circular buffer. The fetch hardware is to fetch from the head of the circular buffer and advance the head no further than the outgoing tail. The buffer tail is to be filled by software and advanced no further than the head.
摘要翻译：公开了用于冗余虚拟化环境中的循环缓冲器的系统，装置和方法的实施例。在一个实施例中，装置包括头部指示器存储位置，输出尾部指示器存储位置，缓冲器尾部存储位置和提取硬件。头部指示器，输出尾部指示器和缓冲器尾部指示器分别指示循环缓冲器的头部，出口尾部和缓冲器尾部。提取硬件是从循环缓冲区的头部取出，并且不要将输出尾部提前。缓冲尾巴要由软件填充，不要超过头。

7. 发明申请

WO2007048133A2 POINTER COMPUTATION METHOD AND SYSTEM FOR A SCALABLE, PROGRAMMABLE CIRCULAR BUFFER 审中-公开
标题翻译：指针计算方法和系统，用于可扩展的可编程循环缓冲器
公开(公告)号：WO2007048133A2
公开(公告)日：2007-04-26
申请号：PCT/US2006/060133
申请日：2006-10-20
申请人： QUALCOMM INCORPORATED , PLONDKE, Erich , CODRESCU, Lucian , AHMED, Muhammad , ZENG, Mao , JAMIL, Sujat , ANDERSON, William, C.
发明人： PLONDKE, Erich , CODRESCU, Lucian , AHMED, Muhammad , ZENG, Mao , JAMIL, Sujat , ANDERSON, William, C.
IPC分类号： G06F9/355
CPC分类号： G06F5/10 , G06F9/3552 , G06F9/3851 , G06F2205/106
摘要： Techniques for processing digital signals for a variety of applications, including in a communications (e.g., CDMA) system. A pointer location within a circular buffer is determined by establishing a length of the circular buffer, a start address that is aligned to a power of 2, and an end address located distant from the start address by the length and less than a power of 2 greater than the length. The method and system determine a current pointer location for an address within the circular buffer, a stride value of bits between the start address and the end address, a new pointer location within the circular buffer that is shifted from the current pointer location by the number of bits of the stride value. An adjusted pointer location is within the circular buffer by an arithmetic operation of the new pointer location with the length.
摘要翻译：用于处理各种应用的数字信号的技术，包括在通信（例如CDMA）系统中。循环缓冲器中的指针位置通过建立循环缓冲器的长度，与2的幂对齐的起始地址以及远离起始地址长度而小于2的幂的结束地址来确定大于长度。方法和系统确定循环缓冲区内的地址的当前指针位置，起始地址和结束地址之间的比特的步幅值，循环缓冲区内的新指针位置，从当前指针位置移位数字的步幅值。通过具有长度的新指针位置的算术运算，调整的指针位置在循环缓冲器内。

8. 发明申请

WO0217494A3 NON-POWER-OF-TWO GREY-CODE COUNTER SYSTEM HAVING BINARY INCREMENTER WITH COUNTS DISTRIBUTED WITH BILATERAL SYMMETRY 审中-公开
标题翻译：具有二进制增值税的非双重灰色代码计数器系统，具有双向对称性分布
公开(公告)号：WO0217494A3
公开(公告)日：2004-02-26
申请号：PCT/EP0109573
申请日：2001-08-17
申请人： KONINKL PHILIPS ELECTRONICS NV
发明人： PONTIUS TIMOTHY A
IPC分类号： G06F5/12 , G06F5/10 , G06F5/14 , H03K23/00 , H03K23/66 , H03M7/16
CPC分类号： G06F5/14 , G06F2205/102 , G06F2205/106 , H03K23/005
摘要： A gray-code counter system (AP1) for a RAM-based FIFO comprises a read pointer (10), a write pointer (20), and a detector (30). The read pointer includes a gray-code decoder (11), a binary incrementer (12), a gray-code encoder (13), and a register (14) that holds the pointer count). The binary incrementer increments by 1 except when the input is 0110 (decimal 6) or 1110 (decimal 14); in these cases, it increments by 3. The result is a 4-bit modulo-12 gray-code sequence with the twelve allowed gray-code values being distributed among the sixteen possible 4-bit gray code values with translational and reflective bilateral symmetry. The write pointer is similar. Because of the translational symmetry, detectors that work with counters with modulo numbers that are power of two work with the corresponding non-power-of-two counter to provide "full" and "empty" indications. When read and write counts differ at the two most-significant bit positions but are equal at the remaining bit positions, the detector provides a "full" indication for a 6-count FIFO. The gray-code counter design is scaleable to any non-power-of-two modulo number divisible by four.
摘要翻译：用于基于RAM的FIFO的灰度计数器系统（AP1）包括读指针（10），写指针（20）和检测器（30）。读指针包括灰码解码器（11），二进制递增器（12），灰码编码器（13）和保存指针计数的寄存器（14）。二进制递增器递增1，除非输入为0110（十进制6）或1110（十进制14）; 在这些情况下，它增加3.结果是4位模12灰度序列，其中十二个允许的灰度值分布在具有平移和反射双边对称性的十六个可能的4位灰色码值中。写指针是类似的。由于平移对称性，使用具有模数的计数器的检测器是两个功能的计数器，与相应的非二功能计数器相结合来提供“完全”和“空”指示。当读和写计数在两个最高有效位位置不同但在其余位位置相等时，检测器为6位FIFO提供“满”指示。灰度计数器设计可以扩展到可以被四个整除的任何非二次幂模数。

9. 发明申请

WO02054227A1 MODULO ADDRESSING 审中-公开
标题翻译： MODULO寻址
公开(公告)号：WO02054227A1
公开(公告)日：2002-07-11
申请号：PCT/US2001/050765
申请日：2001-12-28
IPC分类号： G06F12/02 , G06F5/10 , G06F7/72 , G06F9/355 , G06F5/06
CPC分类号： G06F5/10 , G06F7/72 , G06F9/3552 , G06F2205/106
摘要： In one embodiment, a modulo addressing unit for a processor is described that includes a plurality of adders to generate an uncorrected target modulo address and at least one corrected target modulo address in parallel. A comparator selects one of the target modulo addresses a function of a base address (b) for a circular buffer, a length (L) of the circular buffer, an index address (I) and a modifier value (M). In one embodiment the comparator selects a first corrected target modulo address when I+M =B+L and an uncorrected modulo address B
摘要翻译：在一个实施例中，描述了一种用于处理器的模寻址单元，其包括多个加法器，以并行生成未校正的目标模地址和至少一个校正的目标模数地址。比较器选择目标模数地址中的一个作为循环缓冲器的基址（b），循环缓冲器的长度（L），索引地址（I）和修改值（M）的函数。在一个实施例中，当I + M = B + L和未校正的模地址B <= I + M

10. 发明申请

WO1996023252A1 DATA TRANSMISSION SYSTEM 审中-公开
标题翻译：数据传输系统
公开(公告)号：WO1996023252A1
公开(公告)日：1996-08-01
申请号：PCT/SE1996000049
申请日：1996-01-19
申请人： TELEFONAKTIEBOLAGET LM ERICSSON , ARVIDSSON, Carl-Erik , LINDBLOM, Martin
发明人： TELEFONAKTIEBOLAGET LM ERICSSON
IPC分类号： G06F05/06
CPC分类号： G06F5/10 , G06F2205/106 , G11C8/00
摘要： A data buffer includes a number of data storing elements (202), a tree shaped structure (218) of multiplexer elements (216), a write address generator (21), and a read address generator (214). The data storing elements have data inputs connected in parallel to an input for a data stream from a sending clock domain. The tree shaped structure of multiplexer elements is arranged for receiving data from the data storing elements, and emits on an output a data stream to a receiving clock domain. The write address generator generates, controlled by a write clock signal (C1) from the clock of the sending clock domain, write addresses for entering data from the sending clock domain into the data storing elements, one at a time. The read address generator generates, controlled by a read clock signal (c2) from the clock generator of the receiving clock domain, read addresses for reading out data from the data storing elements in the same order as they were read in.
摘要翻译：数据缓冲器包括多个数据存储元件（202），多路复用器元件（218）的树形结构（218），写地址生成器（21）和读地址生成器（214）。数据存储元件具有与来自发送时钟域的数据流的输入并行连接的数据输入。多路复用器元件的树形结构被布置用于从数据存储元件接收数据，并将数据流输出到接收时钟域。写地址生成器由来自发送时钟域的时钟的写入时钟信号（C1）产生，用于将数据从发送时钟域输入数据存储元件的写入地址，一次一个。读取地址生成器由接收时钟域的时钟发生器的读取时钟信号（c2）产生，读取地址用于从与数据存储元件读取的数据相同的顺序读出数据。

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