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1. 发明申请

WO2013078439A2 MEMORY CIRCUIT INCORPORATING RADIATION HARDENED MEMORY SCRUB ENGINE 审中-公开
标题翻译：包含辐射硬化存储器擦洗发动机的存储电路
公开(公告)号：WO2013078439A2
公开(公告)日：2013-05-30
申请号：PCT/US2012066430
申请日：2012-11-21
申请人： MORRIS WESLEY H , GIFFORD DAVID R , LOWTHER REX E , SILICON SPACE TECHNOLOGY CORP
发明人： MORRIS WESLEY H , GIFFORD DAVID R , LOWTHER REX E
IPC分类号： G06F11/10
CPC分类号： G06F11/1008 , G06F11/0793 , G06F11/1048 , G06F11/183 , G06F11/186 , G11C8/00 , H03K19/00392
摘要： An example integrated circuit includes a first memory array including a first plurality of data groups, each such data group including a respective plurality of data bits. The integrated circuit also includes a first error detection and correction (ED AC) circuit configured to detect and correct an error in a data group read from the first memory array. The integrated circuit also includes a first scrub circuit configured to access in a sequence each of the first plurality of data groups to correct any detected errors therein. Both the first ED AC circuit and the first scrub circuit include spatially redundant circuitry. The first ED AC circuit and the first scrub circuit may include buried guard ring (BGR) structures, and may include parasitic isolation device (PID) structures. The spatially redundant circuitry may include dual interlocked storage cell (DICE) circuits, and may include temporal filtering circuitry.
摘要翻译：示例集成电路包括第一存储器阵列，第一存储器阵列包括第一多个数据组，每个这样的数据组包括相应的多个数据位。该集成电路还包括第一错误检测和校正（ED AC）电路，该电路被配置为检测并校正从第一存储器阵列读取的数据组中的错误。该集成电路还包括第一擦除电路，该第一擦除电路被配置为按顺序访问第一多个数据组中的每一个，以校正其中的任何检测到的错误。第一ED交流电路和第一擦洗电路都包括空间冗余电路。第一EDAC电路和第一擦除电路可以包括掩埋保护环（BGR）结构，并且可以包括寄生隔离器件（PID）结构。空间冗余电路可以包括双互锁存储单元（DICE）电路，并且可以包括时间滤波电路。

2. 发明申请

WO00017757A2 REDUNDANT FORM ADDRESS DECODER FOR MEMORY SYSTEM 审中-公开
标题翻译：存储器系统的冗余形状地址解码器
公开(公告)号：WO00017757A2
公开(公告)日：2000-03-30
申请号：PCT/US1999/027873
申请日：1999-08-27
IPC分类号： G11C8/00 , G06F12/00
CPC分类号： G11C8/00
摘要： The present invention provides a memory system (200) that retrieves data based upon redundant form address data. The memory system (200) includes a memory (220) having a plurality of memory lines (222) and an address decoder (210) that enables one of the memory lines (222) in response to a redundant form address signal. A redundant form decoder (230) decodes redundant form data into a differential pair of decoded address lines for each bit position of a memory address. One of the two differential pairs carries correct address data. The one address line to be used is determined on a memory line by memory line basis, using the address of the memory lines themselves. The redundant form address decoder (230) avoids a completion add that would otherwise be required, yielding very fast access to memory.
摘要翻译：本发明涉及一种基于冗余表格地址数据检索数据的存储器系统（200）。存储器系统（200）包括具有多个存储器线（222）的存储器（220）和响应于信号而使存储器线（222）中的一个存储器线有效的地址解码器解决多余的表格。冗余格式解码器（230）对冗余格式数据进行解码并为存储器地址的每个比特位置提供解码地址线的差分对。两个差分对中的一个携带正确的地址数据。通过直接使用存储器行的地址，应根据存储器行逐行确定应该使用的地址行的地址。该冗余表格地址解码器（230）避免了通常需要的最终添加，这允许非常快速的存储器访问。

3. 发明申请

WO99035649A1 A MEMORY SUPPORTING MULTIPLE ADDRESS PROTOCOLS 审中-公开
标题翻译：支持多地址协议的内存
公开(公告)号：WO99035649A1
公开(公告)日：1999-07-15
申请号：PCT/US1998/000459
申请日：1998-01-06
IPC分类号： G11C16/06 , G06F9/445 , G06F12/00 , G06F12/02 , G11C8/00 , G11C16/08 , G11C16/10
CPC分类号： G06F9/4403 , G11C8/00 , G11C16/08 , G11C16/10
摘要： The present invention provides a new memory device for storage of boot code for microprocessors. The device includes a memory array (130), a first block, and decoders (118, 120). The first block is defined as rows of the memory array. The decoders decode a memory access request for the data. The memory access request may be either one of a top-down or bottom-up address protocol. In another embodiment, an integrated circuit memory includes: a memory array (130), a decoder, a control (136), and a logic gate (132). The decoders select a row of the memory array. The control outputs either a bottom-up or a top-down address protocol signal. The logic gate outputs a logical "Exclusive Or" of the control signal and a corresponding bit of the memory request, whereby a memory request in a bottom-up address protocol is converted to a memory address in a top-down address protocol.
摘要翻译：本发明提供了一种用于存储微处理器的引导代码的新的存储器件。该设备包括存储器阵列（130），第一块和解码器（118,120）。第一个块被定义为存储器阵列的行。解码器解码数据的存储器访问请求。存储器访问请求可以是自顶向下或自下而上的地址协议之一。在另一实施例中，集成电路存储器包括：存储器阵列（130），解码器，控制（136）和逻辑门（132）。解码器选择一行存储器阵列。控制输出自下而上或自顶向下的地址协议信号。逻辑门输出控制信号的逻辑“异或”和存储器请求的相应位，由此自下而上的地址协议中的存储器请求被转换成自顶向下地址协议中的存储器地址。

4. 发明申请

WO9802886A3 MEMORY WITH FAST DECODING 审中-公开
标题翻译：内存快速解码
公开(公告)号：WO9802886A3
公开(公告)日：1998-05-07
申请号：PCT/US9712648
申请日：1997-07-17
申请人： CHANG EDWARD C M , CHANG DEIRDRE S , CHANG DEREK S
发明人： CHANG EDWARD C M , CHANG DEIRDRE S , CHANG DEREK S
IPC分类号： G11C11/413 , G11C7/10 , G11C8/00 , G11C8/10 , G11C11/407
CPC分类号： G11C7/1042 , G11C7/1018 , G11C8/00 , G11C8/10
摘要： A set of techniques are disclosed for organizing an electronic memory to increase the effective decoding speed while being able to randomly address storage locations in the memory. The memory typically contains a memory array (41 or 51) and address circuitry (40 or 50). In one memory-organization technique, the address circuitry contains a group of decoding segments (501-50M) arranged in series. Each decoding segment partially decodes an input memory address. In another memory-organization technique, the address circuitry contains a plurality of decoding segments (401 and 402) arranged in parallel, each decoding segment sequentially decoding different ones of the input memory addresses than each other decoding segment. A variation of the parallel memory-organization technique can be used with off-the-shelf memories.
摘要翻译：公开了用于组织电子存储器以增加有效解码速度同时能够随机地寻址存储器中的存储位置的一组技术。存储器通常包含存储器阵列（41或51）和地址电路（40或50）。在一种存储器组织技术中，地址电路包含一组串联排列的解码段（501-50M）。每个解码段都部分解码输入存储器地址。在另一种存储器组织技术中，地址电路包含并行排列的多个解码段（401和402），每个解码段顺序解码输入存储器地址中的不同输入存储器地址，而不是每个其他解码段。并行存储器组织技术的变体可以与现成的存储器一起使用。

5. 发明申请

WO1998002886A2 MEMORY WITH FAST DECODING 审中-公开
标题翻译：快速解码的记忆
公开(公告)号：WO1998002886A2
公开(公告)日：1998-01-22
申请号：PCT/US1997012648
申请日：1997-07-17
申请人： CHANG, Edward, C., M. , CHANG, Deirdre, S. , CHANG, Derek, S.
IPC分类号： G11C11/047
CPC分类号： G11C7/1042 , G11C7/1018 , G11C8/00 , G11C8/10
摘要： A set of techniques are disclosed for organizing an electronic memory to increase the effective decoding speed while being able to randomly address storage locations in the memory. The memory typically contains a memory array (41 or 51) and address circuitry (40 or 50). In one memory-organization technique, the address circuitry contains a group of decoding segments (501-50M) arranged in series. Each decoding segment partially decodes an input memory address. In another memory-organization technique, the address circuitry contains a plurality of decoding segments (401 and 402) arranged in parallel, each decoding segment sequentially decoding different ones of the input memory addresses than each other decoding segment. A variation of the parallel memory-organization technique can be used with off-the-shelf memories.
摘要翻译：一组技术被公开用于组织电子存储器以增加有效解码速度，同时能够随机地解决存储器中的存储位置。存储器通常包含存储器阵列（41或51）和地址电路（40或50）。在一种存储组织技术中，地址电路包含一组串联布置的解码段（501-50M）。每个解码段部分地解码输入存储器地址。在另一存储器组织技术中，地址电路包含并行排列的多个解码段（401和402），每个解码段顺序地解码输入存储器地址中的不同的译码段，而不是每个解码段。并行记忆组织技术的变体可以与现成的存储器一起使用。

6. 发明申请

WO1995002248A1 MEMORY BUFFER HAVING SELECTIVE FLUSH CAPABILITY 审中-公开
标题翻译：具有选择性冲洗能力的内存缓冲区
公开(公告)号：WO1995002248A1
公开(公告)日：1995-01-19
申请号：PCT/US1994007543
申请日：1994-07-06
申请人： VERTEX SEMICONDUCTOR CORPORATION
发明人： VERTEX SEMICONDUCTOR CORPORATION , NGUYEN, Andrea , YEUN, Joe , STEARNS, Charles
IPC分类号： G11C11/34
CPC分类号： G11C8/00 , G06F12/0897 , G11C7/00
摘要： A write buffer (10) having selective flush is disclosed. The write buffer (10) has address buffers (50) and associated data buffers (52) and comparators (54). During a "sneak read" operation, the address of the read operation is compared to the address signals stored in each of the address buffers (52). If a match is found, the read operation is temporarily suspended for only as long as the matched address remains stored in the write buffer (10). In a further improvement, the overhead associated with each match can be minimized to one write operation for each match before the matched address and data signals are written out of the write buffer (10).
摘要翻译：公开了一种具有选择性冲洗的写入缓冲器（10）。写缓冲器（10）具有地址缓冲器（50）和相关联的数据缓冲器（52）和比较器（54）。在“潜行读取”操作期间，将读取操作的地址与存储在每个地址缓冲器（52）中的地址信号进行比较。如果发现匹配，只要匹配的地址保持存储在写缓冲器（10）中，读操作就被暂停。在进一步的改进中，在将匹配的地址和数据信号写入写入缓冲器（10）之前，与每个匹配相关联的开销可以被最小化为每个匹配的一个写入操作。

7. 发明申请

WO1992009084A1 SEMICONDUCTOR MEMORY HAVING HIGH-SPEED ADDRESS DECODER 审中-公开
标题翻译：具有高速地址解码器的半导体存储器
公开(公告)号：WO1992009084A1
公开(公告)日：1992-05-29
申请号：PCT/JP1991001563
申请日：1991-11-15
申请人： FUJITSU LIMITED , FUJITSU VLSI LIMITED , KAWAMOTO, Satoru
发明人： FUJITSU LIMITED , FUJITSU VLSI LIMITED
IPC分类号： G11C11/406
CPC分类号： G11C8/00 , G11C11/406 , G11C11/408
摘要： A semiconductor memory comprising a memory cell array (1), a first address bus (2) for transferring external address signals, a second address bus (3) for transferring internal address signals, an address decoder (4), and a controller (5); wherein the address decoder (4) includes a decoding section (4A) for decoding the address signal inputted to the address decoder (4) to select the predetermined word line of the memory cell array (1) and a changing section (4B) for changing the address signal to be inputted to the decoding section (4A) to the external or internal address signal by selecting either of the first and second address buses (2 and 3). Thus, it is possible to decrease the transfer time by transferring the external and internal address signals to the address decoder (4) through the first and second address buses (2 and 3) in accordance with an address activation signal before operation mode is decided and accelerate the access time of the memory cell by decreasing the decoding time.

8. 发明申请

WO1988001426A1 INTEGRATED SEMICONDUCTOR MEMORY AND INTEGRATED SIGNAL PROCESSOR HAVING SUCH A MEMORY 审中-公开
标题翻译：集成半导体存储器和具有这种存储器的集成信号处理器
公开(公告)号：WO1988001426A1
公开(公告)日：1988-02-25
申请号：PCT/NL1986000024
申请日：1986-08-11
申请人： N.V. PHILIPS' GLOEILAMPENFABRIEKEN , VAN MEERBERGEN, Jozef, Louis , GUBBELS, Wilhelmus, Christianus, Hyacintus
发明人： N.V. PHILIPS' GLOEILAMPENFABRIEKEN
IPC分类号： G11C08/00
CPC分类号： G11C8/00
摘要： Increasing the storage capacity of high-performance (signal) processors while maintaining the original RAM cell necessitates modification of the entire lay-out of the circuit. The invention relates to the once-only design of peripheral circuitry which provides control of blocks of 4 Full CMOS RAM cells (easy to process) or 9 double-layer polysilicon cells (more difficult to process, but having smaller dimensions). It is defined in the RAM peripheral circuitry whether all 9 cells can be accessed (memory capacity from 2 n to 2 (n+1) + 2 (n-2)) or 8 cells can be accessed (memory capacity from 2 n to 2 (n+1)).
摘要翻译：提高高性能（信号）处理器的存储容量同时保持原始RAM单元需要修改电路的整个布局。本发明涉及提供对4个全CMOS RAM单元（易于处理）或9个双层多晶硅单元（更难以处理但具有较小尺寸）的块的控制的外围电路的一次性设计。在RAM外围电路中定义是否可以访问所有9个单元（存储器容量从2个**到2个**（n + 1）+ 2个**（n-2））或8个可以访问单元（存储容量从2 * * n到2 * **（n + 1））。

9. 发明申请

WO8700675A3 CONTROL SYSTEM FOR CHAINED CIRCUIT MODULES 审中-公开
标题翻译：链式电路模块控制系统
公开(公告)号：WO8700675A3
公开(公告)日：1987-03-26
申请号：PCT/GB8600401
申请日：1986-07-11
申请人： ANAMARTIC LTD , BRENT MICHAEL
发明人： BRENT MICHAEL
IPC分类号： G06F12/06 , G06F11/20 , G06F13/14 , G06F13/18 , G11C7/00 , G11C7/22 , G11C8/00 , G11C8/12 , G11C8/18 , G11C11/406 , G11C29/00 , H01L27/10
CPC分类号： G11C11/406 , G11C7/00 , G11C7/22 , G11C8/00 , G11C8/12 , G11C8/18 , G11C29/006
摘要： A wafer-scale integrated circuit comprises a few hundred modules (10) which can be connected into a long chain by commands sent to the modules along a transmit path set up by way of module inputs (XINN, XINE, XINS, XINW) from neighbouring modules and outputs thereto (XOUTN, XOUTE, XOUTS, XOUTW), only one of which is enabled by one of four selection signals (SELN, SELE, SELS, SELW) acting both on transmit path logic (20) and on receive path logic (21) in a return path. A RAM unit (23) can be enabled by WRITE to write a block of data sent to RID via the transmit path and can be enabled by READ to read a block of data to ROD for return along the return path. The provision of SELN, etc READ and WRITE is effected by configuration logic (22) which includes a shift register and is responsive to a command mode signal (CMND), on a line which runs to all modules in parallel. If, when CMND is asserted the bit currently in the transmit path is logic 0, the module is not addressed. If the bit is 1, the module is addressed and the bit is latched as a token within the XMIT path logic (20). The configuration logic then clocks the 1 bit token along its shift register until CMND goes low again. The first six stages of the shift register provide SELN, SELE, SELS, SELW, READ and WRITE respectively and the position of the token when CMND goes low determines which command is generated. The shift register has further stages for providing a signal ACR to reset an address counter in the RAM unit (23) and for toggling RPON which controls the power supply to the RAM unit (23) via a transistor switch.
摘要翻译：晶圆级集成电路包括几百个模块（10），它们可以通过沿着通过来自相邻模块的模块输入（XINN，XINE，XINS，XINW）建立的发送路径发送到模块的命令连接成长链（20）和接收路径逻辑（20）上的四个选择信号（SELN，SELE，SELS，SELW）中的一个选择信号中仅有一个选通信号被启用（XOUTN，XOUTE，XOUTS，XOUTW） 21）在返回路径中。 RAM单元（23）可以通过WRITE使能，以写入通过发送路径发送到RID的数据块，并且可以通过读使能读取数据块到ROD以沿着返回路径返回。 SELN等READ和WRITE的提供是由配置逻辑（22）实现的，配置逻辑（22）包括一个移位寄存器，并响应一条命令模式信号（CMND），并行传送到所有模块。如果当CMND被置位时，发送路径中当前的位为逻辑0，则该模块不被寻址。如果该位为1，则该模块被寻址，并且该位被锁存为XMIT路径逻辑（20）内的令牌。然后，配置逻辑沿移位寄存器对1位令牌进行计时，直到CMND再次变为低电平。移位寄存器的前六个阶段分别提供SELN，SELE，SELS，SELW，READ和WRITE，当CMND变为低电平时，令牌的位置决定生成哪个命令。移位寄存器还具有用于提供信号ACR以复位RAM单元（23）中的地址计数器并且用于切换RPON的另外的级，该RPON经由晶体管开关来控制对RAM单元（23）的电力供应。

10. 发明申请

WO1987000674A2 WAFER-SCALE INTEGRATED CIRCUIT MEMORY 审中-公开
标题翻译：超大规模集成电路存储器
公开(公告)号：WO1987000674A2
公开(公告)日：1987-01-29
申请号：PCT/GB1986000400
申请日：1986-07-11
申请人： ANAMARTIC LIMITED , BRENT, Michael , MACDONALD, Neal
发明人： ANAMARTIC LIMITED
IPC分类号： G11C07/00
CPC分类号： G11C8/00 , G11C7/00 , G11C7/22 , G11C8/12 , G11C8/18 , G11C11/406 , G11C29/006
摘要： A wafer scale integrated circuit comprises a few hundred modules (10) which can be connected into a long chain by commands sent to the modules along a transmit path set up by way of module inputs (XINN, XINE, XINS, XINW) from neighbouring modules and outputs thereto (XOUTN, XOUTE, XOUTS, XOUTW), only one of which is enabled by one of four selection signals (SELN, SELE, SELS, SELW) acting both on transmit path logic (20) and on receive path logic (21) in a return path. Each module includes configuration logic (22) which decodes commands providing the selection signals (SELN, etc), a READ signal and a WRITE signal. The configuration logic (22) is addressed when a bit is presented thereto by the transmit path simultaneously with assertion of a signal (CMND) which is supplied globally to all modules. The address configuration logic clocks the bit along a shift register and the selected command is determined by the position of the bit at the time that the global signal (CMND) is terminated. Each module includes a memory unit (23) including a free running address counter. When the WRITE command appears a data stream on the transmit path is read into the memory. When READ appears, the contents of the memory are read out onto the return path. Memory refresh occurs conventionally under control of the free-running address counter. In order to avoid heavy current in any of the power distribution conductors on the wafer, the count cycles of the free-running address counters are staggered.
摘要翻译：晶圆级集成电路包括几百个模块（10），其可以通过沿着通过模块输入（XINN，XINE，XINS，XINW）设置的传输路径从相邻模块发送到模块的命令连接到长链并且向其输出（XOUTN，XOUTE，XOUTS，XOUTW），其中仅一个由在发送路径逻辑（20）和接收路径逻辑（21）上起作用的四个选择信号（SELN，SELE，SELS，SELW）中的一个使能）在返回路径。每个模块包括对提供选择信号（SELN等）的命令，READ信号和WRITE信号进行解码的配置逻辑（22）。当通过发送路径同时向所有模块全局提供的信号（CMND）的断言同时向其发送位时，配置逻辑（22）被寻址。地址配置逻辑沿着移位寄存器对该位进行时钟，并且所选择的命令由全局信号（CMND）终止时的位的位置确定。每个模块包括包括自由运行的地址计数器的存储器单元（23）。当WRITE命令出现时，发送路径上的数据流被读入存储器。当READ出现时，内存的内容被读出到返回路径上。存储器刷新通常在自由运行地址计数器的控制下发生。为了避免晶片上的任何配电导体中的大电流，自由运行的地址计数器的计数周期是交错的。

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