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1. 发明申请

WO2008061086A2 METHOD AND SYSTEM FOR A DIGITAL SIGNAL PROCESSOR DEBUGGING DURING POWER TRANSITIONS 审中-公开
标题翻译：数字信号处理器在功率转换过程中调试的方法与系统
公开(公告)号：WO2008061086A2
公开(公告)日：2008-05-22
申请号：PCT/US2007/084523
申请日：2007-11-13
申请人： QUALCOMM Incorporated , CODRESCU, Lucian , ANDERSON, William C. , VENKUMAHANTI, Suresh , GIANNINI, Louis Achille , PYLA, Manojkumar , CHEN, Xufeng
发明人： CODRESCU, Lucian , ANDERSON, William C. , VENKUMAHANTI, Suresh , GIANNINI, Louis Achille , PYLA, Manojkumar , CHEN, Xufeng
CPC分类号： G06F1/3203 , G06F11/362 , G06F11/3656
摘要： Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. A method and system control transferring data between debugging registers and digital signal processor processes in association with a power transition sequence of the digital signal processor. In a digital signal processor, debugging registers associate with the core processor process and the debugging process. Control bits control transferring data among the debugging registers, the core processor process and the debugging process. The control bit prevents transferring data among the debugging registers, the core processor process and the debugging process in the event of a power transition sequence. Control bits also prevent a power transition sequence of the digital signal processor in the event of transferring data among the debugging registers and the core processor process or the debugging process.
摘要翻译：用于设计和使用数字信号处理器的技术，包括（但不限于）用于处理通信（例如，CDMA）系统中的传输。一种与数字信号处理器的功率转换序列相关联的在调试寄存器和数字信号处理器处理之间传送数据的方法和系统控制。在数字信号处理器中，调试寄存器与核心处理器进程和调试过程相关联。控制位控制在调试寄存器，核心处理器进程和调试过程之间传输数据。控制位防止在电源转换序列的情况下在调试寄存器，核心处理器进程和调试过程之间传输数据。在调试寄存器和核心处理器处理或调试过程之间传输数据的情况下，控制位还可以防止数字信号处理器的电源转换序列。

2. 发明申请

WO2007095626A1 POWER-EFFICIENT SIGN EXTENSION FOR BOOTH MULTIPLICATION METHODS AND SYSTEMS 审中-公开
标题翻译：功率有效的信号扩展用于引导方法和系统
公开(公告)号：WO2007095626A1
公开(公告)日：2007-08-23
申请号：PCT/US2007/062256
申请日：2007-02-15
申请人： QUALCOMM INCORPORATED , KRISHNAMURTHI, Rajeev , KOOB, Christopher, Edward , ANDERSON, William, C.
发明人： KRISHNAMURTHI, Rajeev , KOOB, Christopher, Edward , ANDERSON, William, C.
IPC分类号： G06F7/533 , G06F7/499 , G06F7/544
CPC分类号： G06F7/5338 , G06F7/49994 , G06F7/5443
摘要： Techniques for the design and use of a digital signal processor, including processing transmissions in a communications (e.g., CDMA) system. Power-efficient sign extension for Booth multiplication processes involves applying a sign bit in a Booth multiplication tree. The sign bit allows the Booth multiplication process to perform a sign extension step. This further involves one-extending a predetermined partial product row of the Booth multiplication tree using a sign bit for preserving the correct sign of the predetermined partial product row. The process and system resolve the signal value of the sign bit by generating a sign-extension bit in the Booth multiplication tree. The sign-extension bit is positioned in a carry-out column to extend the product of the Booth multiplication process. Then, the method and system form a final product from the Booth multiplication tree by adding the carry-out value to the sign bit positioned at a predetermined column of the Booth multiplication tree. The result is to effectively extend the sum component of the final product with the sign and zero-extending the carry component of the final product.
摘要翻译：用于设计和使用数字信号处理器的技术，包括处理通信（例如，CDMA）系统中的传输。展位乘法过程的功率效率符号扩展涉及在展位乘法树中应用符号位。符号位允许展位乘法过程执行符号扩展步骤。这还涉及使用用于保留预定部分乘积行的正确符号的符号位来单扩展布乘除树的预定部分乘积行。该过程和系统通过在展位乘法树中生成一个符号扩展位来解析符号位的信号值。符号扩展位位于进位列中以扩展展位乘法过程的乘积。然后，该方法和系统通过将位移值位于位于Booth乘法树的预定列处的符号位，从Booth乘积树形成最终乘积。结果是有效地扩展最终产品的总和成分与符号和零扩展最终产品的进位组件。

3. 发明申请

WO2007047784A2 SHARED INTERRUPT CONTROL METHOD AND SYSTEM FOR A DIGITAL SIGNAL PROCESSOR 审中-公开
标题翻译：数字信号处理器的共享中断控制方法和系统
公开(公告)号：WO2007047784A2
公开(公告)日：2007-04-26
申请号：PCT/US2006040759
申请日：2006-10-18
申请人： QUALCOMM INC , CODRESCU LUCIAN , ANDERSON WILLIAM C
发明人： CODRESCU LUCIAN , ANDERSON WILLIAM C
CPC分类号： G06F9/4812 , G06F9/30101 , G06F9/3851
摘要： Techniques for the design and use of a digital signal processor, including (but not limited to) processing transmissions in a communications (e.g., CDMA) system. The disclosed method and system process interrupts arising in a multithreaded processor by receiving in an interrupt register a plurality of interrupts of a statistically indeterminate interrupt type and then associating a plurality of processing threads with the interrupt register for receiving the interrupt from the interrupt register. The method and system mask at least a subset of the plurality of processing threads so as to receive within each of the threads within the subset only ones of the plurality of interrupts of one or more predetermined types, thereby controlling on a per thread basis the processing of the plurality of interrupts according to the mask associated with a particular thread.
摘要翻译：用于设计和使用数字信号处理器的技术，包括（但不限于）处理通信（例如，CDMA）系统中的传输。所公开的方法和系统过程在多线程处理器中产生的中断通过在中断寄存器中接收到统计不确定的中断类型的多个中断，然后将多个处理线程与中断寄存器相关联，以从中断寄存器接收中断。所述方法和系统掩蔽所述多个处理线程的至少一个子集，以便在所述子集内的每个所述线程内接收一个或多个预定类型的所述多个中断中的一个，从而在每个线程的基础上控制所述处理根据与特定线程相关联的掩码的多个中断。

4. 发明申请

WO2007002801A2 SYSTEM AND METHOD OF CONTROLLING POWER IN A MULTI-THREADED PROCESSOR 审中-公开
标题翻译：多线程处理器中的电源控制系统及方法
公开(公告)号：WO2007002801A2
公开(公告)日：2007-01-04
申请号：PCT/US2006/025299
申请日：2006-06-27
申请人： QUALCOMM INCORPORATED , ANDERSON, William, C.
发明人： ANDERSON, William, C.
IPC分类号： G06F1/32
CPC分类号： G06F9/3851 , G06F1/3203 , G06F9/4812
摘要： A multithreaded processor device is disclosed and includes a plurality of execution units to execute a plurality of program threads and includes a global low power detection circuit. The global low power detection circuit includes an input that is responsive to each of the plurality of program threads. The input indicates an execution activity level for each of the plurality of program threads. The global low power detection circuit further comprises logic to evaluate the activity level of each of the plurality of program threads. The logic provides a power level signal. Additionally, the global low power detection circuit includes an output that is responsive to the power level signal. The output is coupled to one or more global resources within the multithreaded processor and the output selectively controls an amount of power provided to the one or more global resources.
摘要翻译：公开了一种多线程处理器设备，并且包括执行多个程序线程的多个执行单元，并且包括全局低功率检测电路。全局低功率检测电路包括响应于多个程序线程中的每一个的输入。输入指示多个程序线程中的每一个的执行活动级别。全局低功率检测电路还包括用于评估多个程序线程中的每一个的活动级别的逻辑。该逻辑提供功率电平信号。另外，全局低功率检测电路包括响应于功率电平信号的输出。输出耦合到多线程处理器内的一个或多个全局资源，并且输出选择性地控制提供给一个或多个全局资源的功率量。

5. 发明申请

WO2007002415A1 SHARED TRANSLATION LOOK-ASIDE BUFFER AND METHOD 审中-公开
标题翻译：共享翻译书面缓冲区和方法
公开(公告)号：WO2007002415A1
公开(公告)日：2007-01-04
申请号：PCT/US2006/024500
申请日：2006-06-23
申请人： QUALCOMM INCORPORATED , PLONDKE, Erich , ANDERSON, William, C. , CONDRESCU, Lucian
发明人： PLONDKE, Erich , ANDERSON, William, C. , CONDRESCU, Lucian
IPC分类号： G06F9/48
CPC分类号： G06F9/4812 , G06F12/1027 , Y02D10/13 , Y02D10/24
摘要： A shared translation look-aside buffer method comprises saving data stored in a first selected set of registers to a predetermined section of a thread-specific area in memory upon encountering an exception/interrupt, re-enabling exceptions and optionally interrupts, addressing a cause of the exception/interrupt while safely permitting another exception, and restoring the saved data to the first selected set of registers.
摘要翻译：共享翻译后备缓冲方法包括：当遇到异常/中断时，将存储在第一选定寄存器组中的数据保存到存储器中线程特定区域的预定部分，重新启用异常和可选中断，解决原因异常/中断，同时安全地允许另一个异常，并将保存的数据恢复到第一选定的寄存器组。

6. 发明申请

WO2006116257A2 SYSTEM AND METHOD OF EXECUTING PROGRAM THREADS IN A MULTI-THREADED PROCESSOR 审中-公开
标题翻译：在多线程处理器中执行程序线程的系统和方法
公开(公告)号：WO2006116257A2
公开(公告)日：2006-11-02
申请号：PCT/US2006015390
申请日：2006-04-24
申请人： QUALCOMM INC , CODRESCU LUCIAN , PLONDKE ERICH , AHMED MUHAMMAD , ANDERSON WILLIAM C
发明人： CODRESCU LUCIAN , PLONDKE ERICH , AHMED MUHAMMAD , ANDERSON WILLIAM C
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3853
摘要： A multithreaded processor device is disclosed and includes a first program thread and second program thread. The second program thread is execution linked to the first program thread in a lock step manner. As such, when the first program thread experiences a stall event, the second program thread is instructed to perform a no operation instruction in order to keep the second program thread execution linked to the first program thread. Also, the second program thread performs a no operation instruction during each clock cycle that the first program thread is stalled due to the stall event. When the first program thread performs a first successful operation after the stall event, the second program thread restarts normal execution.
摘要翻译：公开了一种多线程处理器设备，并且包括第一程序线程和第二程序线程。第二个程序线程以锁定步骤的方式执行链接到第一个程序线程。这样，当第一程序线程经历停顿事件时，指示第二程序线程执行无操作指令，以便使第二程序线程执行与第一程序线程相关联。此外，第二程序线程在每个时钟周期期间执行无操作指令，由于失速事件使第一程序线程停滞。当第一程序线程在停止事件之后执行第一次成功操作时，第二程序线程重新启动正常执行。

7. 发明申请

WO2006110906A2 UNIFIED NON-PARTITIONED REGISTER FILES FOR A DIGITAL SIGNAL PROCESSOR OPERATING IN AN INTERLEAVED MULTI-THREADED ENVIRONMENT 审中-公开
标题翻译：用于数字信号处理器的统一的非分区寄存器文件在交互式多线程环境中运行
公开(公告)号：WO2006110906A2
公开(公告)日：2006-10-19
申请号：PCT/US2006/014174
申请日：2006-04-11
申请人： QUALCOMM INCORPORATED , CODRESCU, Lucian , PLONDKE, Erich , AHMED, Muhammad , ANDERSON, William, C. , SIMPSON, Taylor
发明人： CODRESCU, Lucian , PLONDKE, Erich , AHMED, Muhammad , ANDERSON, William, C. , SIMPSON, Taylor
CPC分类号： H04M1/72522 , G06F9/3012 , G06F9/3885 , H04M1/2535 , H04M2250/02
摘要： A processor device is disclosed and includes a memory and a sequencer that is responsive to the memory. The sequencer can support very long instruction word (VLIW) instructions and superscalar instructions. The processor device further includes a first instruction execution unit responsive to the sequencer, a second instruction execution unit responsive to the sequencer, a third instruction execution unit responsive to the sequencer, and a fourth instruction execution unit responsive to the sequencer. Further, the processor device includes a plurality of register files and each of the plurality of register files includes a plurality of registers. The plurality of register files are coupled to the sequencer and coupled to the first instruction execution unit, the second instruction execution unit, the third instruction execution unit, and the fourth instruction execution unit.
摘要翻译：公开了处理器设备，并且包括响应于存储器的存储器和定序器。音序器可以支持非常长的指令字（VLIW）指令和超标量指令。处理器装置还包括响应于定序器的第一指令执行单元，响应于定序器的第二指令执行单元，响应于定序器的第三指令执行单元和响应于定序器的第四指令执行单元。此外，处理器装置包括多个寄存器文件，并且多个寄存器文件中的每一个包括多个寄存器。多个寄存器文件耦合到定序器并耦合到第一指令执行单元，第二指令执行单元，第三指令执行单元和第四指令执行单元。

8. 发明申请

WO2006110905A2 SYSTEM AND METHOD OF USING A PREDICATE VALUE TO ACCESS A REGISTER FILE 审中-公开
标题翻译：使用预测值访问寄存器文件的系统和方法
公开(公告)号：WO2006110905A2
公开(公告)日：2006-10-19
申请号：PCT/US2006014173
申请日：2006-04-11
申请人： QUALCOMM INC , AHMED MUHAMMAD , PLONDKE ERICH , CODRESCU LUCIAN , ANDERSON WILLIAM C
发明人： AHMED MUHAMMAD , PLONDKE ERICH , CODRESCU LUCIAN , ANDERSON WILLIAM C
CPC分类号： G06F9/3842 , G06F9/3851 , G06F9/3885
摘要： A processor device is disclosed and includes a memory unit and at least one interleaved multi-threading instruction pipeline. The interleaved multi-threading instruction pipeline utilizes a number of clock cycles that is less than an instruction issue rate for each of a plurality of program threads that are stored within the memory unit. The memory unit includes six instruction caches. Further, the processor device includes six register files and each of the six register files is associated with one of the six instruction caches. Each of the plurality of program threads is associated with one of the six register files. Further, each of the six program threads includes a plurality of instructions and each of the plurality of instructions is stored within one of the six instruction caches of the memory.
摘要翻译：公开了一种处理器设备，并且包括存储器单元和至少一个交错多线程指令流水线。交错多线程指令流水线利用了小于存储在存储器单元内的多个程序线程中的每一个的指令发布速率的多个时钟周期。存储单元包括六个指令高速缓存。此外，处理器设备包括六个寄存器文件，六个寄存器文件中的每一个与六个指令高速缓存中的一个相关联。多个程序线程中的每一个与六个寄存器文件之一相关联。此外，六个程序线程中的每一个包括多个指令，并且多个指令中的每一个被存储在存储器的六个指令高速缓存之一中。

9. 发明申请

WO2006102668A2 METHOD AND SYSTEM FOR VARIABLE THREAD ALLOCATION AND SWITCHING IN A MULTITHREADED PROCESSOR 审中-公开
标题翻译：在多处理器中可变螺纹分配和切换的方法和系统
公开(公告)号：WO2006102668A2
公开(公告)日：2006-09-28
申请号：PCT/US2006011175
申请日：2006-03-23
申请人： QUALCOMM INC , AHMED MUHAMMAD , JAMIL SUJAT , PLONDKE ERICH , CODRESCU LUCIAN , ANDERSON WILLIAM C
发明人： AHMED MUHAMMAD , JAMIL SUJAT , PLONDKE ERICH , CODRESCU LUCIAN , ANDERSON WILLIAM C
IPC分类号： G06F9/38
CPC分类号： G06F9/3851
摘要： Techniques for processing transmissions in a communications (e.g., CDMA) system. An aspect of the disclosed subject matter includes a method for processing instructions on a multithreaded processor. The multithreaded processor processes a plurality of threads via a plurality of processor pipelines. The method includes the step determining the operating frequency, F, at which the multithreaded processor operates. Then, the method determines a variable thread switch timeout state for triggering the switching of the processing among the plurality of active threads. The variable thread switch timeout state varies so that each of the plurality of active threads operates at a frequency of an allocated portion of the frequency, F. The allocated portion at which the active threads operate is determined at least in part in order to optimize the operation of the multithreaded processor. The method furtherswitches the processing from a first one of the active threads to a next one of the active threads upon the occurrence of the variable thread switch timeout state.
摘要翻译：用于在通信（例如，CDMA）系统中处理传输的技术。所公开的主题的一个方面包括用于在多线程处理器上处理指令的方法。多线程处理器经由多个处理器管线处理多个线程。该方法包括确定多线程处理器工作的工作频率F的步骤。然后，该方法确定用于触发多个活动线程之间的处理切换的可变线程切换超时状态。可变线程切换超时状态改变，使得多个活动线程中的每一个以所分配的频率部分F的频率运行。活动线程运行的分配部分至少部分地被确定，以便优化操作多线程处理器。在发生可变线程切换超时状态时，该方法还将从主动线程中的第一个到下一个活动线程的处理开关。

10. 发明申请

WO2012162225A1 MEMORY WITH METADATA STORED IN A PORTION OF THE MEMORY PAGES 审中-公开
标题翻译：存储在存储器页的存储器中的存储器
公开(公告)号：WO2012162225A1
公开(公告)日：2012-11-29
申请号：PCT/US2012/038794
申请日：2012-05-21
申请人： QUALCOMM INCORPORATED , PLONDKE, Erich, James , CODRESCU, Lucian , ANDERSON, William, C.
发明人： PLONDKE, Erich, James , CODRESCU, Lucian , ANDERSON, William, C.
IPC分类号： G06F11/10
CPC分类号： G06F12/0893 , G06F11/1064 , G06F12/0646 , Y02D10/13
摘要： Systems and method for configuring a page-based memory device without pre-existing dedicated metadata. The method includes reading metadata from a metadata portion of a page of the memory device, and determining a characteristic of the page based on the metadata. The memory device may be configured as a cache. The metadata may include address tags, such that determining the characteristic may include determining if desired information is present in the page, and reading the desired information if it is determined to be present in the page. The metadata may also include error-correcting code (ECC), such that determining the characteristic may include detecting errors present in data stored in the page. The metadata may further include directory information, memory coherency information, or dirty/valid/lock information.
摘要翻译：用于配置基于页面的存储设备而不具有预先存在的专用元数据的系统和方法。该方法包括从存储设备的页面的元数据部分读取元数据，以及基于元数据确定页面的特性。存储器件可以被配置为高速缓存。元数据可以包括地址标签，使得确定特征可以包括确定页面中是否存在所需信息，并且如果确定存在于页面中则读取所需信息。元数据还可以包括纠错码（ECC），使得确定特性可以包括检测存在于页面中的数据中存在的错误。元数据还可以包括目录信息，存储器一致性信息或脏/有效/锁定信息。

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