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1. 发明申请

WO1996023252A1 DATA TRANSMISSION SYSTEM 审中-公开
标题翻译：数据传输系统
公开(公告)号：WO1996023252A1
公开(公告)日：1996-08-01
申请号：PCT/SE1996000049
申请日：1996-01-19
申请人： TELEFONAKTIEBOLAGET LM ERICSSON , ARVIDSSON, Carl-Erik , LINDBLOM, Martin
发明人： TELEFONAKTIEBOLAGET LM ERICSSON
IPC分类号： G06F05/06
CPC分类号： G06F5/10 , G06F2205/106 , G11C8/00
摘要： A data buffer includes a number of data storing elements (202), a tree shaped structure (218) of multiplexer elements (216), a write address generator (21), and a read address generator (214). The data storing elements have data inputs connected in parallel to an input for a data stream from a sending clock domain. The tree shaped structure of multiplexer elements is arranged for receiving data from the data storing elements, and emits on an output a data stream to a receiving clock domain. The write address generator generates, controlled by a write clock signal (C1) from the clock of the sending clock domain, write addresses for entering data from the sending clock domain into the data storing elements, one at a time. The read address generator generates, controlled by a read clock signal (c2) from the clock generator of the receiving clock domain, read addresses for reading out data from the data storing elements in the same order as they were read in.
摘要翻译：数据缓冲器包括多个数据存储元件（202），多路复用器元件（218）的树形结构（218），写地址生成器（21）和读地址生成器（214）。数据存储元件具有与来自发送时钟域的数据流的输入并行连接的数据输入。多路复用器元件的树形结构被布置用于从数据存储元件接收数据，并将数据流输出到接收时钟域。写地址生成器由来自发送时钟域的时钟的写入时钟信号（C1）产生，用于将数据从发送时钟域输入数据存储元件的写入地址，一次一个。读取地址生成器由接收时钟域的时钟发生器的读取时钟信号（c2）产生，读取地址用于从与数据存储元件读取的数据相同的顺序读出数据。

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