专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2012162225A1 MEMORY WITH METADATA STORED IN A PORTION OF THE MEMORY PAGES 审中-公开
标题翻译：存储在存储器页的存储器中的存储器
公开(公告)号：WO2012162225A1
公开(公告)日：2012-11-29
申请号：PCT/US2012/038794
申请日：2012-05-21
申请人： QUALCOMM INCORPORATED , PLONDKE, Erich, James , CODRESCU, Lucian , ANDERSON, William, C.
发明人： PLONDKE, Erich, James , CODRESCU, Lucian , ANDERSON, William, C.
IPC分类号： G06F11/10
CPC分类号： G06F12/0893 , G06F11/1064 , G06F12/0646 , Y02D10/13
摘要： Systems and method for configuring a page-based memory device without pre-existing dedicated metadata. The method includes reading metadata from a metadata portion of a page of the memory device, and determining a characteristic of the page based on the metadata. The memory device may be configured as a cache. The metadata may include address tags, such that determining the characteristic may include determining if desired information is present in the page, and reading the desired information if it is determined to be present in the page. The metadata may also include error-correcting code (ECC), such that determining the characteristic may include detecting errors present in data stored in the page. The metadata may further include directory information, memory coherency information, or dirty/valid/lock information.
摘要翻译：用于配置基于页面的存储设备而不具有预先存在的专用元数据的系统和方法。该方法包括从存储设备的页面的元数据部分读取元数据，以及基于元数据确定页面的特性。存储器件可以被配置为高速缓存。元数据可以包括地址标签，使得确定特征可以包括确定页面中是否存在所需信息，并且如果确定存在于页面中则读取所需信息。元数据还可以包括纠错码（ECC），使得确定特性可以包括检测存在于页面中的数据中存在的错误。元数据还可以包括目录信息，存储器一致性信息或脏/有效/锁定信息。

2. 发明申请

WO2011072083A1 THREAD ALLOCATION AND CLOCK CYCLE ADJUSTMENT IN AN INTERLEAVED MULTI-THREADED PROCESSOR 审中-公开
标题翻译：交叉多线程处理器中的螺纹分配和时钟周期调整
公开(公告)号：WO2011072083A1
公开(公告)日：2011-06-16
申请号：PCT/US2010/059579
申请日：2010-12-08
申请人： QUALCOMM INCORPORATED , VENKUMAHANTI, Suresh, K. , SAINT-LAURENT, Martin , CODRESCU, Lucian , MOHAMMAD, Baker, S.
发明人： VENKUMAHANTI, Suresh, K. , SAINT-LAURENT, Martin , CODRESCU, Lucian , MOHAMMAD, Baker, S.
IPC分类号： G06F9/38 , G06F9/50
CPC分类号： G01R1/07378 , G01R3/00 , G01R31/2846 , G01R31/2889 , G01R31/2896 , G06F9/3851
摘要： Methods, apparatuses, and computer-readable storage media are disclosed for reducing power by reducing hardware-thread toggling in a multi-threaded processor. In a particular embodiment, a method allocates software threads to hardware threads. A number of software threads to be allocated is identified. It is determined when the number of software threads is less than a number of hardware threads. When the number of software threads is less than the number of hardware threads, at least two of the software threads are allocated to non-sequential hardware threads. A clock signal to be applied to the hardware threads is adjusted responsive to the non-sequential hardware threads allocated.
摘要翻译：公开了用于通过减少多线程处理器中的硬件线程切换来降低功率的方法，装置和计算机可读存储介质。在特定实施例中，一种方法将软件线程分配给硬件线程。识别要分配的多个软件线程。何时软件线程的数量少于多个硬件线程。当软件线程的数量小于硬件线程数时，至少两个软件线程被分配给非顺序硬件线程。响应于所分配的非顺序硬件线程调整应用于硬件线程的时钟信号。

3. 发明申请

WO2010102134A1 APPARATUS AND METHOD TO TRANSLATE VIRTUAL ADDRESSES TO PHYSICAL ADDRESSES IN A BASE PLUS OFFSET ADDRESSING MODE 审中-公开
标题翻译：将虚拟地址转换为基本偏移寻址模式的物理地址的装置和方法
公开(公告)号：WO2010102134A1
公开(公告)日：2010-09-10
申请号：PCT/US2010/026249
申请日：2010-03-04
申请人： QUALCOMM INCORPORATED , BASSETT, Paul, Douglas , INGLE, Ajay, Anant , JAMIL, Sujat , CODRESCU, Lucian , AHMED, Muhammad
发明人： BASSETT, Paul, Douglas , INGLE, Ajay, Anant , JAMIL, Sujat , CODRESCU, Lucian , AHMED, Muhammad
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F2212/1016 , G06F2212/652 , G06F2212/654 , G06F2212/655
摘要： An apparatus and method to translate virtual addresses to physical addresses in a base plus offset addressing mode are disclosed. In an embodiment, a method includes performing a first translation lookaside buffer (TLB) lookup based on a base address value to retrieve a speculative physical address. While performing the TLB lookup based on the base address value, the base address value is added to an offset value to generate an effective address value. The method also includes performing a comparison of the base address value and the effective address value based on a variable page size to determine whether the speculative physical address corresponds to the effective address.
摘要翻译：公开了一种将虚拟地址转换为基本加偏移寻址模式的物理地址的装置和方法。在一个实施例中，一种方法包括基于基地址值执行第一翻译后备缓冲器（TLB）查找以检索推测性物理地址。在基于基地址值执行TLB查找的同时，将基地址值添加到偏移值以生成有效的地址值。该方法还包括基于可变页大小执行基地址值与有效地址值的比较，以确定推测物理地址是否对应于有效地址。

4. 发明申请

WO2009158254A1 SYSTEM AND METHOD TO PERFORM FAST ROTATION OPERATIONS 审中-公开
标题翻译：执行快速旋转操作的系统和方法
公开(公告)号：WO2009158254A1
公开(公告)日：2009-12-30
申请号：PCT/US2009/047671
申请日：2009-06-17
申请人： QUALCOMM INCORPORATED , KRITHIVASAN, Shankar , PLONDKE, Erich, James , CODRESCU, Lucian , ZENG, Mao , GURSKI, Remi, Jonathan
发明人： KRITHIVASAN, Shankar , PLONDKE, Erich, James , CODRESCU, Lucian , ZENG, Mao , GURSKI, Remi, Jonathan
IPC分类号： G06F9/30 , G06F9/315 , G06F7/548
CPC分类号： G06F9/30032 , G06F7/48 , G06F7/49921 , G06F7/768
摘要： Systems and methods to perform fast rotation operations are disclosed. In a particular embodiment, a method includes executing a single instruction. The method includes receiving first data indicating a first coordinate and a second coordinate, receiving a first control value that indicates a first rotation value selected from a set of ninety degree multiples, and writing output data corresponding to the first data rotated by the first rotation value.
摘要翻译：公开了执行快速旋转操作的系统和方法。在特定实施例中，一种方法包括执行单个指令。所述方法包括：接收指示第一坐标和第二坐标的第一数据，接收指示从九十度倍数的集合中选择的第一旋转值的第一控制值，以及写入与第一旋转值旋转的第一数据相对应的输出数据。

5. 发明申请

WO2009114289A1 SYSTEM AND METHOD OF SELECTIVELY COMMITTING A RESULT OF AN EXECUTED INSTRUCTION 审中-公开
标题翻译：选择执行结果的系统和方法
公开(公告)号：WO2009114289A1
公开(公告)日：2009-09-17
申请号：PCT/US2009/035372
申请日：2009-02-27
申请人： QUALCOMM INCORPORATED , CODRESCU, Lucian , LESTER, Robert, A. , TABONY, Charles, J. , PLONDKE, Erich, J. , ZENG, Mao , VENKUMAHANTI, Suresh, K. , INGLE, Ajay, A.
发明人： CODRESCU, Lucian , LESTER, Robert, A. , TABONY, Charles, J. , PLONDKE, Erich, J. , ZENG, Mao , VENKUMAHANTI, Suresh, K. , INGLE, Ajay, A.
IPC分类号： G06F9/38
CPC分类号： G06F9/3853 , G06F9/30036 , G06F9/30069 , G06F9/3826 , G06F9/3828 , G06F9/3889
摘要： In a particular embodiment, a method is disclosed that includes receiving an instruction packet including a first instruction and a second instruction that is dependent on the first instruction at a processor having a plurality of parallel execution pipelines, including a first execution pipeline and a second execution pipeline. The method further includes executing in parallel at least a portion of the first instruction and at least a portion of the second instruction. The method also includes selectively committing a second result of executing the at least a portion of the second instruction with the second execution pipeline based on a first result related to execution of the first instruction with the first execution pipeline.
摘要翻译：在特定实施例中，公开了一种方法，其包括在具有多个并行执行流水线的处理器处接收包括依赖于第一指令的第一指令和第二指令的指令分组，所述处理器包括第一执行流水线和第二执行管道。该方法还包括并行地执行第一指令的至少一部分和第二指令的至少一部分。该方法还包括基于与第一执行流水线执行第一指令相关的第一结果，选择性地提交执行具有第二执行流水线的第二指令的至少一部分的第二结果。

6. 发明申请

WO2008061102A2 EMBEDDED TRACE MACROCELL FOR ENHANCED DIGITAL SIGNAL PROCESSOR DEBUGGING OPERATIONS 审中-公开
标题翻译：用于增强型数字信号处理器调试操作的嵌入式宏跟踪器
公开(公告)号：WO2008061102A2
公开(公告)日：2008-05-22
申请号：PCT/US2007/084578
申请日：2007-11-13
申请人： QUALCOMM INCORPORATED , CODRESCU, Lucian , ANDERSON, William C. , VENKUMAHANTI, Suresh , GIANNINI, Louis Achille , PYLA, Manojkumar , CHEN, Xufeng
发明人： CODRESCU, Lucian , ANDERSON, William C. , VENKUMAHANTI, Suresh , GIANNINI, Louis Achille , PYLA, Manojkumar , CHEN, Xufeng
IPC分类号： G06F11/36
CPC分类号： G06F11/3656 , G06F9/3005
摘要： Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. The method and system improve software instruction debugging operations by capturing real-time information relating to software execution flow and include and instructions and circuitry for operating a core processor process within a core processor. A non-intrusive debugging process operates within a debugging mechanism of a digital signal processor. Non-intrusively monitoring in real time predetermined aspects of software execution occurs with the core processing process and occurs in real-time on the processor. An embedded trace macrocell records selectable aspects of the non-intrusively monitored software execution and generates at least one breakpoint in response to events arising within the selectable aspects of the non-intrusively monitored software execution. The present disclosure controls aspects of the non-intrusive debugging process in response to at least one breakpoint.
摘要翻译：用于设计和使用数字信号处理器的技术，包括（但不限于）用于处理通信（例如，CDMA）系统中的传输。该方法和系统通过捕获与软件执行流有关的实时信息来改进软件指令调试操作，并且包括用于在核心处理器内操作核心处理器过程的指令和电路。非侵入式调试过程在数字信号处理器的调试机制内运行。实时非侵入式地监控软件执行的预定方面与核心处理过程一起发生并且在处理器上实时发生。嵌入式跟踪宏小区记录非侵入式监控的软件执行的可选方面并且响应于在非侵入式监控的软件执行的可选方面内出现的事件而产生至少一个断点。本公开内容响应于至少一个断点来控制非侵入式调试过程的各个方面。

7. 发明申请

WO2007048133A3 POINTER COMPUTATION METHOD AND SYSTEM FOR A SCALABLE, PROGRAMMABLE CIRCULAR BUFFER 审中-公开
标题翻译：指针计算方法和系统，用于可扩展的可编程循环缓冲器
公开(公告)号：WO2007048133A3
公开(公告)日：2007-08-02
申请号：PCT/US2006060133
申请日：2006-10-20
申请人： QUALCOMM INC , PLONDKE ERICH , CODRESCU LUCIAN , AHMED MUHAMMAD , ZENG MAO , JAMIL SUJAT , ANDERSON WILLIAM C
发明人： PLONDKE ERICH , CODRESCU LUCIAN , AHMED MUHAMMAD , ZENG MAO , JAMIL SUJAT , ANDERSON WILLIAM C
IPC分类号： G06F9/355 , G06F5/06
CPC分类号： G06F5/10 , G06F9/3552 , G06F9/3851 , G06F2205/106
摘要： Techniques for processing digital signals for a variety of applications, including in a communications (e.g. , CDMA) system. A pointer location within a circular buffer is determined by establishing a length of the circular buffer, a start address that is aligned to a power of 2, and an end address located distant from the start address by the length and less than a power of 2 greater than the length. The method and system determine a current pointer location for an address within the circular buffer, a stride value of bits between the start address and the end address, a new pointer location within the circular buffer by adding the current pointer location to the stride value. An adjusted pointer location is within the circular buffer by an arithmetic operation of the new pointer location with the length.
摘要翻译：用于处理包括在通信（例如CDMA）系统中的各种应用的数字信号的技术。循环缓冲器中的指针位置通过建立循环缓冲器的长度，与2的幂对齐的起始地址和远离起始地址长度并小于2的幂的结束地址来确定大于长度。该方法和系统确定循环缓冲器内的地址的当前指针位置，起始地址和结束地址之间的比特的步幅值，通过将当前指针位置添加到步幅值，循环缓冲器内的新指针位置。通过具有长度的新指针位置的算术运算，调整的指针位置在循环缓冲器内。

8. 发明申请

WO2006110906A3 UNIFIED NON-PARTITIONED REGISTER FILES FOR A DIGITAL SIGNAL PROCESSOR OPERATING IN AN INTERLEAVED MULTI-THREADED ENVIRONMENT 审中-公开
标题翻译：用于数字信号处理器的统一的非分区寄存器文件在交互式多线程环境中运行
公开(公告)号：WO2006110906A3
公开(公告)日：2007-07-26
申请号：PCT/US2006014174
申请日：2006-04-11
申请人： QUALCOMM INC , CODRESCU LUCIAN , PLONDKE ERICH , AHMED MUHAMMAD , ANDERSON WILLIAM C , SIMPSON TAYLOR
发明人： CODRESCU LUCIAN , PLONDKE ERICH , AHMED MUHAMMAD , ANDERSON WILLIAM C , SIMPSON TAYLOR
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： H04M1/72522 , G06F9/3012 , G06F9/3885 , H04M1/2535 , H04M2250/02
摘要： A processor device is disclosed and includes a memory and a sequencer that is responsive to the memory. The sequencer can support very long instruction word (VLIW) instructions and superscalar instructions. The processor device further includes a first instruction execution unit responsive to the sequencer, a second instruction execution unit responsive to the sequencer, a third instruction execution unit responsive to the sequencer, and a fourth instruction execution unit responsive to the sequencer. Further, the processor device includes a plurality of register files and each of the plurality of register files includes a plurality of registers. The plurality of register files are coupled to the sequencer and coupled to the first instruction execution unit, the second instruction execution unit, the third instruction execution unit, and the fourth instruction execution unit.
摘要翻译：公开了处理器设备，并且包括响应于存储器的存储器和定序器。定序器可以支持非常长的指令字（VLIW）指令和超标量指令。处理器装置还包括响应于定序器的第一指令执行单元，响应于定序器的第二指令执行单元，响应于定序器的第三指令执行单元，以及响应于定序器的第四指令执行单元。此外，处理器装置包括多个寄存器文件，并且多个寄存器文件中的每一个包括多个寄存器。多个寄存器文件耦合到定序器并耦合到第一指令执行单元，第二指令执行单元，第三指令执行单元和第四指令执行单元。

9. 发明申请

WO2007048132A2 BACKGROUND THREAD PROCESSING IN A MULTITHREAD DIGITAL SIGNAL PROCESSOR 审中-公开
标题翻译：多线程数字信号处理器中的背景线程处理
公开(公告)号：WO2007048132A2
公开(公告)日：2007-04-26
申请号：PCT/US2006060132
申请日：2006-10-20
申请人： QUALCOMM INC , CODRESCU LUCIAN
发明人： CODRESCU LUCIAN
IPC分类号： G06F9/48
CPC分类号： G06F9/4812 , G06F9/30101 , G06F9/3851 , G06F12/0862
摘要： Techniques for the design and use of a digital signal processor, including processing transmissions in a communications (e.g., CDMA) system. The disclosed method and system provide background thread processing in a multithread digital signal processor for backgrounding and other background operations. The method and system form a background thread interrupt as one of a plurality of interrupt types, the background thread interrupt initiates a low-priority background process using one of a plurality of processing threads of a multithread digital signal processor. The process includes storing the background thread interrupt in an interrupt register and a background processing mask for associating with a processing thread of the multithread digital signal processor, which associates with at least a subset of said plurality of processing threads. Upon sensing a cache miss in one of the processing threads during multithread processing, the interrupt register issues the background thread interrupt and the digital signal processor initiates background processing using one of the processing threads having an associated background processing mask.
摘要翻译：用于设计和使用数字信号处理器的技术，包括处理通信（例如，CDMA）系统中的传输。所公开的方法和系统在用于背景和其他后台操作的多线程数字信号处理器中提供后台线程处理。该方法和系统形成作为多个中断类型之一的后台线程中断，后台线程中断使用多线程数字信号处理器的多个处理线程之一来发起低优先级后台进程。该过程包括将后台线程中断存储在中断寄存器和后台处理掩码中，用于与多线程数字信号处理器的处理线程相关联，该处理线程与所述多个处理线程的至少一个子集相关联。在多线程处理期间感测到其中一个处理线程中的高速缓存未命中时，中断寄存器发出后台线程中断，并且数字信号处理器使用具有相关联的后台处理掩码的处理线程之一发起后台处理。

10. 发明申请

WO2006105295A2 MIXED SUPERSCALAR AND VLIW INSTRUCTION ISSUING AND PROCESSING METHOD AND SYSTEM 审中-公开
标题翻译：混合超级和VLIW指令发布和处理方法和系统
公开(公告)号：WO2006105295A2
公开(公告)日：2006-10-05
申请号：PCT/US2006011646
申请日：2006-03-28
申请人： QUALCOMM INC , AHMED MUHAMMAD , PLONDKE ERICH , CODRESCU LUCIAN , ANDERSON WILLIAM C
发明人： AHMED MUHAMMAD , PLONDKE ERICH , CODRESCU LUCIAN , ANDERSON WILLIAM C
IPC分类号： G06F9/38
CPC分类号： G06F9/3853 , G06F9/3836 , G06F9/3838 , G06F9/3857
摘要： Techniques for processing transmissions in a communications (e.g., CDMA) system. A method and system for issuing and executing mixed architecture instructions in a multiple-issue digital signal processor receives in a mixed instruction listing a plurality of digital signal processor instructions. The plurality of digital signal processor instructions includes a plurality of parallel executable instructions (e.g., VLIW instructions or instruction packets) mixed among a plurality of series executable instructions (e.g., superscalar instructions). The series executable instructions are associated by various instruction dependencies. The method and system further identify in the mixed instruction listing the plurality of parallel executable instructions. Once identified, the parallel executable instructions are first executed in parallel irrespective of any such instruction's relative order in the mixed instruction listing. Then, the series executable instructions are executed serially according to said various instruction dependencies.
摘要翻译：用于在通信（例如，CDMA）系统中处理传输的技术。用于在多问题数字信号处理器中发出和执行混合架构指令的方法和系统以列出多个数字信号处理器指令的混合指令接收。多个数字信号处理器指令包括在多个串行可执行指令（例如，超标量指令）中混合的多个并行可执行指令（例如，VLIW指令或指令分组）。该系列可执行指令通过各种指令依赖关联。该方法和系统进一步标识列出多个并行可执行指令的混合指令。一旦确定，并行执行并行执行指令，而不管混合指令列表中的这种指令的相对顺序如何。然后，根据所述各种指令依赖性，串行执行指令被串行执行。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式