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1. 发明申请

WO2012162225A1 MEMORY WITH METADATA STORED IN A PORTION OF THE MEMORY PAGES 审中-公开
标题翻译：存储在存储器页的存储器中的存储器
公开(公告)号：WO2012162225A1
公开(公告)日：2012-11-29
申请号：PCT/US2012/038794
申请日：2012-05-21
申请人： QUALCOMM INCORPORATED , PLONDKE, Erich, James , CODRESCU, Lucian , ANDERSON, William, C.
发明人： PLONDKE, Erich, James , CODRESCU, Lucian , ANDERSON, William, C.
IPC分类号： G06F11/10
CPC分类号： G06F12/0893 , G06F11/1064 , G06F12/0646 , Y02D10/13
摘要： Systems and method for configuring a page-based memory device without pre-existing dedicated metadata. The method includes reading metadata from a metadata portion of a page of the memory device, and determining a characteristic of the page based on the metadata. The memory device may be configured as a cache. The metadata may include address tags, such that determining the characteristic may include determining if desired information is present in the page, and reading the desired information if it is determined to be present in the page. The metadata may also include error-correcting code (ECC), such that determining the characteristic may include detecting errors present in data stored in the page. The metadata may further include directory information, memory coherency information, or dirty/valid/lock information.
摘要翻译：用于配置基于页面的存储设备而不具有预先存在的专用元数据的系统和方法。该方法包括从存储设备的页面的元数据部分读取元数据，以及基于元数据确定页面的特性。存储器件可以被配置为高速缓存。元数据可以包括地址标签，使得确定特征可以包括确定页面中是否存在所需信息，并且如果确定存在于页面中则读取所需信息。元数据还可以包括纠错码（ECC），使得确定特性可以包括检测存在于页面中的数据中存在的错误。元数据还可以包括目录信息，存储器一致性信息或脏/有效/锁定信息。

2. 发明申请

WO2009158254A1 SYSTEM AND METHOD TO PERFORM FAST ROTATION OPERATIONS 审中-公开
标题翻译：执行快速旋转操作的系统和方法
公开(公告)号：WO2009158254A1
公开(公告)日：2009-12-30
申请号：PCT/US2009/047671
申请日：2009-06-17
申请人： QUALCOMM INCORPORATED , KRITHIVASAN, Shankar , PLONDKE, Erich, James , CODRESCU, Lucian , ZENG, Mao , GURSKI, Remi, Jonathan
发明人： KRITHIVASAN, Shankar , PLONDKE, Erich, James , CODRESCU, Lucian , ZENG, Mao , GURSKI, Remi, Jonathan
IPC分类号： G06F9/30 , G06F9/315 , G06F7/548
CPC分类号： G06F9/30032 , G06F7/48 , G06F7/49921 , G06F7/768
摘要： Systems and methods to perform fast rotation operations are disclosed. In a particular embodiment, a method includes executing a single instruction. The method includes receiving first data indicating a first coordinate and a second coordinate, receiving a first control value that indicates a first rotation value selected from a set of ninety degree multiples, and writing output data corresponding to the first data rotated by the first rotation value.
摘要翻译：公开了执行快速旋转操作的系统和方法。在特定实施例中，一种方法包括执行单个指令。所述方法包括：接收指示第一坐标和第二坐标的第一数据，接收指示从九十度倍数的集合中选择的第一旋转值的第一控制值，以及写入与第一旋转值旋转的第一数据相对应的输出数据。

3. 发明申请

WO2009114289A1 SYSTEM AND METHOD OF SELECTIVELY COMMITTING A RESULT OF AN EXECUTED INSTRUCTION 审中-公开
标题翻译：选择执行结果的系统和方法
公开(公告)号：WO2009114289A1
公开(公告)日：2009-09-17
申请号：PCT/US2009/035372
申请日：2009-02-27
申请人： QUALCOMM INCORPORATED , CODRESCU, Lucian , LESTER, Robert, A. , TABONY, Charles, J. , PLONDKE, Erich, J. , ZENG, Mao , VENKUMAHANTI, Suresh, K. , INGLE, Ajay, A.
发明人： CODRESCU, Lucian , LESTER, Robert, A. , TABONY, Charles, J. , PLONDKE, Erich, J. , ZENG, Mao , VENKUMAHANTI, Suresh, K. , INGLE, Ajay, A.
IPC分类号： G06F9/38
CPC分类号： G06F9/3853 , G06F9/30036 , G06F9/30069 , G06F9/3826 , G06F9/3828 , G06F9/3889
摘要： In a particular embodiment, a method is disclosed that includes receiving an instruction packet including a first instruction and a second instruction that is dependent on the first instruction at a processor having a plurality of parallel execution pipelines, including a first execution pipeline and a second execution pipeline. The method further includes executing in parallel at least a portion of the first instruction and at least a portion of the second instruction. The method also includes selectively committing a second result of executing the at least a portion of the second instruction with the second execution pipeline based on a first result related to execution of the first instruction with the first execution pipeline.
摘要翻译：在特定实施例中，公开了一种方法，其包括在具有多个并行执行流水线的处理器处接收包括依赖于第一指令的第一指令和第二指令的指令分组，所述处理器包括第一执行流水线和第二执行管道。该方法还包括并行地执行第一指令的至少一部分和第二指令的至少一部分。该方法还包括基于与第一执行流水线执行第一指令相关的第一结果，选择性地提交执行具有第二执行流水线的第二指令的至少一部分的第二结果。

4. 发明申请

WO2007048133A3 POINTER COMPUTATION METHOD AND SYSTEM FOR A SCALABLE, PROGRAMMABLE CIRCULAR BUFFER 审中-公开
标题翻译：指针计算方法和系统，用于可扩展的可编程循环缓冲器
公开(公告)号：WO2007048133A3
公开(公告)日：2007-08-02
申请号：PCT/US2006060133
申请日：2006-10-20
申请人： QUALCOMM INC , PLONDKE ERICH , CODRESCU LUCIAN , AHMED MUHAMMAD , ZENG MAO , JAMIL SUJAT , ANDERSON WILLIAM C
发明人： PLONDKE ERICH , CODRESCU LUCIAN , AHMED MUHAMMAD , ZENG MAO , JAMIL SUJAT , ANDERSON WILLIAM C
IPC分类号： G06F9/355 , G06F5/06
CPC分类号： G06F5/10 , G06F9/3552 , G06F9/3851 , G06F2205/106
摘要： Techniques for processing digital signals for a variety of applications, including in a communications (e.g. , CDMA) system. A pointer location within a circular buffer is determined by establishing a length of the circular buffer, a start address that is aligned to a power of 2, and an end address located distant from the start address by the length and less than a power of 2 greater than the length. The method and system determine a current pointer location for an address within the circular buffer, a stride value of bits between the start address and the end address, a new pointer location within the circular buffer by adding the current pointer location to the stride value. An adjusted pointer location is within the circular buffer by an arithmetic operation of the new pointer location with the length.
摘要翻译：用于处理包括在通信（例如CDMA）系统中的各种应用的数字信号的技术。循环缓冲器中的指针位置通过建立循环缓冲器的长度，与2的幂对齐的起始地址和远离起始地址长度并小于2的幂的结束地址来确定大于长度。该方法和系统确定循环缓冲器内的地址的当前指针位置，起始地址和结束地址之间的比特的步幅值，通过将当前指针位置添加到步幅值，循环缓冲器内的新指针位置。通过具有长度的新指针位置的算术运算，调整的指针位置在循环缓冲器内。

5. 发明申请

WO2006110906A3 UNIFIED NON-PARTITIONED REGISTER FILES FOR A DIGITAL SIGNAL PROCESSOR OPERATING IN AN INTERLEAVED MULTI-THREADED ENVIRONMENT 审中-公开
标题翻译：用于数字信号处理器的统一的非分区寄存器文件在交互式多线程环境中运行
公开(公告)号：WO2006110906A3
公开(公告)日：2007-07-26
申请号：PCT/US2006014174
申请日：2006-04-11
申请人： QUALCOMM INC , CODRESCU LUCIAN , PLONDKE ERICH , AHMED MUHAMMAD , ANDERSON WILLIAM C , SIMPSON TAYLOR
发明人： CODRESCU LUCIAN , PLONDKE ERICH , AHMED MUHAMMAD , ANDERSON WILLIAM C , SIMPSON TAYLOR
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： H04M1/72522 , G06F9/3012 , G06F9/3885 , H04M1/2535 , H04M2250/02
摘要： A processor device is disclosed and includes a memory and a sequencer that is responsive to the memory. The sequencer can support very long instruction word (VLIW) instructions and superscalar instructions. The processor device further includes a first instruction execution unit responsive to the sequencer, a second instruction execution unit responsive to the sequencer, a third instruction execution unit responsive to the sequencer, and a fourth instruction execution unit responsive to the sequencer. Further, the processor device includes a plurality of register files and each of the plurality of register files includes a plurality of registers. The plurality of register files are coupled to the sequencer and coupled to the first instruction execution unit, the second instruction execution unit, the third instruction execution unit, and the fourth instruction execution unit.
摘要翻译：公开了处理器设备，并且包括响应于存储器的存储器和定序器。定序器可以支持非常长的指令字（VLIW）指令和超标量指令。处理器装置还包括响应于定序器的第一指令执行单元，响应于定序器的第二指令执行单元，响应于定序器的第三指令执行单元，以及响应于定序器的第四指令执行单元。此外，处理器装置包括多个寄存器文件，并且多个寄存器文件中的每一个包括多个寄存器。多个寄存器文件耦合到定序器并耦合到第一指令执行单元，第二指令执行单元，第三指令执行单元和第四指令执行单元。

6. 发明申请

WO2006105295A2 MIXED SUPERSCALAR AND VLIW INSTRUCTION ISSUING AND PROCESSING METHOD AND SYSTEM 审中-公开
标题翻译：混合超级和VLIW指令发布和处理方法和系统
公开(公告)号：WO2006105295A2
公开(公告)日：2006-10-05
申请号：PCT/US2006011646
申请日：2006-03-28
申请人： QUALCOMM INC , AHMED MUHAMMAD , PLONDKE ERICH , CODRESCU LUCIAN , ANDERSON WILLIAM C
发明人： AHMED MUHAMMAD , PLONDKE ERICH , CODRESCU LUCIAN , ANDERSON WILLIAM C
IPC分类号： G06F9/38
CPC分类号： G06F9/3853 , G06F9/3836 , G06F9/3838 , G06F9/3857
摘要： Techniques for processing transmissions in a communications (e.g., CDMA) system. A method and system for issuing and executing mixed architecture instructions in a multiple-issue digital signal processor receives in a mixed instruction listing a plurality of digital signal processor instructions. The plurality of digital signal processor instructions includes a plurality of parallel executable instructions (e.g., VLIW instructions or instruction packets) mixed among a plurality of series executable instructions (e.g., superscalar instructions). The series executable instructions are associated by various instruction dependencies. The method and system further identify in the mixed instruction listing the plurality of parallel executable instructions. Once identified, the parallel executable instructions are first executed in parallel irrespective of any such instruction's relative order in the mixed instruction listing. Then, the series executable instructions are executed serially according to said various instruction dependencies.
摘要翻译：用于在通信（例如，CDMA）系统中处理传输的技术。用于在多问题数字信号处理器中发出和执行混合架构指令的方法和系统以列出多个数字信号处理器指令的混合指令接收。多个数字信号处理器指令包括在多个串行可执行指令（例如，超标量指令）中混合的多个并行可执行指令（例如，VLIW指令或指令分组）。该系列可执行指令通过各种指令依赖关联。该方法和系统进一步标识列出多个并行可执行指令的混合指令。一旦确定，并行执行并行执行指令，而不管混合指令列表中的这种指令的相对顺序如何。然后，根据所述各种指令依赖性，串行执行指令被串行执行。

7. 发明申请

WO2006102379A3 PROCESSOR AND METHOD OF GROUPING AND EXECUTING DEPENDENT INSTRUCTIONS IN A PACKET 审中-公开
公开(公告)号：WO2006102379A3
公开(公告)日：2006-09-28
申请号：PCT/US2006/010339
申请日：2006-03-21
申请人： QUALCOMM Incorporated , CRODESCU, Lucian , PLONDKE, Erich , AHMED, Muhammad , JAMIL, Sujat , ANDERSON, William C.
发明人： CRODESCU, Lucian , PLONDKE, Erich , AHMED, Muhammad , JAMIL, Sujat , ANDERSON, William C.
IPC分类号： G06F9/38
摘要： An interleaved multithreading pipeline operating method comprises reading an instruction packet containing at least two instructions, steering a first instruction of the instruction packet to a first execution unit for execution and generating a first result, steering a second instruction of the instruction packet to a second execution unit for execution using the first result and generating a second result, and storing the second result.

8. 发明申请

WO2011149828A1 SYSTEM AND METHOD TO EVALUATE A DATA VALUE AS AN INSTRUCTION 审中-公开
标题翻译：用于评估作为指令的数据值的系统和方法
公开(公告)号：WO2011149828A1
公开(公告)日：2011-12-01
申请号：PCT/US2011/037537
申请日：2011-05-23
申请人： QUALCOMM INCORPORATED , CODRESCU, Lucian , PLONDKE, Erich J. , VENKUMAHANTI, Suresh K.
发明人： CODRESCU, Lucian , PLONDKE, Erich J. , VENKUMAHANTI, Suresh K.
IPC分类号： G06F9/455 , G06F9/30
CPC分类号： G06F9/322 , G06F9/26 , G06F9/328
摘要： A system and method to evaluate a data value as an instruction is disclosed. For example, an apparatus configured to execute program code includes an execute unit configured to execute a first instruction associated with a location of a second instruction. The first instruction is identified by a program counter. The apparatus also includes a decode unit configured to receive the second instruction from the location and to decode the second instruction to generate a decoded second instruction without changing the program counter to point to the second instruction. The first and second instruction are virtual machine instructions and the execute unit is adapted to interprete these virtual machine instructions.
摘要翻译：公开了一种用于评估数据值作为指令的系统和方法。例如，被配置为执行程序代码的装置包括执行单元，被配置为执行与第二指令的位置相关联的第一指令。第一条指令由程序计数器识别。所述装置还包括：解码单元，被配置为从所述位置接收所述第二指令，并且解码所述第二指令以生成解码的第二指令，而不改变所述程序计数器以指向所述第二指令。第一和第二指令是虚拟机指令，并且执行单元适于分配这些虚拟机指令。

9. 发明申请

WO2011109476A1 SYSTEM AND METHOD OF PROCESSING HIERARCHICAL VERY LONG INSTRUCTION PACKETS 审中-公开
标题翻译：处理分层非常长的指令包的系统和方法
公开(公告)号：WO2011109476A1
公开(公告)日：2011-09-09
申请号：PCT/US2011/026815
申请日：2011-03-02
申请人： QUALCOMM INCORPORATED , CODRESCU, Lucian , PLONDKE, Erich James , INGLE, Ajay Anant , VENKUMAHANTI, Suresh K. , TABONY, Charles Joseph
发明人： CODRESCU, Lucian , PLONDKE, Erich James , INGLE, Ajay Anant , VENKUMAHANTI, Suresh K. , TABONY, Charles Joseph
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3853 , G06F9/30149
摘要： A system and method of processing a hierarchical very long instruction word (VLIW) packet is disclosed. In a particular embodiment, a method of processing instructions is disclosed. The method includes receiving a hierarchical VLIW packet of instructions and decoding an instruction from the packet to determine whether the instruction is a single instruction or whether the instruction includes a subpacket that includes a plurality of sub-instructions. The method also includes, in response to determining that the instruction includes the subpacket, executing each of the sub-instructions.
摘要翻译：公开了一种处理分级非常长的指令字（VLIW）分组的系统和方法。在特定实施例中，公开了一种处理指令的方法。该方法包括：接收分层VLIW指令分组，并对来自分组的指令进行解码，以确定该指令是单个指令还是指令是否包括包含多个子指令的子分组。响应于确定指令包括子分组，该方法还包括执行每个子指令。

10. 发明申请

WO2009158370A2 LOOP CONTROL SYSTEM AND METHOD 审中-公开
标题翻译：环路控制系统和方法
公开(公告)号：WO2009158370A2
公开(公告)日：2009-12-30
申请号：PCT/US2009/048370
申请日：2009-06-24
申请人： QUALCOMM INCORPORATED , CODRESCU, Lucian , PLONDKE, Erich , WANG, Lin , VENKUMAHANTI, Suresh, K.
发明人： CODRESCU, Lucian , PLONDKE, Erich , WANG, Lin , VENKUMAHANTI, Suresh, K.
IPC分类号： G06F9/445
CPC分类号： G06F8/4452 , G06F9/30072 , G06F9/325 , G06F9/3853 , G06F9/3885
摘要： Loop control systems and methods are disclosed. In a particular embodiment, a hardware loop control logic circuit includes a detection unit to detect an end of loop indicator of a program loop. The hardware loop control logic circuit also includes a decrement unit to decrement a loop count and to decrement a predicate trigger counter. The hardware loop control logic circuit further includes a comparison unit to compare the predicate trigger counter to a reference to determine when to set a predicate value.
摘要翻译：公开了回路控制系统和方法。在特定实施例中，硬件回路控制逻辑电路包括检测单元以检测程序循环的循环指示符的结束。硬件回路控制逻辑电路还包括递减单元，用于递减循环计数并递减谓词触发计数器。硬件循环控制逻辑电路还包括比较单元，用于将谓词触发计数器与参考值进行比较，以确定何时设置谓词值。

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