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1. 发明申请

WO0217494A3 NON-POWER-OF-TWO GREY-CODE COUNTER SYSTEM HAVING BINARY INCREMENTER WITH COUNTS DISTRIBUTED WITH BILATERAL SYMMETRY 审中-公开
标题翻译：具有二进制增值税的非双重灰色代码计数器系统，具有双向对称性分布
公开(公告)号：WO0217494A3
公开(公告)日：2004-02-26
申请号：PCT/EP0109573
申请日：2001-08-17
申请人： KONINKL PHILIPS ELECTRONICS NV
发明人： PONTIUS TIMOTHY A
IPC分类号： G06F5/12 , G06F5/10 , G06F5/14 , H03K23/00 , H03K23/66 , H03M7/16
CPC分类号： G06F5/14 , G06F2205/102 , G06F2205/106 , H03K23/005
摘要： A gray-code counter system (AP1) for a RAM-based FIFO comprises a read pointer (10), a write pointer (20), and a detector (30). The read pointer includes a gray-code decoder (11), a binary incrementer (12), a gray-code encoder (13), and a register (14) that holds the pointer count). The binary incrementer increments by 1 except when the input is 0110 (decimal 6) or 1110 (decimal 14); in these cases, it increments by 3. The result is a 4-bit modulo-12 gray-code sequence with the twelve allowed gray-code values being distributed among the sixteen possible 4-bit gray code values with translational and reflective bilateral symmetry. The write pointer is similar. Because of the translational symmetry, detectors that work with counters with modulo numbers that are power of two work with the corresponding non-power-of-two counter to provide "full" and "empty" indications. When read and write counts differ at the two most-significant bit positions but are equal at the remaining bit positions, the detector provides a "full" indication for a 6-count FIFO. The gray-code counter design is scaleable to any non-power-of-two modulo number divisible by four.
摘要翻译：用于基于RAM的FIFO的灰度计数器系统（AP1）包括读指针（10），写指针（20）和检测器（30）。读指针包括灰码解码器（11），二进制递增器（12），灰码编码器（13）和保存指针计数的寄存器（14）。二进制递增器递增1，除非输入为0110（十进制6）或1110（十进制14）; 在这些情况下，它增加3.结果是4位模12灰度序列，其中十二个允许的灰度值分布在具有平移和反射双边对称性的十六个可能的4位灰色码值中。写指针是类似的。由于平移对称性，使用具有模数的计数器的检测器是两个功能的计数器，与相应的非二功能计数器相结合来提供“完全”和“空”指示。当读和写计数在两个最高有效位位置不同但在其余位位置相等时，检测器为6位FIFO提供“满”指示。灰度计数器设计可以扩展到可以被四个整除的任何非二次幂模数。

2. 发明申请

WO2003039061A2 CLOCK DOMAIN CROSSING FIFO 审中-公开
标题翻译：时域交叉FIFO
公开(公告)号：WO2003039061A2
公开(公告)日：2003-05-08
申请号：PCT/IB2002/004076
申请日：2002-10-02
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V.
发明人： PONTIUS, Timothy, A. , PAYNE, Robert, L. , EVOY, David, R.
IPC分类号： H04L7/02
CPC分类号： H04L7/02 , G06F5/10 , G06F2205/102 , H04L7/0008 , H04L7/005
摘要： A method and arrangement of passing data from a source clock domain to a non-synchronous receive clock domain are provided. A first processing circuit, located in the source clock domain, links write-address information with the data, and a clock generator generates a transmit clock signal in the source clock domain synchronous with a source clock. The first processing circuit transmits the clock signal and the data with the linked write-address information to a second processing circuit in the receive clock domain. In the receive clock domain, the second processing circuit writes the data at an address designating a storage element corresponding to the linked write-address information. The second processing circuit clocks the data into the storage element synchronous with the accompanying transmit clock signal responsive to a write enable signal from the source clock domain, and reads the data out of the storage element synchronous with a receive domain clock.
摘要翻译：提供了将数据从源时钟域传递到非同步接收时钟域的方法和装置。位于源时钟域的第一处理电路将写入地址信息与数据相连接，并且时钟发生器在与源时钟同步的源时钟域中生成发送时钟信号。第一处理电路将时钟信号和具有链接的写入地址信息的数据发送到接收时钟域中的第二处理电路。在接收时钟域中，第二处理电路将数据写入指定对应于链接的写入地址信息的存储元件的地址。第二处理电路响应于来自源时钟域的写入使能信号将数据与伴随的发送时钟信号同步地存储到存储元件中，并且从存储元件读出与接收域时钟同步的数据。

3. 发明申请

WO1990004294A1 METHOD AND APPARATUS FOR DETECTING IMPENDING OVERFLOW AND/OR UNDERRUN OF ELASTICITY BUFFER 审中-公开
标题翻译：用于检测弹性缓冲区溢出和/或暴露的方法和装置
公开(公告)号：WO1990004294A1
公开(公告)日：1990-04-19
申请号：PCT/US1989001691
申请日：1989-04-26
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： DIGITAL EQUIPMENT CORPORATION , IANNARONE, John, R. , THOMPSON, Bruce, W.
IPC分类号： H04J03/06
CPC分类号： G06F5/14 , G06F2205/102 , H04J3/0632
摘要： A parallel asynchronous elasticity buffer. Selection of the address of a storage element for writing or reading of data is provided by asynchronous input and output pointers implemented using circular gray code counters. The buffer is initialized once during transmission of each frame of data so that the pointers do not select the same storage element for writing and reading at the same time. Write overflow or read underrun of a storage element is detected before any data corruption can occur by comparing the input and output pointers. An error condition is detected if the input and output pointers overlap for a threshold period, which can be shorter than the period required for writing or reading of a multibit data unit to or from the buffer. The overlap time period is determined by comparing the pointers at one or more sampling times corresponding to selected phases of a clock signal.
摘要翻译：并行异步弹性缓冲器。选择用于写入或读取数据的存储元件的地址由使用循环灰度代码计数器实现的异步输入和输出指针提供。在每帧数据的传输期间，缓冲器被初始化一次，使得指针不会同时选择用于写入和读取的相同存储元件。在通过比较输入和输出指针发生任何数据损坏之前，检测到存储元件的写入溢出或读取欠载。如果输入和输出指针重叠一个阈值周期，那么可以检测出错误条件，该阈值周期可能短于向缓冲器写入或读取多位数据单元所需的周期。通过在对应于时钟信号的所选相位的一个或多个采样时间比较指针来确定重叠时间段。

4. 发明申请

WO2014027328A1 METHOD AND APPARATUS FOR TRANSFERRING DATA FROM A FIRST DOMAIN TO A SECOND DOMAIN 审中-公开
标题翻译：将数据从第一个域传输到第二个域的方法和装置
公开(公告)号：WO2014027328A1
公开(公告)日：2014-02-20
申请号：PCT/IB2013/056660
申请日：2013-08-15
申请人： RENESAS MOBILE CORPORATION , KULMALA, Ari Tapani , SERTAMO, Jaakko Illmari
发明人： KULMALA, Ari Tapani , SERTAMO, Jaakko Illmari
IPC分类号： G06F5/10
CPC分类号： G06F3/0656 , G06F3/0644 , G06F5/10 , G06F13/124 , G06F13/1689 , G06F2205/102
摘要： Data is written from a first domain (117) to a FIFO memory buffer (105) in a second domain(119). The first domain (117) uses a first clock signal, the second domain (119) uses a second clock signal and the memory buffer (105) uses the first clock signal that is delivered alongside the data. The data is read from the memory buffer(105)using the second clock signal. A read pointer is adjusted and synchronised with the delivered first clock signal. A token is generated using the delivered first clock signal, based on the read pointer. The token represents a capacity of the memory buffer (105) having been made available. The token is passed to the first domain (117) and synchronised with the first clock signal. The writing of data to the memory buffer (105) is controlled based on a comparison between the synchronised token and a previously received token.
摘要翻译：将数据从第一域（117）写入到第二域（119）中的FIFO存储缓冲器（105）。第一域（117）使用第一时钟信号，第二域（119）使用第二时钟信号，并且存储器缓冲器（105）使用与数据一起传送的第一时钟信号。使用第二时钟信号从存储器缓冲器（105）读取数据。读取指针被调整并与所传送的第一时钟信号同步。基于读取指针，使用传递的第一时钟信号生成令牌。令牌表示存储缓冲器（105）已经可用的容量。令牌被传递到第一域（117）并与第一时钟信号同步。基于同步令牌和先前接收的令牌之间的比较来控制向存储器缓冲器（105）写入数据。

5. 发明申请

WO2013025637A1 DATA STORAGE FOR VOLTAGE DOMAIN CROSSINGS 审中-公开
标题翻译：数据存储用于电压域交叉
公开(公告)号：WO2013025637A1
公开(公告)日：2013-02-21
申请号：PCT/US2012/050641
申请日：2012-08-13
申请人： QUALCOMM Incorporated , KOOB, Christopher Edward , LIN, Jen Tsung , PYLA, Manojkumar , SAINT-LAURENT, Martin
发明人： KOOB, Christopher Edward , LIN, Jen Tsung , PYLA, Manojkumar , SAINT-LAURENT, Martin
IPC分类号： G06F5/06
CPC分类号： G06F5/06 , G06F5/10 , G06F5/14 , G06F2205/102 , G11C5/145
摘要： According to an embodiment, an apparatus includes a data storage device. Data to be stored in the data storage device is level shifted from a first voltage domain to a second voltage domain prior to being stored within the data storage device. The data storage device is powered by the second voltage domain. The apparatus further includes a circuit that is powered by the second voltage domain and that is responsive to data output by the data storage device.
摘要翻译：根据实施例，一种装置包括数据存储装置。要存储在数据存储设备中的数据在被存储在数据存储设备中之前从第一电压域电平移位到第二电压域。数据存储设备由第二电压域供电。该装置还包括由第二电压域供电并且响应于数据存储装置输出的数据的电路。

6. 发明申请

WO03005219A2 MULTIPROCESSOR SYSTEM AND METHOD FOR OPERATING A MULTIPROCESSOR SYSTEM 审中-公开
标题翻译：用于操作多处理器系统的多处理器系统和方法
公开(公告)号：WO03005219A2
公开(公告)日：2003-01-16
申请号：PCT/IB0202337
申请日：2002-06-20
申请人： KONINKL PHILIPS ELECTRONICS NV , KANG I-CHIH , GANGWAL OM P , NIEUWLAND ANDRE K
发明人： KANG I-CHIH , GANGWAL OM P , NIEUWLAND ANDRE K
IPC分类号： G06F9/38 , G06F9/46 , G06F9/52 , G06F15/16 , G06F15/177 , H04L7/00
CPC分类号： G06F5/12 , G06F9/52 , G06F2205/102
摘要： A multiprocessor system according to the invention comprises at least a dedicated processor (1, 6) and a further processor (1, 3), and a memory (1, 5) shared by the processors. The shared memory (1, 5) and processors (1, 6, 1, 3) are coupled to an interconnect ion network (1, 7). The processors are arranged for transferring data to each other via a buffer (2, 1) in accordance with a synchronization protocol. The dedicated processor (1, 3) comprises facilities for administrating information relating to the synchronization protocol and a copy of at least part of this information is maintained in the shared memory (2, 1).
摘要翻译：根据本发明的多处理器系统至少包括由处理器共享的专用处理器（1,6）和另外的处理器（1,3）以及存储器（1,5）。共享存储器（1,5）和处理器（1,6,1,3）被耦合到互连离子网络（1,7）。处理器被安排用于根据同步协议经由缓冲器（2,1）将数据彼此传送。专用处理器（1,3）包括用于管理与同步协议有关的信息的设施，并且该信息的至少一部分的副本被保存在共享存储器（2,1）中。

7. 发明申请

WO2008001285A1 ASYNCHRONOUS DATA FIFO THAT PROVIDES UNINTERRUPTED DATA FLOW 审中-公开
标题翻译：异步数据FIFO，提供不间断的数据流
公开(公告)号：WO2008001285A1
公开(公告)日：2008-01-03
申请号：PCT/IB2007/052402
申请日：2007-06-21
申请人： NXP B.V. , KOUTSOURES, Dennis , SVESTKA, Ivan
发明人： KOUTSOURES, Dennis , SVESTKA, Ivan
IPC分类号： H04J3/06 , G06F5/12
CPC分类号： H04L49/901 , G06F5/12 , G06F2205/102 , H04L7/02 , H04L47/30 , H04L49/90
摘要： An asynchronous FIFO is provided that determines whether its buffer is primed with at least one data element during a data transfer across clock domains in order to eliminate metastability issues that cause data stalls and interruptions in data flow.
摘要翻译：提供了异步FIFO，其在跨时钟域的数据传输期间确定其缓冲器是否被至少一个数据元素引用，以消除导致数据流失和数据流中断的亚稳态问题。

8. 发明申请

WO2003003232A2 DATA PROCESSING APPARATUS AND A METHOD OF SYNCHRONIZING A FIRST AND A SECOND PROCESSING MEANS IN A DATA PROCESSING APPARATUS 审中-公开
标题翻译：数据处理装置和在数据处理装置中同步第一和第二处理装置的方法
公开(公告)号：WO2003003232A2
公开(公告)日：2003-01-09
申请号：PCT/IB2002/002417
申请日：2002-06-20
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , NIEUWLAND, Andre, K. , LIPPENS, Paul, E., R. , GANGWAL, Om, P.
发明人： NIEUWLAND, Andre, K. , LIPPENS, Paul, E., R. , GANGWAL, Om, P.
IPC分类号： G06F15/16
CPC分类号： G06F5/12 , G06F9/52 , G06F2205/102
摘要： A data processing apparatus according to the invention comprising at least a first (1.2) and a second processing means (1.3). The first processing means being capable of providing data by writing tokens in a buffer means (2.1) which are readable by the second processing means for further processing. The processing means are assigned a first and a second synchronization counter. The first synchronization counter (writec) is modifiable by the first processing means (2.1)and is readable by the second processing means (1.3). The second synchronization counter (readc) is modifiable by the second processing means (1.3), and readable by the first processing means (1.2). The first synchronization counter (writec) is indicative for a number of tokens being written by the first processing means (1.2). The second synchronization counter (readc) is indicative for a number of tokens being read by the second processing means (1.3).
摘要翻译：根据本发明的数据处理装置至少包括第一（1.2）和第二处理装置（1.3）。第一处理装置能够通过在缓冲器装置（2.1）中写入令牌来提供数据，缓冲器装置（2.1）可由第二处理装置读取以进一步处理。处理装置被分配有第一和第二同步计数器。第一同步计数器（writec）可由第一处理装置（2.1）修改，并且可由第二处理装置（1.3）读取。第二同步计数器（readc）可由第二处理装置（1.3）修改，并且可由第一处理装置（1.2）读取。第一同步计数器（writec）指示由第一处理装置（1.2）写入的许多令牌。第二同步计数器（readc）指示由第二处理装置读取的令牌数量（1.3）。

9. 发明申请

WO01079987A1 TWO CLOCK DOMAIN PULSE TO PULSE SYNCHRONIZER 审中-公开
标题翻译：两个时钟脉冲脉冲同步器
公开(公告)号：WO01079987A1
公开(公告)日：2001-10-25
申请号：PCT/IT2000/000153
申请日：2000-04-17
IPC分类号： G06F5/06 , H04L7/02
CPC分类号： G06F5/06 , G06F2205/102 , H04L7/02
摘要： A synchronization circuit (P2P) for interfacing a first digital circuit functioning with a first clock (CLK1) and a second digital circuit functioning with a second clock (CLK2) that may be different from the first clock (CLK1) in terms of frequency and/or phase is constituted by a transmitting section functioning with the first clock (CLK1), a receiving section functioning with the second clock (CLK2) and a feedback section functioning with the first clock (CLK1). A bidirectional synchronizer transfers commands with a strobe signal (STR) from a microprocessor interface (MPRI) functioning with the first clock (CLK1) to an application circuit (APL) functioning with the second clock (CLK2) and alarm signals from the application circuit (APL) to the microprocessor interface (MPRI).
摘要翻译：一种同步电路（P2P），用于将与第一时钟（CLK1）起作用的第一数字电路和与第一时钟（CLK1）不同的第二时钟（CLK2）功能的第二数字电路（频率和/ 或相位由与第一时钟（CLK1）起作用的发送部分，与第二时钟（CLK2）起作用的接收部分和与第一时钟（CLK1）起作用的反馈部分构成。双向同步器将来自与第一时钟（CLK1）功能的微处理器接口（MPRI）的选通信号（STR）的命令传送到与第二时钟（CLK2）起作用的应用电路（APL）和来自应用电路的报警信号 APL）到微处理器接口（MPRI）。

10. 发明申请

WO2014001766A1 DATA TRANSFER BETWEEN CLOCK DOMAINS 审中-公开
标题翻译：时钟域之间的数据传输
公开(公告)号：WO2014001766A1
公开(公告)日：2014-01-03
申请号：PCT/GB2013/051609
申请日：2013-06-20
申请人： NORDIC SEMICONDUCTOR ASA , SAMUELS, Adrian
发明人： SKOGLUND, Per Carsten , HAVASHKI, Asghar , VENÅS, Arne Wanvik , HOLEN, Åsmund , HJERTØ, Markus Bakka
IPC分类号： G06F5/06
CPC分类号： G06F5/06 , G06F2205/061 , G06F2205/102
摘要： An arrangement for transferring a data signal (data_a) from a first clock domain (2) to a second clock domain (4) in a digital system. The arrangement has a signal input (6, 7) for receiving an input signal (data_a) from the first clock domain (2), means (6, 7) for storing the input signal (data_a), and means (12, 13) for transferring the input signal (data_a) to the second clock domain (4) following a transition in the clock signal (ck) of the second clock domain (4).
摘要翻译：一种用于在数字系统中将数据信号（data_a）从第一时钟域（2）传送到第二时钟域（4）的装置。该装置具有用于从第一时钟域（2）接收输入信号（data_a）的信号输入（6,7），用于存储输入信号（data_a）的装置（6,7）和装置（12,13）用于在第二时钟域（4）的时钟信号（ck）中的转变之后将输入信号（data_a）传送到第二时钟域（4）。

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