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1. 发明申请

WO2006058200A3 MICRO-THREADED MEMORY 审中-公开
公开(公告)号：WO2006058200A3
公开(公告)日：2006-06-01
申请号：PCT/US2005/042722
申请日：2005-11-23
申请人： RAMBUS INC. , WARE, Frederick, A. , HAMPEL, Craig, E. , RICHARDSON, Wayne, S. , BELLOWS, Chad, A. , LAI, Lawrence
发明人： WARE, Frederick, A. , HAMPEL, Craig, E. , RICHARDSON, Wayne, S. , BELLOWS, Chad, A. , LAI, Lawrence
IPC分类号： G11C7/22
摘要： A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval.

2. 发明申请

WO2006039106A1 MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTERGRATED CIRCUIT MEMORY DEVICE 审中-公开
标题翻译：包括集成电路存储器件的多字段寻址模式存储器系统
公开(公告)号：WO2006039106A1
公开(公告)日：2006-04-13
申请号：PCT/US2005/032770
申请日：2005-09-12
申请人： RAMBUS INC. , WARE, Frederick, A. , LAI, Lawrence , BELLOWS, Chad, A. , RICHARDSON, Wayne, S.
发明人： WARE, Frederick, A. , LAI, Lawrence , BELLOWS, Chad, A. , RICHARDSON, Wayne, S.
IPC分类号： G11C8/12 , G11C8/16
CPC分类号： G11C8/10 , G11C8/12 , G11C8/16
摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. During a third mode of operation, a first plurality of storage cells in a first row of storage cells in a first memory bank is accessible in response to a first column address. A second plurality of storage cells in a second row of storage cells in a second bank is accessible in response to a second column address. A third plurality of storage cells in the first row of storage cells is accessible in response to a third column address and a fourth plurality of storage cells in the second row of storage cells is accessible in response to a fourth column address. The first and second column addresses are in a first request packet and the third and fourth column addresses are in a second request packet provided by the master device.
摘要翻译：存储器系统包括主设备，诸如图形控制器或处理器，以及以双列寻址模式可操作的集成电路存储器件。集成电路存储器件包括一个接口和列解码器，以访问存储单元行或存储体中的页面。在第一操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元。在第二操作模式期间，响应于列周期时间间隔期间的第二列地址，可访问第一行存储单元中的第一多个存储单元。响应于列周期时间间隔期间的第三列地址，可访问第一行存储单元中的第二多个存储单元。在第三操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元中的第一多个存储单元。响应于第二列地址，可访问第二存储体中第二行存储单元中的第二多个存储单元。第一行存储单元中的第三多个存储单元响应于第三列地址而可访问，并且第二行存储单元中的第四多个存储单元响应于第四列地址而可访问。第一列地址和第二列地址在第一请求分组中，并且第三和第四列地址在由主设备提供的第二请求分组中。

3. 发明申请

WO2006023391A1 MEMORY DEVICE HAVING STAGGERED MEMORY OPERATIONS 审中-公开
标题翻译：具有存储器存储器操作的存储器件
公开(公告)号：WO2006023391A1
公开(公告)日：2006-03-02
申请号：PCT/US2005/028728
申请日：2005-08-11
申请人： RAMBUS INC. , LAI, Lawrence , RICHARDSON, Wayne, S. , BELLOWS, Chad, A.
发明人： LAI, Lawrence , RICHARDSON, Wayne, S. , BELLOWS, Chad, A.
IPC分类号： G11C7/10 , G11C7/22 , G11C8/12
CPC分类号： G11C7/1042 , G11C7/22 , G11C8/12 , G11C2207/2227
摘要： A memory system includes logical banks divided into sub-banks or collections of sub-banks. The memory system responds to memory-access requests (e.g., read and write) directed to a given logical bank by sequentially accessing sub-banks or collections of sub-banks. Sequential access reduces the impact of power-supply spikes induced by memory operations, and thus facilitates improved system performance. Some embodiments of the memory system combine sequential sub-bank access with other performance-enhancing features, such as wider power buses or increased bypass capacitance, to further enhance performance.
摘要翻译：记忆系统包括分为子银行或子银行集合的逻辑银行。存储器系统通过顺序地访问子银行或子银行集合来响应指向给定逻辑银行的存储器访问请求（例如，读取和写入）。顺序访问减少了由存储器操作引起的电源尖峰的影响，从而有助于提高系统性能。存储器系统的一些实施例将顺序的子银行访问与诸如更宽的电源总线或增加的旁路电容的其他性能增强特征相结合，以进一步提高性能。

4. 发明申请

WO2012115839A1 PROTOCOL FOR MEMORY POWER-MODE CONTROL 审中-公开
标题翻译：用于存储器功率模式控制的协议
公开(公告)号：WO2012115839A1
公开(公告)日：2012-08-30
申请号：PCT/US2012/025310
申请日：2012-02-15
申请人： RAMBUS INC. , ELLIS, Wayne F. , RICHARDSON, Wayne S. , BANSAL, Akash , WARE, Frederick A. , LAI, Lawrence , KASAMSETTY, Kishore Ven
发明人： ELLIS, Wayne F. , RICHARDSON, Wayne S. , BANSAL, Akash , WARE, Frederick A. , LAI, Lawrence , KASAMSETTY, Kishore Ven
IPC分类号： G11C7/10 , G11C11/4096 , G11C11/402 , G06F13/14
CPC分类号： G11C11/40615 , G06F1/3234 , G11C7/02 , G11C7/20 , G11C11/4072 , G11C11/4074 , G11C29/022 , G11C29/028
摘要： In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.
摘要翻译：在一个实施例中，存储器设备包括存储器核心和用于接收命令和数据的输入接收器。存储器装置还包括寄存器，用于存储指示输入接收器的子集是否响应于控制信号掉电的值。存储器控制器将命令和数据发送到存储器件。存储器控制器还发送该值以指示存储器件的输入接收器的子集是否响应于控制信号掉电。此外，响应于自我新命令，存储装置延迟进入自刷新操作，直到接收到接收到自刷新命令之后接收到的控制信号。

5. 发明申请

WO2013028854A1 METHODS AND SYSTEMS FOR MAPPING A PERIPHERAL FUNCTION ONTO A LEGACY MEMORY INTERFACE 审中-公开
标题翻译：用于将外围功能映射到遗传存储器接口的方法和系统
公开(公告)号：WO2013028854A1
公开(公告)日：2013-02-28
申请号：PCT/US2012/052052
申请日：2012-08-23
申请人： Rambus Inc. , PEREGO, Richard, E. , BATRA, Pradeep , WOO, Steven , LAI, Lawrence , YEUNG, Chi-Ming
发明人： PEREGO, Richard, E. , BATRA, Pradeep , WOO, Steven , LAI, Lawrence , YEUNG, Chi-Ming
IPC分类号： G06F13/14 , G06F13/38 , G11C7/10
CPC分类号： G06F3/061 , G06F3/0629 , G06F3/0685 , G06F12/00 , G06F12/0246 , G06F12/0638 , G06F12/10 , G06F13/385 , G06F13/4239 , G06F2212/2022 , G06F2212/205 , G06F2212/251 , G06F2212/7201 , G06F2212/7206 , G11C7/1072 , G11C14/0018 , Y02D10/14 , Y02D10/151
摘要： A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.
摘要翻译：存储器系统包括将命令和地址传送到主存储器模块的CPU。该模块包含一个缓冲电路，用于在CPU和主存储器之间中继命令和数据。存储器模块还包括嵌入式处理器，其共享对主存储器的访问以支持诸如图形处理等外围功能，以提高整体系统性能。缓冲电路有助于CPU和外设处理器之间的指令和数据通信，其方式可以最大限度地减少或消除修改CPU的需求，从而降低采用具有集成处理能力的主内存模块的实际障碍。

6. 发明申请

WO2013028859A1 METHODS AND SYSTEMS FOR MAPPING A PERIPHERAL FUNCTION ONTO A LEGACY MEMORY INTERFACE 审中-公开
公开(公告)号：WO2013028859A1
公开(公告)日：2013-02-28
申请号：PCT/US2012/052059
申请日：2012-08-23
申请人： Rambus Inc. , PEREGO, Richard E. , BATRA, Pradeep , WOO, Steven , LAI, Lawrence , YEUNG, Chi-Ming
发明人： PEREGO, Richard E. , BATRA, Pradeep , WOO, Steven , LAI, Lawrence , YEUNG, Chi-Ming
IPC分类号： G06F13/14 , G06F13/38 , G11C7/10
CPC分类号： G06F3/061 , G06F3/0629 , G06F3/0685 , G06F12/00 , G06F12/0246 , G06F12/0638 , G06F12/10 , G06F13/385 , G06F13/4239 , G06F2212/2022 , G06F2212/205 , G06F2212/251 , G06F2212/7201 , G06F2212/7206 , G11C7/1072 , G11C14/0018 , Y02D10/14 , Y02D10/151
摘要： A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.

7. 发明申请

WO2013028849A1 METHODS AND SYSTEMS FOR MAPPING A PERIPHERAL FUNCTION ONTO A LEGACY MEMORY INTERFACE 审中-公开
公开(公告)号：WO2013028849A1
公开(公告)日：2013-02-28
申请号：PCT/US2012/052043
申请日：2012-08-23
申请人： RAMBUS INC. , PEREGO, Richard E. , BATRA, Pradeep , WOO, Steven , LAI, Lawrence , YEUNG, Chi-Ming
发明人： PEREGO, Richard E. , BATRA, Pradeep , WOO, Steven , LAI, Lawrence , YEUNG, Chi-Ming
IPC分类号： G11C7/10 , G06F13/14
CPC分类号： G06F3/061 , G06F3/0629 , G06F3/0685 , G06F12/00 , G06F12/0246 , G06F12/0638 , G06F12/10 , G06F13/385 , G06F13/4239 , G06F2212/2022 , G06F2212/205 , G06F2212/251 , G06F2212/7201 , G06F2212/7206 , G11C7/1072 , G11C14/0018 , Y02D10/14 , Y02D10/151
摘要： A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.

8. 发明申请

WO2008014413A3 CROSS-THREADED MEMORY DEVICE AND SYSTEM 审中-公开
公开(公告)号：WO2008014413A3
公开(公告)日：2008-01-31
申请号：PCT/US2007/074513
申请日：2007-07-26
申请人： RAMBUS INC. , WARE, Frederick A. , KASAMSETTY, Kishore , LAI, Lawrence , FANG, Wayne , PENG, Liang
发明人： WARE, Frederick A. , KASAMSETTY, Kishore , LAI, Lawrence , FANG, Wayne , PENG, Liang
IPC分类号： G06F13/16
摘要： Within an integrated-circuit (IC) memory device, and during a first interval, a first storage location within a first memory array and a second storage location within a second memory array are concurrently accessed via first and second external signaling interfaces, respectively. During a second interval, a third storage location within the first memory array and a fourth storage location within the second memory array are concurrently accessed via the first and second external signaling interfaces.

9. 发明申请

WO2013028827A1 METHODS AND SYSTEMS FOR MAPPING A PERIPHERAL FUNCTION ONTO A LEGACY MEMORY INTERFACE 审中-公开
标题翻译：将外部功能映射到记忆体界面的方法和系统
公开(公告)号：WO2013028827A1
公开(公告)日：2013-02-28
申请号：PCT/US2012/052000
申请日：2012-08-23
申请人： RAMBUS INC. , PEREGO, Richard, E. , LINSTADT, John, Eric , BATRA, Pradeep , BROOKS, John, Welsford , WOO, Steven , LAI, Lawrence
发明人： PEREGO, Richard, E. , LINSTADT, John, Eric , BATRA, Pradeep , BROOKS, John, Welsford , WOO, Steven , LAI, Lawrence
IPC分类号： G06F13/14 , G06F13/16 , G11C7/10
CPC分类号： G06F3/061 , G06F3/0629 , G06F3/0685 , G06F12/00 , G06F12/0246 , G06F12/0638 , G06F12/10 , G06F13/385 , G06F13/4239 , G06F2212/2022 , G06F2212/205 , G06F2212/251 , G06F2212/7201 , G06F2212/7206 , G11C7/1072 , G11C14/0018 , Y02D10/14 , Y02D10/151
摘要： A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.
摘要翻译：存储器系统包括将命令和地址传送到主存储器模块的CPU。该模块包括缓冲电路，用于中继CPU和主存储器之间的命令和数据。存储器模块还包括嵌入式处理器，其共享对主存储器的访问以支持外围功能，例如图形处理，以改善整体系统性能。缓冲电路有助于CPU和外围处理器之间的指令和数据通信，以最小化或消除修改CPU的需要，从而减少采用具有集成处理能力的主存储器模块的实际障碍。

10. 发明申请

WO2011022114A1 ATOMIC MEMORY DEVICE 审中-公开
标题翻译：原子记忆装置
公开(公告)号：WO2011022114A1
公开(公告)日：2011-02-24
申请号：PCT/US2010/039095
申请日：2010-06-17
申请人： RAMBUS INC. , SHEFFLER, Thomas , LAI, Lawrence , PENG, Liang , RYCHLIK, Bohuslav
发明人： SHEFFLER, Thomas , LAI, Lawrence , PENG, Liang , RYCHLIK, Bohuslav
IPC分类号： G11C8/04 , G11C7/10 , G11C7/22
CPC分类号： G06F12/023 , G06F2212/2024 , G11C7/1006 , G11C7/1039 , G11C7/22 , G11C8/10 , G11C2207/107
摘要： In an integrated-circuit memory device having a memory core, a first data value is retrieved from an address-specified location within the memory core in response to a memory access command. The first data value is output from the memory device in response to the memory access command, and a second data value is stored in the address-specified location within the memory core in response to the memory access command.
摘要翻译：在具有存储器核心的集成电路存储器件中，响应于存储器访问命令，从存储器内核中的地址指定位置检索第一数据值。响应于存储器访问命令，从存储器件输出第一数据值，并且响应于存储器访问命令，将第二数据值存储在存储器内核中的地址指定位置中。

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