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1. 发明申请

WO2012115839A1 PROTOCOL FOR MEMORY POWER-MODE CONTROL 审中-公开
标题翻译：用于存储器功率模式控制的协议
公开(公告)号：WO2012115839A1
公开(公告)日：2012-08-30
申请号：PCT/US2012/025310
申请日：2012-02-15
申请人： RAMBUS INC. , ELLIS, Wayne F. , RICHARDSON, Wayne S. , BANSAL, Akash , WARE, Frederick A. , LAI, Lawrence , KASAMSETTY, Kishore Ven
发明人： ELLIS, Wayne F. , RICHARDSON, Wayne S. , BANSAL, Akash , WARE, Frederick A. , LAI, Lawrence , KASAMSETTY, Kishore Ven
IPC分类号： G11C7/10 , G11C11/4096 , G11C11/402 , G06F13/14
CPC分类号： G11C11/40615 , G06F1/3234 , G11C7/02 , G11C7/20 , G11C11/4072 , G11C11/4074 , G11C29/022 , G11C29/028
摘要： In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.
摘要翻译：在一个实施例中，存储器设备包括存储器核心和用于接收命令和数据的输入接收器。存储器装置还包括寄存器，用于存储指示输入接收器的子集是否响应于控制信号掉电的值。存储器控制器将命令和数据发送到存储器件。存储器控制器还发送该值以指示存储器件的输入接收器的子集是否响应于控制信号掉电。此外，响应于自我新命令，存储装置延迟进入自刷新操作，直到接收到接收到自刷新命令之后接收到的控制信号。

2. 发明申请

WO2005125130A3 COMMUNICATION CHANNEL CALIBRATION USING FEEDBACK 审中-公开
标题翻译：使用反馈通信通道校准
公开(公告)号：WO2005125130A3
公开(公告)日：2006-08-10
申请号：PCT/US2005020208
申请日：2005-06-08
申请人： RAMBUS INC , KIM JUN , RICHARDSON WAYNE S , CHIU GLENN
发明人： KIM JUN , RICHARDSON WAYNE S , CHIU GLENN
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04B17/11 , H04L5/1438 , H04L25/03343 , H04L2025/03802
摘要： A method for calibrating a communication channel coupling first and second components includes transmitting a data signal from the first component (201) to the second component (202) on the communication channel (220), and sensing a characteristic (226), such as phase, of the data signal on the second component. Information about the sensed characteristic is fed back to the first component using an auxiliary channel (231). An adjustable parameter, such as phase, for the transmitter is adjusted on the first component in response to the information. Also, a characteristic of a data signal received from the transmitter on the second component is sensed and used to adjust an adjustable parameter for the receiver on the first component.
摘要翻译：用于校准耦合第一和第二组件的通信信道的方法包括：在通信信道（220）上从第一组件（201）向第二组件（202）发送数据信号，并且感测特性（226），例如相位，第二组件上的数据信号。关于感测到的特性的信息使用辅助通道（231）反馈到第一部件。响应于该信息，在第一组件上调整用于发射机的可调参数，例如相位。而且，感测从第二组件上的发射机接收到的数据信号的特性，并用于调整第一组件上的接收机的可调参数。

3. 发明申请

WO2006058200A3 MICRO-THREADED MEMORY 审中-公开
公开(公告)号：WO2006058200A3
公开(公告)日：2006-06-01
申请号：PCT/US2005/042722
申请日：2005-11-23
申请人： RAMBUS INC. , WARE, Frederick, A. , HAMPEL, Craig, E. , RICHARDSON, Wayne, S. , BELLOWS, Chad, A. , LAI, Lawrence
发明人： WARE, Frederick, A. , HAMPEL, Craig, E. , RICHARDSON, Wayne, S. , BELLOWS, Chad, A. , LAI, Lawrence
IPC分类号： G11C7/22
摘要： A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval.

4. 发明申请

WO2006058200A2 MICRO-THREADED MEMORY 审中-公开
标题翻译：微型存储器
公开(公告)号：WO2006058200A2
公开(公告)日：2006-06-01
申请号：PCT/US2005042722
申请日：2005-11-23
申请人： RAMBUS INC , WARE FREDERICK A , HAMPEL CRAIG E , RICHARDSON WAYNE S , BELLOWS CHAD A , LAI LAWRENCE
发明人： WARE FREDERICK A , HAMPEL CRAIG E , RICHARDSON WAYNE S , BELLOWS CHAD A , LAI LAWRENCE
IPC分类号： G11C7/22
CPC分类号： G06F3/0659 , G06F3/0613 , G06F3/0673 , G11C7/1006 , G11C7/1042 , G11C7/22 , G11C8/06 , G11C11/4076 , G11C11/4097
摘要： A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval.
摘要翻译：微线程存储器件。提供了多个存储体，每个存储体包括多行存储单元并且具有访问限制，因为至少最小访问时间间隔必须在对存储单元的给定行的连续访问之间发生。提供传送控制电路以响应于第一存储器访问请求在多个存储体和外部信号路径之间传送第一数据量，第一数据量小于外部信号路径带宽和最小访问时间间隔。

5. 发明申请

WO2006039106A1 MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTERGRATED CIRCUIT MEMORY DEVICE 审中-公开
标题翻译：包括集成电路存储器件的多字段寻址模式存储器系统
公开(公告)号：WO2006039106A1
公开(公告)日：2006-04-13
申请号：PCT/US2005/032770
申请日：2005-09-12
申请人： RAMBUS INC. , WARE, Frederick, A. , LAI, Lawrence , BELLOWS, Chad, A. , RICHARDSON, Wayne, S.
发明人： WARE, Frederick, A. , LAI, Lawrence , BELLOWS, Chad, A. , RICHARDSON, Wayne, S.
IPC分类号： G11C8/12 , G11C8/16
CPC分类号： G11C8/10 , G11C8/12 , G11C8/16
摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. During a third mode of operation, a first plurality of storage cells in a first row of storage cells in a first memory bank is accessible in response to a first column address. A second plurality of storage cells in a second row of storage cells in a second bank is accessible in response to a second column address. A third plurality of storage cells in the first row of storage cells is accessible in response to a third column address and a fourth plurality of storage cells in the second row of storage cells is accessible in response to a fourth column address. The first and second column addresses are in a first request packet and the third and fourth column addresses are in a second request packet provided by the master device.
摘要翻译：存储器系统包括主设备，诸如图形控制器或处理器，以及以双列寻址模式可操作的集成电路存储器件。集成电路存储器件包括一个接口和列解码器，以访问存储单元行或存储体中的页面。在第一操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元。在第二操作模式期间，响应于列周期时间间隔期间的第二列地址，可访问第一行存储单元中的第一多个存储单元。响应于列周期时间间隔期间的第三列地址，可访问第一行存储单元中的第二多个存储单元。在第三操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元中的第一多个存储单元。响应于第二列地址，可访问第二存储体中第二行存储单元中的第二多个存储单元。第一行存储单元中的第三多个存储单元响应于第三列地址而可访问，并且第二行存储单元中的第四多个存储单元响应于第四列地址而可访问。第一列地址和第二列地址在第一请求分组中，并且第三和第四列地址在由主设备提供的第二请求分组中。

6. 发明申请

WO2006023391A1 MEMORY DEVICE HAVING STAGGERED MEMORY OPERATIONS 审中-公开
标题翻译：具有存储器存储器操作的存储器件
公开(公告)号：WO2006023391A1
公开(公告)日：2006-03-02
申请号：PCT/US2005/028728
申请日：2005-08-11
申请人： RAMBUS INC. , LAI, Lawrence , RICHARDSON, Wayne, S. , BELLOWS, Chad, A.
发明人： LAI, Lawrence , RICHARDSON, Wayne, S. , BELLOWS, Chad, A.
IPC分类号： G11C7/10 , G11C7/22 , G11C8/12
CPC分类号： G11C7/1042 , G11C7/22 , G11C8/12 , G11C2207/2227
摘要： A memory system includes logical banks divided into sub-banks or collections of sub-banks. The memory system responds to memory-access requests (e.g., read and write) directed to a given logical bank by sequentially accessing sub-banks or collections of sub-banks. Sequential access reduces the impact of power-supply spikes induced by memory operations, and thus facilitates improved system performance. Some embodiments of the memory system combine sequential sub-bank access with other performance-enhancing features, such as wider power buses or increased bypass capacitance, to further enhance performance.
摘要翻译：记忆系统包括分为子银行或子银行集合的逻辑银行。存储器系统通过顺序地访问子银行或子银行集合来响应指向给定逻辑银行的存储器访问请求（例如，读取和写入）。顺序访问减少了由存储器操作引起的电源尖峰的影响，从而有助于提高系统性能。存储器系统的一些实施例将顺序的子银行访问与诸如更宽的电源总线或增加的旁路电容的其他性能增强特征相结合，以进一步提高性能。

7. 发明申请

WO2010017015A1 REQUEST-COMMAND ENCODING FOR REDUCED-DATA-RATE TESTING 审中-公开
标题翻译：要求减少数据速率测试的请求命令编码
公开(公告)号：WO2010017015A1
公开(公告)日：2010-02-11
申请号：PCT/US2009/051081
申请日：2009-07-17
申请人： RAMBUS INC. , KASAMSETTY, Kishore, Ven , RICHARDSON, Wayne, S. , KNORPP, Kurt , WARE, Frederick, A.
发明人： KASAMSETTY, Kishore, Ven , RICHARDSON, Wayne, S. , KNORPP, Kurt , WARE, Frederick, A.
IPC分类号： G11C29/16 , G11C29/18
CPC分类号： G11C29/16 , G11C29/028 , G11C29/12015 , G11C29/18 , G11C29/56012
摘要： Embodiments of a memory device are described. This memory device includes a signal connector which is electrically coupled to a command/address (CA) link, and an interface circuit, which is electrically coupled to the signal connector, and which receives CA packets via the CA link. A given CA packet includes an address field having address information corresponding to one or more storage locations in the memory device. Moreover, the memory device includes control logic having two operating modes, where, during a first operating mode, the control logic decodes address information in the CA packets using full-field sampling, and, during the second operating mode, the control logic decodes a portion of the address information in the CA packets using sub-field sampling.
摘要翻译：描述存储器件的实施例。该存储装置包括电连接到命令/地址（CA）链路的信号连接器和电耦合到信号连接器并且经由CA链路接收CA分组的接口电路。给定的CA分组包括具有与存储设备中的一个或多个存储位置相对应的地址信息的地址字段。此外，存储器件包括具有两种操作模式的控制逻辑，其中在第一操作模式期间，控制逻辑使用全场采样来解码CA分组中的地址信息，并且在第二操作模式期间，控制逻辑解码 CA分组中的部分地址信息使用子场采样。

8. 发明申请

WO2005125130A2 COMMUNICATION CHANNEL CALIBRATION USING FEEDBACK 审中-公开
标题翻译：使用反馈通信通道校准
公开(公告)号：WO2005125130A2
公开(公告)日：2005-12-29
申请号：PCT/US2005/020208
申请日：2005-06-08
申请人： RAMBUS, INC. , KIM, Jun , RICHARDSON, Wayne, S. , CHIU, Glenn
发明人： KIM, Jun , RICHARDSON, Wayne, S. , CHIU, Glenn
IPC分类号： H04L12/56
CPC分类号： H04B17/11 , H04L5/1438 , H04L25/03343 , H04L2025/03802
摘要： A method for calibrating a communication channel coupling first and second components includes transmitting a data signal from the first component to the second component on the communication channel, and sensing a characteristic, such as phase, of the data signal on the second component. Information about the sensed characteristic is fed back to the first component using an auxiliary channel. An adjustable parameter, such as phase, for the transmitter is adjusted on the first component in response to the information. Also, a characteristic of a data signal received from the transmitter on the second component is sensed and used to adjust an adjustable parameter for the receiver on the first component.
摘要翻译：用于校准耦合第一和第二组件的通信信道的方法包括在第二组件上传输数据信号从第一分量到通信信道上的第二分量，以及感测数据信号的相位等特性。关于感测到的特性的信息使用辅助信道反馈到第一分量。响应于该信息，在第一组件上调整用于发射机的可调参数，例如相位。而且，感测从第二组件上的发射机接收到的数据信号的特性，并用于调整第一组件上的接收机的可调参数。

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