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1. 发明申请

WO2004093144A3 PARTIAL RESPONSE RECEIVER 审中-公开
标题翻译：部分响应接收者
公开(公告)号：WO2004093144A3
公开(公告)日：2006-10-12
申请号：PCT/US2004010980
申请日：2004-04-09
申请人： RAMBUS INC , STOJANOVIC VLADIMIR M , HOROWITZ MARK A , ZERBE JARED L , BESSIOS ANTHONY , HO ANDREW C C , WEI JASON C , TSANG GRACE , GARLEPP BRUNO W
发明人： STOJANOVIC VLADIMIR M , HOROWITZ MARK A , ZERBE JARED L , BESSIOS ANTHONY , HO ANDREW C C , WEI JASON C , TSANG GRACE , GARLEPP BRUNO W
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159 , H04L25/06 , H04L25/497
CPC分类号： H04L25/03057 , H04L7/0276 , H04L25/063 , H04L25/497 , H04L2025/03369 , H04L2025/03503
摘要： A receive circuit for receiving a signal transmitted via an electrical signal conductor. A first sampling circuit generates a first sample value that indicates whether the signal exceeds a first threshold level, and a second sampling circuit generates a second sample value that indicates whether the signal exceeds a second threshold level. A first select circuit receives the first and second sample values from the first and second sampling circuits and selects, according to a previously generated sample value, either the first sample value or the second sample value to be output as a selected sample value.
摘要翻译：用于接收通过电信号导体发送的信号的接收电路。第一采样电路产生指示信号是否超过第一阈值电平的第一采样值，并且第二采样电路产生指示信号是否超过第二阈值电平的第二采样值。第一选择电路从第一和第二采样电路接收第一和第二采样值，并根据先前产生的采样值选择作为选择的采样值输出的第一采样值或第二采样值。

2. 发明申请

WO2005117325A2 CROSSTALK MINIMIZATION IN SERIAL LINK SYSTEMS 审中-公开
标题翻译：串行链路系统中的最小化
公开(公告)号：WO2005117325A2
公开(公告)日：2005-12-08
申请号：PCT/US2005016891
申请日：2005-05-13
申请人： RAMBUS INC , ZERBE JARED L , GARLEPP BRUNO W
发明人： ZERBE JARED L , GARLEPP BRUNO W
IPC分类号： H04L25/14 , H04L7/00
CPC分类号： H04L25/14
摘要： Described are methods and circuits for reducing the error-inducing effects of crosstalk. Communication circuits in accordance with some embodiments adjust the phase of transmitted "aggressor" data to misalign transmitted signals from the perspective of "victim" channels. This misalignment moves the noise artifacts cross coupled to the victim channel away from sensitive sample times in the victim data, and consequently reduces the net effects of aggressor crosstalk on neighboring victim channels. Some embodiments reduce the effects of crosstalk by introducing static timing offsets to one or a plurality of aggressor transmitters, one or a plurality of victim transmitters, or some combination of aggressor and victim transmitters. Other embodiments dynamically alter the relative timing of aggressor and victim transmitters.
摘要翻译：描述了用于减少串扰的误差诱导效应的方法和电路。根据一些实施例的通信电路调整发射的“侵略者”数据的相位，以从“受害者”信道的角度对发送的信号进行偏移。这种未对准使得与受害者信道交叉耦合的噪声伪影远离受害者数据中的敏感采样时间，并且因此降低了侵入者串扰对相邻受害信道的净影响。一些实施例通过向一个或多个侵略者发射机，一个或多个受害者发射机或侵略者和受害者发射机的某些组合引入静态定时偏移来减少串扰的影响。其他实施例动态地改变攻击者和受害者发射机的相对定时。

3. 发明申请

WO2004105334A3 MARGIN TEST METHODS AND CIRCUITS 审中-公开
标题翻译：测量方法和电路
公开(公告)号：WO2004105334A3
公开(公告)日：2005-06-02
申请号：PCT/US2004015895
申请日：2004-05-20
申请人： RAMBUS INC , GARLEPP BRUNO W , CHEN FRED F , HO ANDREW , STOJANOVIC VLADIMIR
发明人： GARLEPP BRUNO W , CHEN FRED F , HO ANDREW , STOJANOVIC VLADIMIR
IPC分类号： H04L1/20 , H04L1/24 , H04L25/03
CPC分类号： H04L25/03006 , H04L1/20 , H04L1/241 , H04L1/242
摘要： Described are methods and circuits for margin testing digital receivers. Some embodiments prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing, while other embodiments rely upon the statistics of sampled data to explore the margin characteristics of received data.
摘要翻译：描述了数字接收机边缘测试的方法和电路。一些实施例可以防止误差响应于错误接收的数据而崩溃，并且因此可用于采用历史数据的接收机中以减少符号间干扰（ISI）。一些实施例检测未知模式的输入数据流的接收错误，因此可以用于系统内边缘测试。这样的系统可以适于在设备操作期间动态地改变系统参数，以保持足够的余量，尽管由于例如系统噪声环境的波动。温度和电源电压变化。还描述了绘制和解释由所公开的方法和电路产生的滤波和未滤波的误差数据的方法。一些实施例对误差数据进行滤波以便于特定于图案的边缘测试，而其他实施例依赖于采样数据的统计来探索接收数据的边缘特性。

4. 发明申请

WO2008118714A3 CIRCUITS, METHODS AND SYSTEMS FOR LOSS-OF-SIGNAL DETECTION AND EQUALIZATION 审中-公开
标题翻译：信号失真检测和均衡的电路，方法和系统
公开(公告)号：WO2008118714A3
公开(公告)日：2009-02-05
申请号：PCT/US2008057497
申请日：2008-03-19
申请人： RAMBUS INC , LEIBOWITZ BRIAN S , GARLEPP BRUNO W , WERNER CARL W , CHEN FRED F
发明人： LEIBOWITZ BRIAN S , GARLEPP BRUNO W , WERNER CARL W , CHEN FRED F
IPC分类号： H04L25/03 , G01R19/165 , H04B1/16
CPC分类号： H04L25/03019 , H04L25/03057 , H04L2025/0349 , H04L2025/03694
摘要： A circuit, among other embodiments, includes a combined receiver (sampler), equalizer, adaptive engine (correlator), and LOS circuit. An equalizer circuit provides equalized input signals to the receiver circuit, which outputs data values. The LOS circuit outputs a signal that represents a LOS state when one or more equalized signals fall below an adjustable signal VOffset (or threshold sampling signal). When a LOS state is detected, the adaptation of equalization coefficients is halted until the LOS state is no longer detected, so that the equalizer coefficients will not diverge because of erroneously obtained data values during a LOS state. When a LOS state is not detected, adaptation of equalization coefficients based on received data and error values is allowed to proceed. In one embodiment, portions of the LOS circuit and the adaptive engine circuit are combined. In such an embodiment, adaptation of equalizer coefficients are adjusted based on the received data and error values while the LOS circuit is disabled and LOS status is determined when the adaptive engine is disabled. The adaptive engine is temporarily enabled after the LOS status is determined to be negative (a valid signal is present at the receiver).
摘要翻译：除了其它实施例之外，电路包括组合接收器（采样器），均衡器，自适应引擎（相关器）和LOS电路。均衡器电路向接收器电路提供均衡的输入信号，其输出数据值。当一个或多个均衡信号低于可调信号VOffset（或阈值采样信号）时，LOS电路输出表示LOS状态的信号。当检测到LOS状态时，停止对均衡系数的适应，直到不再检测到LOS状态，使得均衡器系数在LOS状态期间由于错误地获得的数据值而不会发散。当未检测到LOS状态时，允许基于接收数据和误差值的均衡系数的适应性进行。在一个实施例中，组合LOS电路和自适应发动机电路的部分。在这样的实施例中，在LOS电路被禁用的同时基于所接收的数据和误差值来调节均衡器系数的适配，并且当禁用自适应引擎时确定LOS状态。在LOS状态被确定为负值（接收机上存在有效信号）之后，自适应引擎被暂时使能。

5. 发明申请

WO0129680A9 BUS SYSTEM OPTIMIZATION 审中-公开
标题翻译：总线系统优化
公开(公告)号：WO0129680A9
公开(公告)日：2002-08-01
申请号：PCT/US0028134
申请日：2000-10-12
申请人： RAMBUS INC
发明人： ZERBE JARED LEVAN , DONNELLY KEVIN S , SIDIROPOULOS STEFANOS , STARK DONALD C , HOROWITZ MARK A , YU LEUNG , VU ROXANNE , KIM JUN , GARLEPP BRUNO W , HO TSYR-CHYANG , LAU BENEDICT CHUNG-KWONG
IPC分类号： G06F1/10 , G06F13/42
CPC分类号： G06F13/364 , G06F1/10 , G06F3/061 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F13/1689 , G06F13/1694 , G06F13/404 , G06F13/4243 , G06F13/4282 , G06F2212/7201 , G06F2212/7207 , G11C7/1045 , H04L7/0008 , H04L7/033
摘要： A bus system comprising a master (11) connected to one or more slave devices (12a-n) via a bus (30) is disclosed. The bus system is able to effectively communicate control information during a calibration phase and to individually determine appropriate timing and/or voltage offsets for each slave device (12). The offsets are used to optimize transfer timing (including duty cycle characteristics), signal equalization, and voltage levels for data exchanged between the master (11) and the slave devices (12a-n).
摘要翻译：公开了一种总线系统，包括经由总线（30）连接到一个或多个从设备（12a-n）的主站（11）。总线系统能够在校准阶段期间有效地传达控制信息，并且单独地确定每个从设备（12）的适当的定时和/或电压偏移。偏移量用于优化在主设备（11）和从设备（12a-n）之间交换的数据的传输定时（包括占空比特性），信号均衡和电压电平。

6. 发明申请

WO9837656A3 DELAY LOCKED LOOP CIRCUITRY FOR CLOCK DELAY ADJUSTMENT 审中-公开
标题翻译：延迟锁定环路电路用于时钟延迟调整
公开(公告)号：WO9837656A3
公开(公告)日：1998-11-19
申请号：PCT/US9802053
申请日：1998-02-04
申请人： RAMBUS INC
发明人： DONNELLY KEVIN S , CHAU PAK SHING , HOROWITZ MARK A , LEE THOMAS H , JOHNSON MARK G , LAU BENEDICT C , YU LEUNG , GARLEPP BRUNO W , CHAN YIU-FAI , KIM JUN , TRAN CHANH VI , STARK DONALD C
IPC分类号： G06F1/10 , G11C7/22 , H03K5/00 , H03K5/13 , H03K5/24 , H03L7/07 , H03L7/081 , H04L7/00 , H04L
CPC分类号： H03K5/133 , G06F1/10 , G11C7/22 , G11C7/222 , H03K5/2481 , H03K2005/00026 , H03K2005/00032 , H03K2005/00052 , H03K2005/00208 , H03L7/07 , H03L7/0805 , H03L7/0812 , H03L7/0814 , H04L7/0008 , H04L7/0025 , H04L7/0037
摘要： Delay locked loops (320, 350) for generating a predetermined phase relationship between a pair of clocks (300, 310). A first delay-locked loop (320) includes delay elements arranged in a chain, the chain receiving an input clock (300) and generating, from each delay element, a set of phase vectors (330), each shifted a unit delay from the adjacent vector. The first delay-locked loop (320) adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors (330) span a predetermined phase shift of the input clock (300). A second delay-locked loop (350) selects, from the first delay-locked loop (320), a pair of phase vectors which brackets the phase of an input clock (300). A phase interpolator (560) receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector (590) compares the delayed output clock with the input clock and adjusts the phase interpolator (560), based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock (410). As a result, there is a predetermined phase relationship being the amount of delay between the output clock (640) and the delayed output clock (360).

7. 发明申请

WO0150228A3 LOW LATENCY MULTI-LEVEL COMMUNICATION INTERFACE 审中-公开
标题翻译：低延迟多层通信接口
公开(公告)号：WO0150228A3
公开(公告)日：2003-12-31
申请号：PCT/US0100481
申请日：2001-01-05
申请人： RAMBUS INC
发明人： ZERBE JARED L , GARLEPP BRUNO W , CHAU PAK S , DONNELLY KEVIN S , HOROWITZ MARK A , SIDIROPOULOS STEFANOS , GARRETT BILLY W JR , WERNER CARL W
IPC分类号： H04L25/02 , G06F12/00 , G06F13/16 , G11C7/10 , G11C7/22 , G11C11/56 , H04L25/03 , H04L25/49 , H01L27/08
CPC分类号： G11C7/1057 , G11C5/063 , G11C7/10 , G11C7/1048 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C7/1072 , G11C7/1078 , G11C7/1087 , G11C7/1096 , G11C7/22 , G11C8/06 , G11C11/56 , G11C27/02 , G11C2207/108
摘要： A memory system uses multiple pulse amplitude modulation (multi-PAM) output drivers and receivers (324-1, 324-2) to send and receive multi-PAM signals (32-01, 320-2). A multi-PAM signal has more than two voltage levels, with each data interval now transmitting a "symbol" at one of the valid voltage levels. In one embodiment, a symbol represents two or more bits. The multi-PAM output driver drives an output symbol onto a signal line. The output symbol represents at least two bits that include a most significant bit (MSB) and a least significant bit (LSB). The multi-PAM receiver receives the output symbol from the signal line and determines the MSB and the LSB.
摘要翻译：存储器系统使用多个脉冲幅度调制（多PAM）输出驱动器和接收器（324-1,324-2）发送和接收多PAM信号（32-01,320-2）。多PAM信号具有两个以上的电压电平，每个数据间隔现在以有效电压电平之一发送“符号”。在一个实施例中，符号表示两个或更多位。多PAM输出驱动器将输出符号驱动到信号线上。输出符号表示包括最高有效位（MSB）和最低有效位（LSB）的至少两个位。多PAM接收器从信号线接收输出符号并确定MSB和LSB。

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