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1. 发明申请

WO2009124145A3 FRACTIONAL AND INTEGER PLL ARCHITECTURES 审中-公开
标题翻译：部分和整数PLL架构
公开(公告)号：WO2009124145A3
公开(公告)日：2010-01-07
申请号：PCT/US2009039204
申请日：2009-04-01
申请人： ATHEROS COMM INC , CHEN SHUO-WEI , SU DAVID KUOCHIEH
发明人： CHEN SHUO-WEI , SU DAVID KUOCHIEH
IPC分类号： H03L7/06
CPC分类号： H03L7/0998 , H03K3/03 , H03K5/133 , H03K2005/00032 , H03K2005/00052 , H03L7/081 , H03L7/093 , H03L7/0991 , H03L7/0995 , H03L7/183 , H03L7/1974 , H03L2207/50
摘要： A digital fractional PLL introduces an accumulated phase offset before the digital VCO using a digital accumulator to achieve the fractional part of the division ratio. To provide this phase offset, the digital accumulator can integrate a fractional component ?n. By forcing ?n to zero, the PLL becomes an integer-N PLL. A de-skew timing configuration can be used to remove any time mismatch between integer and fractional counters of the PLL. A digital PLL can merge the function of frequency generation (DVCO) and that of fractional frequency counting into the same circuit block by reusing various phases of the frequency output to generate a fractional frequency count. A digital integer PLL can include a single bit comparator, wherein the feedback loop of this PLL forces the phase difference between the reference clock signal and the feedback signal to approach zero. By changing the duty cycle of feedback signal, the frequency tracking behavior of the loop can be varied.
摘要翻译：数字分数PLL在使用数字累加器的数字VCO之前引入累积的相位偏移，以实现分数比的分数部分。为了提供这种相位偏移，数字累加器可以集成小数分量？n。通过将？n置为零，PLL变为整数N PLL。可以使用去偏移时序配置来消除PLL的整数和分数计数器之间的任何时间不匹配。数字PLL可以通过重新使用频率输出的各个相位来将频率产生（DVCO）的功能和分数频率计数的功能合并到相同的电路块中，以产生分数频率计数。数字整数PLL可以包括单比特比较器，其中该PLL的反馈环路迫使参考时钟信号和反馈信号之间的相位差接近零。通过改变反馈信号的占空比，可以改变回路的频率跟踪行为。

2. 发明申请

WO2003084067A2 SYSTEM WITH DUAL RAIL REGULATED LOCKED LOOP 审中-公开
标题翻译：具有双轨调节闭环的系统
公开(公告)号：WO2003084067A2
公开(公告)日：2003-10-09
申请号：PCT/US2003/008873
申请日：2003-03-20
申请人： RAMBUS, INC.
发明人： KIZER, Jade, M. , LAU, Benedict, C. , HAMPEL, Craig, E.
IPC分类号： H03L7/099
CPC分类号： H03L7/0805 , G06F1/10 , H03K5/135 , H03K2005/00052 , H03L7/07 , H03L7/0814

3. 发明申请

WO9837656A3 DELAY LOCKED LOOP CIRCUITRY FOR CLOCK DELAY ADJUSTMENT 审中-公开
标题翻译：延迟锁定环路电路用于时钟延迟调整
公开(公告)号：WO9837656A3
公开(公告)日：1998-11-19
申请号：PCT/US9802053
申请日：1998-02-04
申请人： RAMBUS INC
发明人： DONNELLY KEVIN S , CHAU PAK SHING , HOROWITZ MARK A , LEE THOMAS H , JOHNSON MARK G , LAU BENEDICT C , YU LEUNG , GARLEPP BRUNO W , CHAN YIU-FAI , KIM JUN , TRAN CHANH VI , STARK DONALD C
IPC分类号： G06F1/10 , G11C7/22 , H03K5/00 , H03K5/13 , H03K5/24 , H03L7/07 , H03L7/081 , H04L7/00 , H04L
CPC分类号： H03K5/133 , G06F1/10 , G11C7/22 , G11C7/222 , H03K5/2481 , H03K2005/00026 , H03K2005/00032 , H03K2005/00052 , H03K2005/00208 , H03L7/07 , H03L7/0805 , H03L7/0812 , H03L7/0814 , H04L7/0008 , H04L7/0025 , H04L7/0037
摘要： Delay locked loops (320, 350) for generating a predetermined phase relationship between a pair of clocks (300, 310). A first delay-locked loop (320) includes delay elements arranged in a chain, the chain receiving an input clock (300) and generating, from each delay element, a set of phase vectors (330), each shifted a unit delay from the adjacent vector. The first delay-locked loop (320) adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors (330) span a predetermined phase shift of the input clock (300). A second delay-locked loop (350) selects, from the first delay-locked loop (320), a pair of phase vectors which brackets the phase of an input clock (300). A phase interpolator (560) receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector (590) compares the delayed output clock with the input clock and adjusts the phase interpolator (560), based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock (410). As a result, there is a predetermined phase relationship being the amount of delay between the output clock (640) and the delayed output clock (360).

4. 发明申请

WO2015079663A1 A/D CONVERSION DEVICE WITH A MULTIPHASE CLOCK GENERATION UNIT BASED ON PHASE INTERPOLATORS 审中-公开
标题翻译：具有基于相位插值器的多相时钟发生单元的A / D转换器件
公开(公告)号：WO2015079663A1
公开(公告)日：2015-06-04
申请号：PCT/JP2014/005841
申请日：2014-11-20
申请人： SONY CORPORATION
发明人： SAEKI, Takanori , TAKAHASHI, Tomohiro , TAKEDA, Yuiti , SUZUKI, Atsushi
IPC分类号： H03M1/12 , H03K23/00 , H03K5/135 , H03M1/56
CPC分类号： H04N5/37455 , H03K5/135 , H03K23/005 , H03K2005/00052 , H03L7/08 , H03M1/12 , H03M1/123 , H03M1/56 , H04N5/378
摘要： An A/D conversion device includes a phase-difference clock generation unit configured to use a plurality of phase interpolators to generate multi-phase clock signals, of which phases are shifted with respect to an input clock signal, from the input clock signal and a signal obtained by delaying the input clock signal; and an A/D conversion unit configured to perform A/D conversion on an input analog signal using the multi-phase clock signals generated by the phase-difference clock generation unit.
摘要翻译： A / D转换装置包括相位差时钟生成单元，被配置为使用多个相位内插器从输入时钟信号产生相位相对于输入时钟信号偏移的多相时钟信号，以及通过延迟输入时钟信号获得的信号; 以及A / D转换单元，被配置为使用由相位差时钟生成单元生成的多相时钟信号对输入的模拟信号进行A / D转换。

5. 发明申请

WO2012167239A3 APPARATUS AND SYSTEMS DIGITAL PHASE INTERPOLATOR WITH IMPROVED LINEARITY 审中-公开
标题翻译：具有改进线性的装置和系统数字相位插值器
公开(公告)号：WO2012167239A3
公开(公告)日：2013-04-25
申请号：PCT/US2012040718
申请日：2012-06-04
申请人： TEXAS INSTRUMENTS INC , TEXAS INSTRUMENTS JAPAN , ERDOGAN MUSTAFA ULVI
发明人： ERDOGAN MUSTAFA ULVI
IPC分类号： H03L7/081 , H03K5/13
CPC分类号： H03K5/133 , H03K5/131 , H03K2005/00052 , H03L7/0812 , H03L7/16
摘要： An apparatus comprising: a first control switch (111) driven by a first bit value; a first weighted switch (141) driven by a first clock signal; a first intermediate node (112) coupled between the first control switch and the first weighted switch; a first pre-charge transistor (131) coupled to the first intermediate node, wherein the pre-charge transistor is driven by an inverse of the clock signal; a second control switch (121) driven by an inverse of the bit; a second weighted switch (151) driven by a second clock signal; a second intermediate node (122) coupled between the second control switch and the second weighted switch; a second pre-charge transistor (135) coupled to the second intermediate node, wherein the second pre-charge transistor (135) is driven by an inverse of the second clock signal; and a capacitor (159) coupled to the first control switch, the second control switch, the first weighted switch and the second weighted switch.
摘要翻译：一种装置，包括：由第一位值驱动的第一控制开关（111）由第一时钟信号驱动的第一加权开关（141）耦合在所述第一控制开关和所述第一加权开关之间的第一中间节点（112）耦合到所述第一中间节点的第一预充电晶体管（131），其中所述预充电晶体管由所述时钟信号的反相驱动; 由比特的倒数驱动的第二控制开关（121）由第二时钟信号驱动的第二加权开关（151）; 耦合在所述第二控制开关和所述第二加权开关之间的第二中间节点（122）耦合到所述第二中间节点的第二预充电晶体管（135），其中所述第二预充电晶体管（135）由所述第二时钟信号的反相驱动; 以及耦合到第一控制开关，第二控制开关，第一加权开关和第二加权开关的电容器（159）。

6. 发明申请

WO2012167239A2 APPARATUS AND SYSTEMS DIGITAL PHASE INTERPOLATOR WITH IMPROVED LINEARITY 审中-公开
标题翻译：具有改进线性的装置和系统数字相位插值器
公开(公告)号：WO2012167239A2
公开(公告)日：2012-12-06
申请号：PCT/US2012/040718
申请日：2012-06-04
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED , ERDOGAN, Mustafa, Ulvi
发明人： ERDOGAN, Mustafa, Ulvi
CPC分类号： H03K5/133 , H03K5/131 , H03K2005/00052 , H03L7/0812 , H03L7/16
摘要： An apparatus comprising: a first control switch (111) driven by a first bit value; a first weighted switch (141) driven by a first clock signal; a first intermediate node (112) coupled between the first control switch and the first weighted switch; a first pre-charge transistor (131) coupled to the first intermediate node, wherein the pre-charge transistor is driven by an inverse of the clock signal; a second control switch (121) driven by an inverse of the bit; a second weighted switch (151) driven by a second clock signal; a second intermediate node (122) coupled between the second control switch and the second weighted switch; a second pre-charge transistor (135) coupled to the second intermediate node, wherein the second pre-charge transistor (135) is driven by an inverse of the second clock signal; and a capacitor (159) coupled to the first control switch, the second control switch, the first weighted switch and the second weighted switch.
摘要翻译：一种装置，包括：由第一位值驱动的第一控制开关（111）由第一时钟信号驱动的第一加权开关（141）耦合在所述第一控制开关和所述第一加权开关之间的第一中间节点（112）耦合到所述第一中间节点的第一预充电晶体管（131），其中所述预充电晶体管由所述时钟信号的反相驱动; 由比特的倒数驱动的第二控制开关（121）由第二时钟信号驱动的第二加权开关（151）; 耦合在所述第二控制开关和所述第二加权开关之间的第二中间节点（122）耦合到所述第二中间节点的第二预充电晶体管（135），其中所述第二预充电晶体管（135）由所述第二时钟信号的反相驱动; 以及耦合到第一控制开关，第二控制开关，第一加权开关和第二加权开关的电容器（159）。

7. 发明申请

WO2008149981A1 変調装置及びパルス波生成装置审中-公开
标题翻译：调制装置和脉冲波生成装置
公开(公告)号：WO2008149981A1
公开(公告)日：2008-12-11
申请号：PCT/JP2008/060463
申请日：2008-06-06
申请人：日本電気株式会社 , 野瀬浩一 , 石崎晴也 , 水野正之
发明人：野瀬浩一 , 石崎晴也 , 水野正之
IPC分类号： H04L27/12
CPC分类号： H04L27/20 , H03K5/13 , H03K5/156 , H03K2005/00052 , H04L27/12
摘要：　周波数が同一であり、位相差が等しい複数のキャリア信号から、所定の制御信号にしたがって２つのキャリア信号を選択して出力する信号選択回路と、制御信号にしたがって複数のキャリア信号の位相差よりも小さい単位で位相を調整する、信号選択回路で選択されたキャリア信号に基づいて、キャリア信号の周波数または位相をベースバンド信号に応じて変調した信号である搬送波信号を生成する位相補間器とを有する。
摘要翻译：调制装置包括信号选择电路和相位内插器。信号选择电路根据预定的控制信号从具有相同频率和相同相位差的多个载波信号中选择两个载波信号并输出信号。相位内插器根据控制信号调整比载波信号的相位差小的单元。根据由信号选择电路选择的载波信号，相位内插器根据基带信号调制载波信号的频率或相位来产生载波信号。

8. 发明申请

WO00007290A1 MULTIPLE-PHASE-INTERPOLATION LC VOLTAGE-CONTROLLED OSCILLATOR 审中-公开
标题翻译：多相间插LC电压控制振荡器
公开(公告)号：WO00007290A1
公开(公告)日：2000-02-10
申请号：PCT/US1999/017357
申请日：1999-07-31
IPC分类号： H03B5/00 , H03B5/04 , H03B5/12 , H03B5/20 , H03B5/24 , H03B28/00 , H03H11/18
CPC分类号： H03B5/24 , H03B5/1209 , H03B5/1221 , H03B5/1228 , H03K2005/00052
摘要： A phase interpolation voltage controlled oscillator includes a plurality of n phase shifting cells (A) and n-1 levels of summing cells (S). The phase shifting cells (A) receive a common input signal and each shifts the input signal a different amount than the other phase shifting cells (A). A summing cell (S) of the first level receives and sums the outputs of at least two phase shifting cells (A), and each remaining level of summing cells receives outputs of a previous level of summing cells (S). The last level contains a single summing cell (S) which produces an output signal that is fed back as the common input signal of the phase shifting cells (A).
摘要翻译：相位插值压控振荡器包括多个n个相移单元（A）和n-1个求和单元（S）。相移单元（A）接收公共输入信号，并且每个移位单元将输入信号与其它相移单元（A）移动不同的量。第一级的求和单元（S）接收并加和至少两个移相单元（A）的输出，并且求和单元的每个剩余电平接收先前级别的求和单元（S）的输出。最后一级包含单个求和单元（S），其产生作为相移单元（A）的公共输入信号反馈的输出信号。

9. 发明申请

WO2016144625A1 CLOCK DISTRIBUTION SCHEMES WITH WIDE OPERATING VOLTAGE RANGES 审中-公开
标题翻译：具有宽操作电压范围的时钟分配方案
公开(公告)号：WO2016144625A1
公开(公告)日：2016-09-15
申请号：PCT/US2016/020330
申请日：2016-03-02
申请人： QUALCOMM INCORPORATED
发明人： SAMSON, Giby , PU, Yu , YUEN, Kendrick, Hoy Leong
IPC分类号： G06F1/10
CPC分类号： H03K5/135 , G06F1/10 , H03K19/0016 , H03K2005/00052
摘要： Clock distribution schemes with wide operating voltage ranges are disclosed. In one aspect, an operating voltage level or condition within a computing device is sensed. In a first voltage condition, delay elements are used within a clock tree to minimize clock skew. In a second voltage condition, one or more delay and/or clocked elements are bypassed to minimize clock skew at the second voltage condition. In addition to controlling clock skew, power may be conserved by depowering the bypassed elements. Controlling clock skew in this fashion improves operation of a computing device that includes the clock tree and may improve battery life.
摘要翻译：公开了具有宽工作电压范围的时钟分配方案。在一个方面，感测计算设备内的工作电压电平或状况。在第一电压条件下，在时钟树中使用延迟元件以最小化时钟偏移。在第二电压条件下，绕过一个或多个延迟和/或时钟元件以使在第二电压条件下的时钟偏移最小化。除了控制时钟偏移之外，通过削弱旁路元件可以节省功率。以这种方式控制时钟偏移改善了包括时钟树的计算设备的操作并且可以提高电池寿命。

10. 发明申请

WO2015191227A1 IMPROVING LINEARITY OF PHASE INTERPOLATORS USING CAPACITIVE ELEMENTS 审中-公开
标题翻译：使用电容元件改善相位插补器的线性
公开(公告)号：WO2015191227A1
公开(公告)日：2015-12-17
申请号：PCT/US2015/030884
申请日：2015-05-14
申请人： QUALCOMM INCORPORATED
发明人： SUN, Li , ZHU, Zhi , KONG, Xiaohua
IPC分类号： H04L7/00 , H03K5/1252
CPC分类号： H03K5/13 , H03K2005/00052 , H03K2005/00286 , H04L7/0025 , H04L7/02
摘要： A phase interpolator, including: a pair of load resistors coupled to a supply voltage; a plurality of branches coupled to the pair of load resistors, each branch including a differential pair of transistors connected at source terminal to form a source node; a plurality of tail current sources, each tail current source coupled to one of the source nodes; and a plurality of coupling capacitors, each coupling capacitor coupled between the source nodes in two adjacent branches of the plurality of branches.
摘要翻译：一种相位插值器，包括：耦合到电源电压的一对负载电阻; 耦合到所述一对负载电阻器的多个分支，每个分支包括在源极端子处连接以形成源节点的差分对晶体管; 多个尾流源，每个尾电流源耦合到源节点之一; 以及多个耦合电容器，每个耦合电容器耦合在所述多个分支的两个相邻分支中的源节点之间。

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