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1. 发明申请

WO2013071176A3 THREE PORT MTJ STRUCTURE AND INTEGRATION 审中-公开
标题翻译：三端口MTJ结构和集成
公开(公告)号：WO2013071176A3
公开(公告)日：2013-10-17
申请号：PCT/US2012064536
申请日：2012-11-09
申请人： QUALCOMM INC
发明人： LI XIA , ZHU XIAOCHUN , KANG SEUNG H , KIM JUNG PILL , HSU WAH NAM , KIM TAEHYUN , LEE KANGHO
IPC分类号： G11C11/16 , H01L29/82
CPC分类号： G11C11/161 , G11C8/16 , G11C11/16 , G11C11/1659 , H01L27/228 , H01L43/08
摘要： A two-transistor one-MTJ (2T1MTJ) three port structure includes two separate pin layer structures coupled to one free layer structure. The pin layer structures may include an anti-ferromagnetic layer (AFM) layer coupled to a pin layer. The free layer structure includes free layer coupled to a barrier layer and a cap layer. The free layer structure may include a thin barrier layer coupled to each of the pin layer stacks. The three port MTJ structure provides separate write and read paths which improve read sensing margin without increasing write voltage or current. The three port MTJ structure may be fabricated with a simple two step MTJ etch process.
摘要翻译：双晶体管单MTJ（2T1MTJ）三端口结构包括耦合到一个自由层结构的两个分离的引脚层结构。引脚层结构可以包括耦合到引脚层的反铁磁层（AFM）层。自由层结构包括耦合到阻挡层和帽层的自由层。自由层结构可以包括耦合到每个引脚层堆叠的薄阻挡层。三端口MTJ结构提供独立的写入和读取路径，这些路径在不增加写入电压或电流的情况下提高读取感测裕度。三端口MTJ结构可以用简单的两步MTJ刻蚀工艺制造。

2. 发明申请

WO2016118376A3 FABRICATION OF A TRANSISTOR INCLUDING A TUNNELING LAYER 审中-公开
标题翻译：包括隧道层的晶体管的制造
公开(公告)号：WO2016118376A3
公开(公告)日：2016-09-29
申请号：PCT/US2016013180
申请日：2016-01-13
申请人： QUALCOMM INC
发明人： YUAN JUN , LI XIA , YANG BIN
IPC分类号： H01L29/51 , H01L21/28 , H01L29/161 , H01L29/49 , H01L29/66 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7827 , H01L21/28079 , H01L21/28088 , H01L29/161 , H01L29/4958 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/66356 , H01L29/66666 , H01L29/66977 , H01L29/7391
摘要： In a particular embodiment, an apparatus includes an electron tunnel structure. The electron tunnel structure includes a tunneling layer, a channel layer, a source layer, and a drain layer. The tunneling layer and the channel layer are positioned between the source layer and the drain layer. The transistor device further includes a high-k dielectric layer adjacent to the electron tunnel structure.
摘要翻译：在特定实施例中，一种装置包括电子隧道结构。电子隧道结构包括隧道层，沟道层，源极层和漏极层。隧道层和沟道层位于源极层和漏极层之间。晶体管器件还包括与电子隧道结构相邻的高k电介质层。

3. 发明申请

WO2013169776A2 COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) DEVICE AND METHOD 审中-公开
标题翻译：补充金属氧化物半导体（CMOS）器件及方法
公开(公告)号：WO2013169776A2
公开(公告)日：2013-11-14
申请号：PCT/US2013039947
申请日：2013-05-07
申请人： QUALCOMM INC
发明人： YANG BIN , LI XIA , YUAN JUN
IPC分类号： H01L21/84
CPC分类号： H01L21/823814 , H01L21/28026 , H01L21/823828 , H01L21/84 , H01L27/1203 , H01L27/1211 , H01L29/1054 , H01L29/165 , H01L29/42376 , H01L29/47 , H01L29/66545 , H01L29/66621 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： A complementary metal-oxide-semiconductor (CMOS) device and methods of formation thereof are disclosed. In a particular embodiment, a CMOS device includes a silicon substrate, a dielectric insulator material on the silicon substrate, and an extension layer on the dielectric insulator material. The CMOS device further includes a gate in contact with a channel and in contact with an extension region. The CMOS device also includes a source in contact with the extension region and a drain in contact with the extension region. The extension region includes a first region in contact with the source and the gate and includes a second region in contact with the drain and the gate.
摘要翻译：公开了一种互补金属氧化物半导体（CMOS）器件及其形成方法。在特定实施例中，CMOS器件包括硅衬底，硅衬底上的介电绝缘体材料以及介电绝缘体材料上的延伸层。 CMOS器件还包括与沟道接触并与延伸区域接触的栅极。 CMOS器件还包括与延伸区域接触的源极和与延伸区域接触的漏极。延伸区域包括与源极和栅极接触的第一区域，并且包括与漏极和栅极接触的第二区域。

4. 发明申请

WO2012009524A3 MAGNETIC STORAGE ELEMENT COMPRISING A FUNCTIONAL LAYER IN THE PINNED LAYERS AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：磁性层包含功能层的磁性储存元件及其制造方法
公开(公告)号：WO2012009524A3
公开(公告)日：2012-03-08
申请号：PCT/US2011043992
申请日：2011-07-14
申请人： QUALCOMM INC , CHEN WEI-CHUAN , KANG SEUNG H , ZHU XIAOCHUN , LI XIA
发明人： CHEN WEI-CHUAN , KANG SEUNG H , ZHU XIAOCHUN , LI XIA
IPC分类号： H01L43/08 , H01L27/22
CPC分类号： H01L43/08
摘要： A magnetic tunnel junction (MTJ) storage element comprises a pinned layer stack (520) and functional layer. The pinned layer stack is formed of a plurality of layers at least one comprising a bottom pinned layer (206a, 206b), a coupling layer (208), and a top pinned layer (210a, 210b). The functional layers (540, 560) are disposed in the bottom pinned layer and/or the top pinned layer.
摘要翻译：磁性隧道结（MTJ）存储元件包括钉扎层堆叠（520）和功能层。钉扎层堆叠由多个层组成，至少一层包括底部钉扎层（206a，206b），耦合层（208）和顶部钉扎层（210a，210b）。功能层（540,560）设置在底部被钉扎层和/或顶部钉扎层中。

5. 发明申请

WO2011066324A3 MAGNETIC TUNNEL JUNCTION DEVICE AND FABRICATION 审中-公开
标题翻译：磁性隧道接头装置和制造
公开(公告)号：WO2011066324A3
公开(公告)日：2011-10-20
申请号：PCT/US2010057891
申请日：2010-11-23
申请人： QUALCOMM INC , LI XIA , KANG SEUNG H , ZHU XIAOCHUN
发明人： LI XIA , KANG SEUNG H , ZHU XIAOCHUN
IPC分类号： G11C11/15 , H01L27/22 , H01L43/12 , H04B7/005 , H04W52/12 , H04W52/26 , H04W52/34 , H04W52/44 , H04W52/54 , H04W72/12
CPC分类号： H01L43/12 , G11C11/15 , G11C11/161 , H01L21/00 , H01L27/224 , H01L43/08 , H04W52/12 , H04W52/26 , H04W52/34 , H04W52/44 , H04W52/54 , H04W72/1231 , H04W72/1247 , H04W72/1252 , H04W88/08 , H04W88/12
摘要： A magnetic tunnel junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, a method is disclosed that includes forming a magnetic tunnel junction structure (202) above a bottom electrode (110, 702). The method also includes forming a diffusion barrier layer (302, 402) above and adjacent to the magnetic tunnel junction structure. The method further includes etching back the diffusion barrier layer, removing the diffusion barrier layer above the magnetic tunnel junction structure. The method also includes connecting a top of the magnetic tunnel junction structure to a conductive layer (604, 704).
摘要翻译：公开了一种磁性隧道结（MTJ）装置及其制造方法。在特定实施例中，公开了一种方法，其包括在底部电极（110,702）上形成磁性隧道结结构（202）。该方法还包括在磁性隧道结结构上方并邻近形成扩散阻挡层（302,402）。该方法还包括蚀刻扩散阻挡层，去除在磁性隧道结结构上方的扩散阻挡层。该方法还包括将磁性隧道结结构的顶部连接到导电层（604,704）。

6. 发明申请

WO2016007254A3 NON-VOLATILE MULTIPLE TIME PROGRAMMABLE MEMORY DEVICE 审中-公开
标题翻译：非易失性多时间可编程存储器设备
公开(公告)号：WO2016007254A3
公开(公告)日：2016-03-24
申请号：PCT/US2015035271
申请日：2015-06-11
申请人： QUALCOMM INC
发明人： LI XIA , XU JEFFREY JUNHAO , LU XIAO , NOWAK MATTHEW MICHAEL , KANG SEUNG HYUK , CHEN XIAONAN , WANG ZHONGZE , LU YU
IPC分类号： H01L29/423 , G11C16/10 , G11C16/26 , H01L27/112 , H01L29/51 , H01L29/792
CPC分类号： G11C16/10 , G11C11/223 , G11C11/2259 , G11C11/2273 , G11C11/2275 , G11C16/26 , H01L27/11246 , H01L29/4234 , H01L29/513 , H01L29/517 , H01L29/7836 , H01L29/792
摘要： An apparatus includes a multiple time programmable (MTP) memory device. The MTP memory device includes a metal gate, a substrate material, and an oxide structure between the metal gate and the substrate material. The oxide structure includes a hafnium oxide layer and a silicon dioxide layer. The hafnium oxide layer is in contact with the metal gate and in contact with the silicon dioxide layer. The silicon dioxide layer is in contact with the substrate material. The MTP device includes a transistor, and a non-volatile state of the MTP memory device is based on a threshold voltage of the transistor.
摘要翻译：一种装置包括多时间可编程（MTP）存储器装置。 MTP存储器件包括金属栅极，衬底材料以及金属栅极和衬底材料之间的氧化物结构。氧化物结构包括氧化铪层和二氧化硅层。氧化铪层与金属栅极接触并与二氧化硅层接触。二氧化硅层与衬底材料接触。 MTP器件包括晶体管，并且MTP存储器件的非易失性状态基于晶体管的阈值电压。

7. 发明申请

WO2012019135A3 MRAM DEVICE AND INTEGRATION TECHNIQUES COMPATIBLE WITH LOGIC INTEGRATION 审中-公开
标题翻译： MRAM设备和集成技术兼容逻辑集成
公开(公告)号：WO2012019135A3
公开(公告)日：2012-03-29
申请号：PCT/US2011046811
申请日：2011-08-05
申请人： QUALCOMM INC , LI XIA , ZHU XIAOCHUN , KANG SEUNG H
发明人： LI XIA , ZHU XIAOCHUN , KANG SEUNG H
IPC分类号： H01L27/22 , B82Y25/00 , H01L43/08 , H01L43/12
CPC分类号： H01L43/12 , B82Y10/00 , G11C11/161 , H01L27/228 , H01L43/08
摘要： A semiconductor device includes a magnetic tunnel junction (MTJ) storage element configured to be disposed in a common interlayer metal dielectric (IMD) layer with a logic element. Cap layers separate the common IMD layer from a top and bottom IMD layer. Top and bottom electrodes are coupled to the MTJ storage element. Metal connections to the electrodes are formed in the top and bottom IMD layers respectively through vias in the separating cap layers. Alternatively, the separating cap layers are recessed and the bottom electrodes are embedded, such that direct contact to metal connections in the bottom IMD layer is established. Metal connections to the top electrode in the common IMD layer are enabled by isolating the metal connections from the MTJ storage elements with metal islands and isolating caps.
摘要翻译：一种半导体器件包括被配置为设置在具有逻辑元件的公共层间金属电介质（IMD）层中的磁性隧道结（MTJ）存储元件。盖层将普通IMD层与顶部和底部IMD层分开。顶部和底部电极连接到MTJ存储元件。与电极的金属连接分别通过分离帽层中的通孔形成在顶部和底部IMD层中。可选地，分离盖层凹入并且底部电极被嵌入，从而建立与底部IMD层中的金属连接的直接接触。通过将金属连接与MTJ存储元件与金属岛和隔离帽隔离，可以实现与公共IMD层中的顶部电极的金属连接。

8. 发明申请

WO2010120918A3 MAGNETIC TUNNEL JUNCTION (MTJ) AND METHODS, AND MAGNETIC RANDOM ACCESS MEMORY (MRAM) EMPLOYING SAME 审中-公开
标题翻译：磁性隧道结（MTJ）和方法以及使用其的磁性随机存取存储器（MRAM）
公开(公告)号：WO2010120918A3
公开(公告)日：2011-01-20
申请号：PCT/US2010031080
申请日：2010-04-14
申请人： QUALCOMM INC , ZHU XIAOCHUN , NOWAK MATTHEW , LI XIA , KANG SEUNG H
发明人： ZHU XIAOCHUN , NOWAK MATTHEW , LI XIA , KANG SEUNG H
IPC分类号： H01L27/115 , G11B5/39 , G11C11/15
CPC分类号： H01L43/02 , G11C11/16 , G11C11/161 , G11C11/1659 , H01F10/3254 , H01F10/3272 , H01L27/228 , H01L43/08 , H01L43/12
摘要： Magnetic tunnel junctions (MTJs) and methods of forming same are disclosed. A pinned layer is disposed in the MTJ such that a free layer of the MTJ can couple to a drain of an access transistor when provided in a magnetic random access memory (MRAM) bitcell. This structure alters the write current flow direction to align the write current characteristics of the MTJ with write current supply capability of an MRAM bitcell employing the MTJ. As a result, more write current can be provided to switch the MTJ from a parallel (P) to anti-parallel (AP) state. An anti-ferromagnetic material (AFM) layer is provided on the pinned layer to fix pinned layer magnetization. To provide enough area for depositing the AFM layer to secure pinned layer magnetization, a pinned layer having a pinned layer surface area greater than a free layer surface area of the free layer is provided.
摘要翻译：公开了磁隧道结（MTJ）及其形成方法。被钉扎层设置在MTJ中，使得当提供在磁随机存取存储器（MRAM）位单元中时，MTJ的自由层可以耦合到存取晶体管的漏极。该结构改变写入电流流动方向，以使MTJ的写入电流特性与使用MTJ的MRAM位单元的写入电流供应能力对准。结果，可以提供更多的写入电流以将MTJ从并行（P）切换到反并行（AP）状态。在钉扎层上提供反铁磁材料（AFM）层以固定钉扎层的磁化强度。为了提供足够的用于沉积AFM层以确保钉扎层磁化的区域，提供了具有大于自由层的自由层表面积的钉扎层表面积的钉扎层。

9. 发明申请

WO2010118302A2 DIAMOND TYPE QUAD-RESISTOR CELLS OF PRAM 审中-公开
标题翻译：金刚石型四电极四电极片
公开(公告)号：WO2010118302A2
公开(公告)日：2010-10-14
申请号：PCT/US2010030510
申请日：2010-04-09
申请人： QUALCOMM INC , LI XIA
发明人： LI XIA
IPC分类号： G11C16/02 , H01L27/24 , H01L45/00
CPC分类号： H01L45/06 , G11C13/0004 , G11C13/0069 , G11C2013/008 , G11C2213/52 , H01L27/2463 , H01L27/2472 , H01L45/122 , H01L45/126 , H01L45/144 , H01L45/1608 , H01L45/1675
摘要： A method of forming a phase-change random access memory (PRAM) cell, and a structure of a phase-change random access memory (PRAM) cell are disclosed. The PRAM cell includes a bottom electrode, a heater resistor coupled to the bottom electrode, a phase change material (PCM) formed over and coupled to the heater resistor, and a top electrode coupled to the phase change material. The phase change material contacts a portion of a vertical surface of the heater resistor and a portion of a horizontal surface of the heater resistor to form an active region between the heater resistor and the phase change material.
摘要翻译：公开了一种形成相变随机存取存储器（PRAM）单元的方法以及相变随机存取存储器（PRAM）单元的结构。 PRAM单元包括底部电极，耦合到底部电极的加热器电阻器，在加热器电阻器上形成并耦合到加热器电阻器的相变材料（PCM），以及耦合到相变材料的顶部电极。相变材料接触加热器电阻器的垂直表面的一部分和加热器电阻器的水平表面的一部分，以在加热器电阻器和相变材料之间形成有源区。

10. 发明申请

WO2014004770A3 INTEGRATED CIRCUIT DEVICE FEATURING AN ANTIFUSE AND METHOD OF MAKING SAME 审中-公开
标题翻译：集成电路设备，具有抗病毒及其制造方法
公开(公告)号：WO2014004770A3
公开(公告)日：2014-03-27
申请号：PCT/US2013048088
申请日：2013-06-27
申请人： QUALCOMM INC
发明人： WANG ZHONGZE , ZHU JOHN JIANHONG , LI XIA
IPC分类号： H01L27/112 , G11C17/16 , H01L23/522 , H01L23/525 , H01L49/02
CPC分类号： H01L27/11206 , G11C17/16 , G11C17/165 , H01L21/8239 , H01L23/5228 , H01L23/5252 , H01L27/1052 , H01L27/11286 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit, e.g. an OTP or MTP memory circuit, comprises an access transistor (10) and an antifuse (102). The access transistor includes at least one source/drain region (106, 08), and the antifuse has a conductor-insulator-conductor structure. The antifuse includes a first conductor that acts as a first electrode (134), and also includes an antifuse dielectric (136), and a second conductor (114, 304). A first surface of the first electrode is coupled to a first surface of the antifuse dielectric, a second surface of the antifuse dielectric is coupled to a first surface of the second conductor. The second conductor is electrically coupled to the access transistor's source/ drain region. The antifuse is adapted to transition from an open circuit state to a closed circuit state if a programming voltage Vpp greater than or equal to an antifuse dielectric breakdown voltage is applied between the first electrode and the second conductor. A resistor (202) can also be provided and is formed from the same layer as the first electrode (134) of the antifuse. The resistor is located on an insulating layer (204) that is made from the same layer as the antifuse dielectric,
摘要翻译：集成电路，例如 OTP或MTP存储器电路，包括存取晶体管（10）和反熔丝（102）。存取晶体管包括至少一个源极/漏极区域（106,08），并且反熔丝具有导体 - 绝缘体 - 导体结构。反熔丝包括用作第一电极（134）的第一导体，并且还包括反熔丝电介质（136）和第二导体（114,304）。第一电极的第一表面耦合到反熔丝电介质的第一表面，反熔丝电介质的第二表面耦合到第二导体的第一表面。第二导体电耦合到存取晶体管的源/漏区。如果在第一电极和第二导体之间施加大于或等于抗熔丝电介质击穿电压的编程电压Vpp，则反熔丝适于从开路状态转变到闭合电路状态。还可以提供电阻器（202）并且由与反熔丝的第一电极（134）相同的层形成。电阻器位于由与反熔丝电介质相同的层制成的绝缘层（204）上，

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