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1. 发明申请

WO2016074176A1 FLEXIBLE SYSTEM-IN-PACKAGE SOLUTIONS FOR WEARABLE DEVICES 审中-公开
标题翻译：用于可穿戴设备的灵活的系统级封装解决方案
公开(公告)号：WO2016074176A1
公开(公告)日：2016-05-19
申请号：PCT/CN2014/090939
申请日：2014-11-12
申请人： INTEL CORPORATION , TANG, Jiamiao , ZHAO, Junfeng , SKINNER, Michael P. , SHE, Yong , SIR, Jiun Hann , CHEAH, Bok Eng , PERIAMAN, Shanggar , OOI, Kooi Chi , CHEW, Yen Hsiang
发明人： TANG, Jiamiao , ZHAO, Junfeng , SKINNER, Michael P. , SHE, Yong , SIR, Jiun Hann , CHEAH, Bok Eng , PERIAMAN, Shanggar , OOI, Kooi Chi , CHEW, Yen Hsiang
IPC分类号： H01L23/28
CPC分类号： G06F1/163 , A41B1/00 , A41D1/06 , A41D1/08 , A41F9/002 , A43B3/001 , A43B3/0015 , A43B7/141 , A44C5/0015 , A44C15/005 , F03G5/06 , G06F1/189 , H01L21/4853 , H01L21/565 , H01L23/3135 , H01L23/49838 , H01L23/4985 , H01L23/562 , H01L25/0655 , H01L25/50 , H01L2224/16225 , H01L2224/48091 , H01L2224/73257 , H01L2924/0002 , H01L2924/181 , H02J1/14 , H05K1/189 , H05K2201/05 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： Embodiments of the present disclosure are directed towards an integrated circuit (IC) package. In embodiments, an integrated circuit (IC) package may include a flexible substrate (102). The flexible substrate (102) may have a plurality of dies (104 -112) coupled therewith. The IC package may include a first encapsulation material (116-120), having a first rigidity, disposed on the flexible substrate (102) to at least partially encapsulate each die of the plurality dies (104 -112). The IC package may further include a second encapsulation material (122), having a second rigidity, disposed on the flexible substrate (102). In embodiments, the second rigidity and the first rigidity are different from one another. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例涉及集成电路（IC）封装。在实施例中，集成电路（IC）封装可以包括柔性基板（102）。柔性基板（102）可以具有与其连接的多个管芯（104-112）。 IC封装可以包括具有第一刚性的第一封装材料（116-120），其设置在柔性基板（102）上以至少部分地封装多个管芯（104-112）中的每个管芯。 IC封装还可以包括设置在柔性基板（102）上的具有第二刚性的第二封装材料（122）。在实施例中，第二刚性和第一刚度彼此不同。可以描述和/或要求保护其他实施例。

2. 发明申请

WO2014003533A1 MULTI-DIE SEMICONDUCTOR STRUCTURE WITH INTERMEDIATE VERTICAL SIDE CHIP AND SEMICONDUCTOR PACKAGE FOR SAME 审中-公开
标题翻译：具有中间垂直侧芯片和半导体封装的多芯半导体结构
公开(公告)号：WO2014003533A1
公开(公告)日：2014-01-03
申请号：PCT/MY2012/000191
申请日：2012-06-25
申请人： INTEL CORPORATION , CHEAH, Bok Eng , PERIAMAN, Shanggar , OOI, Kooi Chi , KONG, Jackson Chung Peng
发明人： CHEAH, Bok Eng , PERIAMAN, Shanggar , OOI, Kooi Chi , KONG, Jackson Chung Peng
IPC分类号： H01L23/48 , H01L23/12
CPC分类号： H01L25/0652 , H01L23/3128 , H01L23/3142 , H01L23/481 , H01L23/5386 , H01L23/5389 , H01L24/02 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/73 , H01L24/80 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/02371 , H01L2224/02372 , H01L2224/0401 , H01L2224/0557 , H01L2224/06181 , H01L2224/06182 , H01L2224/06183 , H01L2224/06189 , H01L2224/06517 , H01L2224/131 , H01L2224/16137 , H01L2224/16145 , H01L2224/16225 , H01L2224/1703 , H01L2224/17181 , H01L2224/17183 , H01L2224/32225 , H01L2224/73204 , H01L2224/80894 , H01L2224/81815 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2225/06555 , H01L2225/06562 , H01L2225/06565 , H01L2924/00014 , H01L2924/10253 , H01L2924/12042 , H01L2924/1432 , H01L2924/1434 , H01L2924/1461 , H01L2924/15311 , H01L2924/15787 , H01L2924/18161 , H01L2924/351 , H01L2924/00012 , H01L2224/80 , H01L2924/014 , H01L2924/00 , H01L2224/05552
摘要： Semiconductor multi-die structures having intermediate vertical side chips, and packages housing such semiconductor multi-die structures, are described. In an example, a multi-die semiconductor structure includes a first main stacked dies (MSD) structure having a first substantially horizontal arrangement of semiconductor dies. A second MSD structure having a second substantially horizontal arrangement of semiconductor dies is also included. An intermediate vertical side chip (i-VSC) is disposed between and electrically coupled to the first and second MSD structures.
摘要翻译：描述了具有中间垂直侧芯片的半导体多管芯结构以及容纳这种半导体多管芯结构的封装。在一个示例中，多管芯半导体结构包括具有半导体管芯的第一基本水平布置的第一主堆叠管芯（MSD）结构。还包括具有半导体管芯的第二基本水平布置的第二MSD结构。中间垂直侧芯片（i-VSC）设置在电耦合到第一和第二MSD结构之间。

3. 发明申请

WO2012174449A2 MICROELECTRONIC DEVICE, STACKED DIE PACKAGE AND COMPUTING SYSTEM CONTAINING SAME, METHOD OF MANUFACTURING A MULTI¬ CHANNEL COMMUNICATION PATHWAY IN SAME, AND METHOD OF ENABLING ELECTRICAL COMMUNICATION BETWEEN COMPONENTS OF A STACKED-DIE PACKAGE 审中-公开
标题翻译：微电子装置，堆叠式包装和包含其的计算系统，制造其中的多通道通信路径的方法以及在堆叠式包装的组件之间实现电气通信的方法
公开(公告)号：WO2012174449A2
公开(公告)日：2012-12-20
申请号：PCT/US2012/042774
申请日：2012-06-15
申请人： INTEL CORPORATION , CHEAH, Bok Eng , PERIAMAN, Shanggar , OOI, Kooi Chi
发明人： CHEAH, Bok Eng , PERIAMAN, Shanggar
IPC分类号： H01L23/538 , H01L23/48
CPC分类号： H01L21/76898 , H01L23/31 , H01L23/481 , H01L24/16 , H01L25/0657 , H01L2224/02125 , H01L2224/0401 , H01L2224/13025 , H01L2224/131 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/17181 , H01L2224/73204 , H01L2225/06513 , H01L2225/06517 , H01L2225/06544 , H01L2924/01327 , H01L2924/12042 , H01L2924/15311 , H01L2924/014 , H01L2924/00 , H01L2924/00012
摘要： A microelectronic device comprises a first surface (110, 710), a second surface (120, 720), and a passageway (130, 730) extending from the first surface to the second surface. The passageway contains a plurality of electrically conductive channels (131, 132, 231, 232) separated from each other by an electrically insulating material (133, 1 133).
摘要翻译：微电子器件包括第一表面（110,710），第二表面（120,720）和从第一表面延伸到第二表面的通道（130,730）。通道包含通过电绝缘材料（133,1133）彼此分离的多个导电通道（131,132,231,232）。

4. 发明申请

WO2018063327A1 OVERPASS DICE STACKS AND METHODS OF USING SAME 审中-公开
标题翻译： OVERPASS DICE堆栈及使用它的方法
公开(公告)号：WO2018063327A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054785
申请日：2016-09-30
申请人： INTEL CORPORATION , CHEAH, Bok Eng , LIM, Min Suet , KONG, Jackson Chung Peng
发明人： CHEAH, Bok Eng , LIM, Min Suet , KONG, Jackson Chung Peng
IPC分类号： H01L23/00 , H01L23/48 , H01L25/065
摘要： A system in package device includes an overpass die on a package substrate and the overpass die includes a recess on the back side in order to straddle a landed die also on the package substrate. The recess is bounded by at least two overpass walls. Communication between the dice is done with a through-silicon via and communication between the overpass die and the package substrate is also done with a through-silicon via.
摘要翻译：封装装置中的系统包括位于封装衬底上的跨接裸片，并且跨接裸片包括背侧上的凹槽，以便也跨越位于封装衬底上的着陆裸片。该凹处由至少两个立交桥壁围绕。芯片之间的通信是通过硅通孔完成的，并且通过硅通孔也可以实现跨接芯片和封装衬底之间的通信。

5. 发明申请

WO2018063380A1 MULTIPLE-LAYER, SELF-EQUALIZING INTERCONNECTS IN PACKAGE SUBSTRATES 审中-公开
标题翻译：封装基板中的多层自平衡互连
公开(公告)号：WO2018063380A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054939
申请日：2016-09-30
申请人： INTEL CORPORATION , HALL, Stephen H. , CHEAH, Bok Eng , SREERAMA, Chaitanya , KONG, Jackson Chung Peng
发明人： HALL, Stephen H. , CHEAH, Bok Eng , SREERAMA, Chaitanya , KONG, Jackson Chung Peng
IPC分类号： H01L23/00 , H01L23/12
CPC分类号： H01L23/49822 , H01L21/4857 , H01L23/498 , H01L23/49811 , H01L23/49866 , H01L23/66
摘要： A self-equalizing interconnect in a connector is installed in a microelectronic device. The self-equalizing interconnect is formed of a plurality of electrically conductive layers under conditions to offset skin-effect losses with respect to frequency change during operation. Each successive layer is configured to with the next highest electrical conductivity and subsequent electrically conductive films gradually decrease in electrical conductivity. In an embodiment, thickness of the conductive film adjacent the reference plain is configured thinnest and subsequent films are added and are seriatim gradually thicker. The highest electrically conductive film is configured closest to a reference plane in the connector, and the lowest electrically conductive film is farthest from the reference plane.
摘要翻译：
连接器中的自动均衡互连器安装在微电子器件中。自动均衡互连由多个导电层形成，以在运行期间抵消与频率变化相关的趋肤效应损失。每个连续的层被配置为具有次高的导电率，随后的导电膜的电导率逐渐降低。在一个实施例中，邻近参考平面的导电膜的厚度被构造得最薄并且随后的膜被添加并且逐渐地逐渐变厚。最高导电膜被配置为最接近连接器中的参考平面，并且最低导电膜离基准平面最远。

6. 发明申请

WO2018063154A1 3D STACKED-IN-RECESS SYSTEM IN PACKAGE 审中-公开
标题翻译：包装中的3D堆叠入库系统
公开(公告)号：WO2018063154A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/053935
申请日：2016-09-27
申请人： INTEL CORPORATION , CHEAH, Bok Eng , LIM, Min Suet , KONG, Jackson Chung Peng , LOO, Howe Yin
发明人： CHEAH, Bok Eng , LIM, Min Suet , KONG, Jackson Chung Peng , LOO, Howe Yin
IPC分类号： H01L25/065 , H01L23/538 , H01L23/48 , H01L21/48 , H01L23/00
CPC分类号： H01L21/48 , H01L23/00 , H01L23/48 , H01L23/538 , H01L23/552 , H01L25/0652 , H01L25/0655 , H01L25/18 , H01L25/50 , H01L29/0657 , H01L2224/13025 , H01L2224/16146 , H01L2224/16225 , H01L2224/16235 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/1432 , H01L2924/1434 , H01L2924/15192 , H01L2924/15311 , H01L2924/3025
摘要： A system in package device includes a landed first die disposed on a package substrate. The landed first die includes a notch that is contoured and that opens the backside surface of the die to a ledge. A stacked die is mounted at the ledge and the two dice are each contacted by a through-silicon via (TSV). The system in package device also includes a landed subsequent die on the package substrate and a contoured notch in the landed subsequent die and the notch in the first die form a composite contoured recess into which the stacked die is seated.
摘要翻译：封装装置中的系统包括设置在封装衬底上的落地第一管芯。落地的第一模具包括具有轮廓的凹口并且将模具的背面表面打开成凸缘。堆叠式芯片安装在壁架上，并且两个芯片分别与硅通孔（TSV）接触。封装装置中的系统还包括位于封装衬底上的落地后续裸片，落地后续裸片中的轮廓凹槽和第一裸片中的凹槽形成组合轮廓凹槽，堆叠裸片位于该凹槽中。

7. 发明申请

WO2017112035A1 THROUGH-HOLE INTERCONNECT NETWORK AND METHOD OF MAKING SAME 审中-公开
标题翻译：通孔互连网络及其制造方法
公开(公告)号：WO2017112035A1
公开(公告)日：2017-06-29
申请号：PCT/US2016/056641
申请日：2016-10-12
申请人： INTEL CORPORATION , TAN, Boon Keat , ONG, Andrew Soon Aun , KONG, Jackson Chung Peng , CHEAH, Bok Eng , LI, Jingbo
发明人： TAN, Boon Keat , ONG, Andrew Soon Aun , KONG, Jackson Chung Peng , CHEAH, Bok Eng , LI, Jingbo
IPC分类号： H01L23/498 , H01L21/48 , H01L23/48 , H01L21/768
CPC分类号： H01L21/48 , H01L21/768 , H01L23/48 , H01L23/498 , H01L23/49827 , H01L23/49838
摘要： Techniques and mechanisms for providing connectivity between traces disposed on opposite sides of a substrate such as that of a printed circuit board. In an embodiment, through-hole interconnects (TIs) each extend from a first side of a substrate to a second side of the substrate. A first node and a second node are disposed at the first side and at the second side, respectively. Each of the plurality of TIs is coupled to propagate a respective portion of a signal between the first node and the second node. In another embodiment, a material of the substrate, disposed between two of the TIs, provides for a capacitance that improves signal characteristics.
摘要翻译：用于提供设置在诸如印刷电路板的衬底的相对侧上的迹线之间的连接性的技术和机制。在一个实施例中，通孔互连（TI）均从衬底的第一侧延伸到衬底的第二侧。第一节点和第二节点分别设置在第一侧和第二侧。多个TI中的每一个被耦合以传播第一节点和第二节点之间的信号的相应部分。在另一个实施例中，设置在两个TI之间的衬底材料提供改善信号特性的电容。

8. 发明申请

WO2017099784A1 FLEXIBLE COMPUTING DEVICE THAT INCLUDES A PLURALITY OF DISPLAYS 审中-公开
标题翻译：灵活的计算设备，包括多个显示器
公开(公告)号：WO2017099784A1
公开(公告)日：2017-06-15
申请号：PCT/US2015/065080
申请日：2015-12-10
申请人： INTEL CORPORATION
发明人： KONG, Jackson Chung Peng , OOI, Kooi Chi , CHEAH, Bok Eng , GOH, Eng Huat
IPC分类号： G06F1/16 , G09F9/30
CPC分类号： G06F1/1652 , G06F1/163
摘要： A flexible electronic device that includes a flexible substrate having an upper surface and a lower surface and interconnects extending between the upper surface and the lower surface; a flexible display mounted directly to the upper surface of the flexible substrate such that the flexible display is electrically connected to the flexible substrate; a first encapsulant mounted to the upper surface of the flexible substrate such that the flexible display is at least partially embedded within the first encapsulant; an electronic component mounted to a lower surface of the flexible substrate such that the electronic component is electrically connected to the flexible substrate; a second encapsulant mounted to the lower surface of the flexible substrate such that the electronic component is at least partially embedded within the second encapsulant; a flexible casing that surrounds the electronic component and the second encapsulant.
摘要翻译：一种柔性电子装置，其包括具有上表面和下表面的柔性基板以及在所述上表面和所述下表面之间延伸的互连; 直接安装到所述柔性基板的上表面的柔性显示器，使得所述柔性显示器电连接到所述柔性基板; 第一密封剂，其安装到所述柔性衬底的上表面，使得所述柔性显示器至少部分地嵌入所述第一密封剂内; 电子部件，所述电子部件安装到所述柔性基板的下表面，使得所述电子部件电连接到所述柔性基板; 第二密封剂，所述第二密封剂安装到所述柔性基板的所述下表面，使得所述电子组件至少部分地嵌入所述第二密封剂内; 包围电子元件和第二密封剂的柔性外壳。

9. 发明申请

WO2017044246A1 MULTI-ORIENTATION DISPLAY DEVICE 审中-公开
标题翻译：多方位显示装置
公开(公告)号：WO2017044246A1
公开(公告)日：2017-03-16
申请号：PCT/US2016/046654
申请日：2016-08-12
申请人： INTEL CORPORATION
发明人： YEE, Chee Chun , BROWNING, David W. , CHEAH, Bok Eng , KONG, Jackson Chung Peng , LIM, Min Suet , LOO, Howe Yin , OH, Poh Tat
IPC分类号： G06F1/16 , H04M1/02
CPC分类号： G06F1/1652 , G06F1/1626 , G06F1/1641 , G06F1/1643 , G06F1/1675 , G06F3/041 , G06F2203/04102
摘要： A computing device includes a flexible display screen, a housing to house at least one processor device and at least one memory element, and a first wing to support a side portion of the display screen. The front face of the housing includes a center portion of the display screen. The first wing is connected to the housing by a hinge, the first wing configured to swivel about an axis defined by the hinge. The hinge is configured to lock the first wing in at least two wing positions, a first of the wing positions supports the side portion of the display screen in a first orientation, a second of the wing positions supports the side portion of the display screen in a second orientation, and the side portion of the display screen is active in the first orientation and hidden in the second orientation.
摘要翻译：计算设备包括柔性显示屏，用于容纳至少一个处理器设备和至少一个存储器元件的外壳，以及支撑显示屏幕的侧部的第一翼。壳体的前表面包括显示屏的中心部分。第一翼通过铰链连接到壳体，第一翼构造成围绕由铰链限定的轴线旋转。所述铰链被构造成将所述第一翼片锁定在至少两个翼位置中，所述机翼位置中的第一翼位置以第一方向支撑所述显示屏幕的侧部，所述机翼位置中的第二翼支撑所述显示屏幕的侧部第二取向，并且显示屏幕的侧部在第一取向中是有效的，并且在第二取向中被隐藏。

10. 发明申请

WO2016094024A1 VERTICAL TRENCH ROUTING IN A SUBSTRATE 审中-公开
标题翻译：在基板上垂直倾斜路由
公开(公告)号：WO2016094024A1
公开(公告)日：2016-06-16
申请号：PCT/US2015/060444
申请日：2015-11-12
申请人： INTEL CORPORATION
发明人： KONG, Jackson , CHEAH, Bok Eng , YONG, Khang Choong , HECK, Howard L. , CHEN, Kuan-Yu
IPC分类号： H05K1/02 , H05K3/00
CPC分类号： H01L21/486 , H01L21/4846 , H01L21/4857 , H01L23/49822 , H01L23/49827 , H01L24/10 , H01P3/003 , H01P3/026 , H01P3/04 , H01P3/08 , H01P3/082 , H01P5/028 , H05K1/0224 , H05K1/0242 , H05K1/0245 , H05K2201/0376
摘要： An interconnect topology that includes vertical trench routing in a substrate is disclosed. In one embodiment, the interconnect comprises a substrate having a plurality of layers including a first ground plane layer; a pair of signal conductors that form a differential signal pair, each conductor of the pair of signal conductors having a first portion and a second portion, the second portion extending from the first portion into at least one of the plurality of layers, wherein width of the second portion is less than width of the first portion; and wherein the first ground plane layer is only a first partial layer and has a first void region that is closer to the pair of signal conductors than the first partial layer.
摘要翻译：公开了一种在衬底中包括垂直沟槽布线的互连拓扑。在一个实施例中，互连包括具有包括第一接地平面层的多个层的衬底; 形成差分信号对的一对信号导体，所述一对信号导体中的每个导体具有第一部分和第二部分，所述第二部分从所述第一部分延伸到所述多个层中的至少一个层中，其中，第二部分小于第一部分的宽度; 并且其中所述第一接地层仅为第一部分层，并且具有比所述第一部分层更靠近所述一对信号导体的第一空隙区域。

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