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    • 4. 发明申请
    • THREE CAPACITOR STACK AND ASSOCIATED METHODS
    • 三个电容堆叠和相关方法
    • WO2018063632A1
    • 2018-04-05
    • PCT/US2017/048824
    • 2017-08-28
    • INTEL CORPORATION
    • GOH, Eng HuatSIR, Jiun HannCHUA, Han KungLIM, Min SuetTEOH, Hoay Tien
    • H01G4/38H01G4/30
    • H01L28/75
    • A three capacitor stack and associated methods are shown. An exemplary capacitor device may include a first capacitor stack that includes a first plurality of layers of reference electrodes interleaved with first capacitor electrodes, a second capacitor stack on the first capacitor stack that includes a second plurality of layers of reference electrodes interleaved with second capacitor electrodes, and a third capacitor stack on the second capacitor stack that includes a reference electrode and a third capacitor electrode. A respective layer of dielectric material is formed between the reference electrodes and the first capacitor electrodes, the second capacitor electrodes, and the third capacitor electrode.
    • 显示了三个电容器堆叠和相关的方法。 示例性电容器装置可以包括:第一电容器叠层,其包括与第一电容器电极交错的第一多个参考电极层;第一电容器叠层上的第二电容器叠层,其包括与第二电容器电极交错的第二多个参考电极层 以及在第二电容器堆叠上的第三电容器堆叠,其包括参考电极和第三电容器电极。 在参考电极和第一电容器电极,第二电容器电极和第三电容器电极之间形成相应的介电材料层。
    • 5. 发明申请
    • ELECTRONIC DEVICE PACKAGE ON PACKAGE (POP)
    • 电子设备包装(POP)
    • WO2018009168A1
    • 2018-01-11
    • PCT/US2016/040908
    • 2016-07-02
    • INTEL CORPORATION
    • GOH, Eng HuatSIR, Jiun HannLIM, Min SuetGUO, Xi
    • H01L25/10H01L25/18H01L23/367
    • Electronic device package on package (POP) technology is disclosed. A POP can comprise a first electronic device package including a heat source. The POP can also comprise a second electronic device package disposed on the first electronic device package. The second electronic device package can include a substrate having a heat transfer portion proximate the heat source that facilitates heat transfer from the heat source through a thickness of the substrate. The substrate can also have an electronic component portion at least partially about the heat transfer portion that facilitates electrical communication. In addition, the POP can comprise an electronic component operably coupled to the electronic component portion.
    • 公开了电子装置封装(POP)技术。 POP可以包括包含热源的第一电子设备包。 POP还可以包括设置在第一电子设备包上的第二电子设备包。 第二电子器件封装可以包括具有靠近热源的传热部分的基板,其有助于从热源通过基板厚度的热传递。 衬底还可以具有电子组件部分,该电子组件部分至少部分地围绕促进电通信的传热部分。 另外,POP可以包括可操作地耦合到电子组件部分的电子组件。
    • 6. 发明申请
    • CAPACITIVE INTERCONNECT IN A SEMICONDUCTOR PACKAGE
    • 半导体封装中的容性互连
    • WO2017218135A1
    • 2017-12-21
    • PCT/US2017/033340
    • 2017-05-18
    • INTEL CORPORATION
    • GOH, Eng HuatLIM, Min SuetTAN, Fern NeeYONG, Khang ChoongSIR, Jiun Hann
    • H01L23/495H01L23/498H01L23/00H01L25/07H01L49/02
    • Capacitive interconnects and processes for fabricating the capacitive interconnects are provided. In some embodiments, the capacitive interconnect includes first metal layers, second metal layers; and dielectric layers including a dielectric layer that intercalates a first metal layer of the first metal layers and a second metal layer of the second metal layers. Such layers can be assembled in a nearly concentric arrangement, where the dielectric layer abuts the first metal layer and the second metal layer abuts the dielectric layer. In addition, the capacitive interconnect can include a first electrode electrically coupled to at least one of the first metal layers, and a second electrode electrically coupled to at least one of the second metal layers, the second electrode assembled opposite to the first electrode. The first electrode and the second electrode can include respective solder tops.
    • 提供用于制造电容互连的电容互连和工艺。 在一些实施例中,电容性互连件包括第一金属层,第二金属层; 以及介电层,其包括插入第一金属层的第一金属层和第二金属层的第二金属层的介电层。 这些层可以以几乎同心的结构组装,其中电介质层邻接第一金属层并且第二金属层邻接电介质层。 另外,电容性互连可以包括电耦合到第一金属层中的至少一个的第一电极和电耦合到第二金属层中的至少一个的第二电极,第二电极与第一电极相对组装。 第一电极和第二电极可以包括各自的焊料顶部。
    • 9. 发明申请
    • SYSTEMS, METHODS, AND APPARATUSES FOR IMPLEMENTING A PAD ON SOLDER MASK (POSM) SEMICONDUCTOR SUBSTRATE PACKAGE
    • 用于在焊料掩模(POSM)半导体衬底封装上实施焊盘的系统,方法和设备
    • WO2018004850A1
    • 2018-01-04
    • PCT/US2017/032938
    • 2017-05-16
    • INTEL CORPORATION
    • GOH, Eng HuatSIR, Jiun HannLIM, Min Suet
    • H01L23/00H01L23/498H01L23/31
    • In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing a Pad on Solder Mask (PoSM) semiconductor substrate package. For instance, in accordance with one embodiment, there is a substrate package having embodied therein a functional silicon die at a top layer of the substrate package; a solder resist layer beneath the functional silicon die of the substrate package; a plurality of die bumps at a bottom surface of the functional silicon die, the plurality of die bumps electrically interfacing the functional silicon die to a substrate through a plurality of solder balls at a top surface of the solder resist layer; each of the plurality of die bumps electrically interfaced to a nickel pad at least partially within the solder resist layer and beneath the solder balls; each of the plurality of die bumps electrically interfaced through the nickel pads to a conductive pad exposed at a bottom surface of the solder resist layer; and in which each of the conductive pads exposed at the bottom surface of the solder resist layer are electrically interfaced to an electrical trace at the substrate of the substrate package. Other related embodiments are disclosed.
    • 根据所公开的实施例,提供了用于实现焊盘上焊盘(PoSM)半导体衬底封装的系统,方法和设备。 例如,根据一个实施例,存在一种衬底封装,其中在衬底封装的顶层处实现了功能硅芯片; 位于衬底封装的功能硅芯片下方的阻焊层; 在所述功能硅管芯的底表面处的多个管芯凸块,所述多个管芯凸块通过所述阻焊层的顶表面处的多个焊球将所述功能硅管芯与衬底电连接; 所述多个裸片凸块中的每一个至少部分地在所述阻焊层内并且在所述焊球下方电连接到镍垫; 多个管芯凸块中的每一个通过镍焊盘电连接到暴露在阻焊层的底表面处的导电焊盘; 并且其中暴露在阻焊层的底表面处的每个导电焊盘与在衬底封装的衬底处的电迹线电接口。 披露了其他相关的实施例。