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1. 发明申请

WO2018097924A1 INDUCTOR INTERCONNECT 审中-公开
公开(公告)号：WO2018097924A1
公开(公告)日：2018-05-31
申请号：PCT/US2017/058319
申请日：2017-10-25
申请人： INTEL CORPORATION
发明人： LIM, Min Suet , KUAN, Chin Lee , GOH, Eng Huat , YONG, Khang Choong , CHEAH, Bok Eng , KONG, Jackson Chung Peng , LOO, Howe Yin
IPC分类号： H01L25/07 , H01L23/538 , H01L49/02 , H01L23/498
摘要： A device and method of utilizing spiral interconnects for voltage and power regulation are shown. Examples of spiral interconnects include air core inductors. An integrated circuit package attached to a motherboard using spiral interconnects is shown. Methods of attaching an integrated circuit package to a motherboard using spiral interconnects are shown including air core inductors. Methods of attaching spiral interconnects include using electrically conductive adhesive or solder.

2. 发明申请

WO2017111903A1 INTEGRATING SYSTEM IN PACKAGE (SIP) WITH INPUT/OUTPUT (IO) BOARD FOR PLATFORM MINIATURIZATION 审中-公开
标题翻译：集成系统在包（SIP）与输入/输出（IO）板用于平台小型化
公开(公告)号：WO2017111903A1
公开(公告)日：2017-06-29
申请号：PCT/US2015/067085
申请日：2015-12-21
申请人： INTEL CORPORATION
发明人： GOH, Eng Huat , HOE, Wee , YONG, Khang Choong , OOI, Ping Ping
IPC分类号： H01L25/18 , H01L25/065 , H01L23/48
CPC分类号： H01L23/48 , H01L25/065 , H01L25/18 , H01L2924/1432 , H01L2924/15311 , H01L2924/15313 , H01L2924/19042 , H01L2924/19106
摘要： Methods and apparatus relating to integrating System in Package (SiP) with Input/Output (IO) board for platform miniaturization are described. In an embodiment, a SiP board includes a plurality of logic components. An IO board is coupled to the SiP board via a grid array. The plurality of logic components is provided on both sides of the SiP board and one or more of the plurality of logic components are to positioned in an opening in the IO board. Other embodiments are also disclosed and claimed.
摘要翻译：描述了与用于平台小型化的系统级封装（SiP）与输入/输出（IO）板集成有关的方法和设备。在一个实施例中，SiP板包括多个逻辑组件。 IO板通过网格阵列耦合到SiP板。多个逻辑部件设置在SiP板的两侧，并且多个逻辑部件中的一个或多个逻辑部件设置在IO板的开口中。其他实施例也被公开和要求保护。

3. 发明申请

WO2018093539A1 PACKAGE-BOTTOM THROUGH-MOLD VIA INTERPOSERS FOR LAND-SIDE CONFIGURED DEVICES FOR SYSTEM-IN-PACKAGE APPARATUS 审中-公开
公开(公告)号：WO2018093539A1
公开(公告)日：2018-05-24
申请号：PCT/US2017/058053
申请日：2017-10-24
申请人： INTEL CORPORATION
发明人： LOO, Howe Yin , GOH, Eng Huat , LIM, Min Suet , CHEAH, Bok Eng , KONG, Jackson Chung Peng , YONG, Khang Choong
IPC分类号： H01L25/065 , H01L25/07 , H01L23/498 , H01L23/28 , H01L23/00
摘要： A system-in-package apparatus includes a package substrate configured to carry at least one semiconductive device on a die side and a through-mold via package bottom interposer disposed on the package substrate on a land side. A land side board mates with the through-mold via package bottom interposer, and enough vertical space is created by the through-mold via package bottom interposer to allow space for at least one device disposed on the package substrate on the land side.

4. 发明申请

WO2018063632A1 THREE CAPACITOR STACK AND ASSOCIATED METHODS 审中-公开
标题翻译：三个电容堆叠和相关方法
公开(公告)号：WO2018063632A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/048824
申请日：2017-08-28
申请人： INTEL CORPORATION
发明人： GOH, Eng Huat , SIR, Jiun Hann , CHUA, Han Kung , LIM, Min Suet , TEOH, Hoay Tien
IPC分类号： H01G4/38 , H01G4/30
CPC分类号： H01L28/75
摘要： A three capacitor stack and associated methods are shown. An exemplary capacitor device may include a first capacitor stack that includes a first plurality of layers of reference electrodes interleaved with first capacitor electrodes, a second capacitor stack on the first capacitor stack that includes a second plurality of layers of reference electrodes interleaved with second capacitor electrodes, and a third capacitor stack on the second capacitor stack that includes a reference electrode and a third capacitor electrode. A respective layer of dielectric material is formed between the reference electrodes and the first capacitor electrodes, the second capacitor electrodes, and the third capacitor electrode.
摘要翻译：显示了三个电容器堆叠和相关的方法。示例性电容器装置可以包括：第一电容器叠层，其包括与第一电容器电极交错的第一多个参考电极层;第一电容器叠层上的第二电容器叠层，其包括与第二电容器电极交错的第二多个参考电极层以及在第二电容器堆叠上的第三电容器堆叠，其包括参考电极和第三电容器电极。在参考电极和第一电容器电极，第二电容器电极和第三电容器电极之间形成相应的介电材料层。

5. 发明申请

WO2018009168A1 ELECTRONIC DEVICE PACKAGE ON PACKAGE (POP) 审中-公开
标题翻译：电子设备包装（POP）
公开(公告)号：WO2018009168A1
公开(公告)日：2018-01-11
申请号：PCT/US2016/040908
申请日：2016-07-02
申请人： INTEL CORPORATION
发明人： GOH, Eng Huat , SIR, Jiun Hann , LIM, Min Suet , GUO, Xi
IPC分类号： H01L25/10 , H01L25/18 , H01L23/367
摘要： Electronic device package on package (POP) technology is disclosed. A POP can comprise a first electronic device package including a heat source. The POP can also comprise a second electronic device package disposed on the first electronic device package. The second electronic device package can include a substrate having a heat transfer portion proximate the heat source that facilitates heat transfer from the heat source through a thickness of the substrate. The substrate can also have an electronic component portion at least partially about the heat transfer portion that facilitates electrical communication. In addition, the POP can comprise an electronic component operably coupled to the electronic component portion.
摘要翻译：公开了电子装置封装（POP）技术。 POP可以包括包含热源的第一电子设备包。 POP还可以包括设置在第一电子设备包上的第二电子设备包。第二电子器件封装可以包括具有靠近热源的传热部分的基板，其有助于从热源通过基板厚度的热传递。衬底还可以具有电子组件部分，该电子组件部分至少部分地围绕促进电通信的传热部分。另外，POP可以包括可操作地耦合到电子组件部分的电子组件。

6. 发明申请

WO2017218135A1 CAPACITIVE INTERCONNECT IN A SEMICONDUCTOR PACKAGE 审中-公开
标题翻译：半导体封装中的容性互连
公开(公告)号：WO2017218135A1
公开(公告)日：2017-12-21
申请号：PCT/US2017/033340
申请日：2017-05-18
申请人： INTEL CORPORATION
发明人： GOH, Eng Huat , LIM, Min Suet , TAN, Fern Nee , YONG, Khang Choong , SIR, Jiun Hann
IPC分类号： H01L23/495 , H01L23/498 , H01L23/00 , H01L25/07 , H01L49/02
摘要： Capacitive interconnects and processes for fabricating the capacitive interconnects are provided. In some embodiments, the capacitive interconnect includes first metal layers, second metal layers; and dielectric layers including a dielectric layer that intercalates a first metal layer of the first metal layers and a second metal layer of the second metal layers. Such layers can be assembled in a nearly concentric arrangement, where the dielectric layer abuts the first metal layer and the second metal layer abuts the dielectric layer. In addition, the capacitive interconnect can include a first electrode electrically coupled to at least one of the first metal layers, and a second electrode electrically coupled to at least one of the second metal layers, the second electrode assembled opposite to the first electrode. The first electrode and the second electrode can include respective solder tops.
摘要翻译：提供用于制造电容互连的电容互连和工艺。在一些实施例中，电容性互连件包括第一金属层，第二金属层; 以及介电层，其包括插入第一金属层的第一金属层和第二金属层的第二金属层的介电层。这些层可以以几乎同心的结构组装，其中电介质层邻接第一金属层并且第二金属层邻接电介质层。另外，电容性互连可以包括电耦合到第一金属层中的至少一个的第一电极和电耦合到第二金属层中的至少一个的第二电极，第二电极与第一电极相对组装。第一电极和第二电极可以包括各自的焊料顶部。

7. 发明申请

WO2017099876A1 FOLDABLE FABRIC-BASED PACKAGING SOLUTION 审中-公开
标题翻译：可折叠的基于织物的包装解决方案
公开(公告)号：WO2017099876A1
公开(公告)日：2017-06-15
申请号：PCT/US2016/055564
申请日：2016-10-05
申请人： INTEL CORPORATION
发明人： CHEAH, Bok Eng , KONG, Jackson Chung Peng , OOI, Kooi Chi , SCHAECHER, Mark A. , YEW, Teong Guan , GOH, Eng Huat
IPC分类号： H01L23/498 , H01L23/538 , H01L23/495 , H01L23/14 , H01L25/065 , H01L25/11 , H05K3/46
CPC分类号： H02J7/025 , H01F27/36 , H01F38/14 , H01L21/4853 , H01L21/565 , H01L21/568 , H01L23/3121 , H01L25/50 , H02J50/10
摘要： Methods, systems, and apparatuses for a foldable fabric-based semiconductor package (FFP) that can assist with charging a secondary cell are described. An FFP includes: a ground plane; a first component over the ground plane; a second component adjacent to the ground plane; a third component adjacent to the second component; a molding compound encapsulating the ground plane, the first component, the second component, and the third component; a first fabric layer on a top side of the molding compound; and a second fabric layer on a bottom side of the molding compound. Each of the first, second, and third components includes one or more semiconductor dies. The third component is electrically coupled to each of the first and second components. The first and second components can wireless charge the secondary cell. The third component can power the first and second components. The ground plane can protect against electromagnetic signals.
摘要翻译：描述了用于可辅助给二次电池充电的可折叠基于织物的半导体封装（FFP）的方法，系统和设备。 FFP包括：地平面; 地平面上的第一部件; 邻近接地平面的第二组件; 与第二部件相邻的第三部件; 包封接地平面，第一部件，第二部件和第三部件的模塑料; 在模塑料的顶侧上的第一织物层; 和在模塑料的底侧上的第二织物层。第一，第二和第三部件中的每一个都包括一个或多个半导体管芯。第三组件电耦合到第一和第二组件中的每一个。第一和第二组件可以无线充电辅助电池。第三部件可以为第一和第二部件供电。接地层可以防止电磁信号。

8. 发明申请

WO2018093521A1 MULTIPLE-COMPONENT SUBSTRATE FOR A MICROELECTRONIC DEVICE 审中-公开
公开(公告)号：WO2018093521A1
公开(公告)日：2018-05-24
申请号：PCT/US2017/057224
申请日：2017-10-18
申请人： INTEL CORPORATION
发明人： LIM, Min Suet , CHANG, Mooi Ling , GOH, Eng Huat , TAN, Say Thong Tony , CHUAH, Tin Poay
IPC分类号： H01L25/065 , H01L25/07 , H01L23/498 , H01L23/00
CPC分类号： H01L23/49833 , H01L21/4853 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/5385 , H01L23/5386
摘要： Microelectronic devices having a multiple-component substrate assembly. A primary supports one or more integrated circuits, and an auxiliary substrate is coupled to, and makes electrical connections with, the primary substrate. The primary substrate will define a pinout for some or all contacts of the integrated circuit, and the auxiliary substrate will provide an additional pinout option. Different configurations of a single primary substrate may be adapted to different applications through use of different configurations of auxiliary substrates.

9. 发明申请

WO2018004850A1 SYSTEMS, METHODS, AND APPARATUSES FOR IMPLEMENTING A PAD ON SOLDER MASK (POSM) SEMICONDUCTOR SUBSTRATE PACKAGE 审中-公开
标题翻译：用于在焊料掩模（POSM）半导体衬底封装上实施焊盘的系统，方法和设备
公开(公告)号：WO2018004850A1
公开(公告)日：2018-01-04
申请号：PCT/US2017/032938
申请日：2017-05-16
申请人： INTEL CORPORATION
发明人： GOH, Eng Huat , SIR, Jiun Hann , LIM, Min Suet
IPC分类号： H01L23/00 , H01L23/498 , H01L23/31
摘要： In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing a Pad on Solder Mask (PoSM) semiconductor substrate package. For instance, in accordance with one embodiment, there is a substrate package having embodied therein a functional silicon die at a top layer of the substrate package; a solder resist layer beneath the functional silicon die of the substrate package; a plurality of die bumps at a bottom surface of the functional silicon die, the plurality of die bumps electrically interfacing the functional silicon die to a substrate through a plurality of solder balls at a top surface of the solder resist layer; each of the plurality of die bumps electrically interfaced to a nickel pad at least partially within the solder resist layer and beneath the solder balls; each of the plurality of die bumps electrically interfaced through the nickel pads to a conductive pad exposed at a bottom surface of the solder resist layer; and in which each of the conductive pads exposed at the bottom surface of the solder resist layer are electrically interfaced to an electrical trace at the substrate of the substrate package. Other related embodiments are disclosed.
摘要翻译：根据所公开的实施例，提供了用于实现焊盘上焊盘（PoSM）半导体衬底封装的系统，方法和设备。例如，根据一个实施例，存在一种衬底封装，其中在衬底封装的顶层处实现了功能硅芯片; 位于衬底封装的功能硅芯片下方的阻焊层; 在所述功能硅管芯的底表面处的多个管芯凸块，所述多个管芯凸块通过所述阻焊层的顶表面处的多个焊球将所述功能硅管芯与衬底电连接; 所述多个裸片凸块中的每一个至少部分地在所述阻焊层内并且在所述焊球下方电连接到镍垫; 多个管芯凸块中的每一个通过镍焊盘电连接到暴露在阻焊层的底表面处的导电焊盘; 并且其中暴露在阻焊层的底表面处的每个导电焊盘与在衬底封装的衬底处的电迹线电接口。披露了其他相关的实施例。

10. 发明申请

WO2017099931A1 REDUCED-HEIGHT MEMORY SYSTEM AND METHOD 审中-公开
标题翻译：减小高度存储器系统和方法
公开(公告)号：WO2017099931A1
公开(公告)日：2017-06-15
申请号：PCT/US2016/061043
申请日：2016-11-09
申请人： INTEL CORPORATION
发明人： GOH, Eng Huat , LIM, Min Suet , SIR, Jiun Hann
IPC分类号： H01L23/31 , H01L23/00 , H01L23/498
CPC分类号： H01L25/0657 , H01L23/3128 , H01L25/105 , H01L25/18 , H01L25/50 , H01L27/108 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2225/0651 , H01L2225/0652 , H01L2225/06548 , H01L2225/06586 , H01L2225/1023 , H01L2225/1058 , H01L2225/1088 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/1815 , H01L2924/18161 , H01L2924/00014
摘要： A computer memory module can include a molded layer disposed on a DRAM substrate. The molded layer can encapsulate a DRAM die and wire bonds that connect the DRAM die to the DRAM substrate, and can be shaped to include at least one cavity having a footprint sized to accommodate a system on chip (SOC) die. The DRAM module can attach to an SOC package so that the SOC die and the DRAM die are both positioned between the DRAM substrate and the SOC package, the DRAM substrate can form its electrical connections on only one side of the DRAM substrate, and the SOC die can fit at least partially into the cavity in the molded layer. This can reduce a package Z-height, compared to conventional DRAM packages in which the SOC die and the DRAM die are positioned on opposite sides of the DRAM substrate.
摘要翻译：计算机存储器模块可以包括设置在DRAM基板上的模制层。模制层可以封装DRAM管芯和将DRAM管芯连接至DRAM衬底的引线接合，并且可以被成形为包括至少一个具有尺寸适合于容纳片上系统（SOC）管芯的覆盖区的空腔。 DRAM模块可以连接到SOC封装，使得SOC裸片和DRAM裸片都位于DRAM衬底和SOC封装之间，DRAM衬底可以仅在DRAM衬底的一侧形成其电连接，并且SOC 模具可以至少部分地配合到模制层中的空腔中。与其中SOC裸片和DRAM裸片位于DRAM衬底的相对侧上的常规DRAM封装相比，这可以减小封装Z高度。

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