专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2018097924A1 INDUCTOR INTERCONNECT 审中-公开
公开(公告)号：WO2018097924A1
公开(公告)日：2018-05-31
申请号：PCT/US2017/058319
申请日：2017-10-25
申请人： INTEL CORPORATION
发明人： LIM, Min Suet , KUAN, Chin Lee , GOH, Eng Huat , YONG, Khang Choong , CHEAH, Bok Eng , KONG, Jackson Chung Peng , LOO, Howe Yin
IPC分类号： H01L25/07 , H01L23/538 , H01L49/02 , H01L23/498
摘要： A device and method of utilizing spiral interconnects for voltage and power regulation are shown. Examples of spiral interconnects include air core inductors. An integrated circuit package attached to a motherboard using spiral interconnects is shown. Methods of attaching an integrated circuit package to a motherboard using spiral interconnects are shown including air core inductors. Methods of attaching spiral interconnects include using electrically conductive adhesive or solder.

2. 发明申请

WO2018063279A1 VERTICAL EMBEDDED COMPONENT IN A PRINTED CIRCUIT BOARD BLIND HOLE 审中-公开
标题翻译：垂直嵌入式组件在印刷电路板盲孔中的应用
公开(公告)号：WO2018063279A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054643
申请日：2016-09-30
申请人： INTEL CORPORATION
发明人： CHUAH, Tin Poay , LIM, Min Suet , TEOH, Hoay Tien , CHANG, Mooi Ling , KUAN, Chin Lee
IPC分类号： H05K3/42 , H05K3/34 , H05K3/46
CPC分类号： H05K3/0035 , H05K1/184 , H05K3/341 , H05K2201/09072 , H05K2201/10454 , H05K2203/0126 , H05K2203/1438
摘要： A printed circuit board (PCB) comprises a blind via and a discrete component vertically embedded within the blind via.
摘要翻译：印刷电路板（PCB）包括盲孔和垂直嵌入盲孔内的分立元件。

3. 发明申请

WO2018093521A1 MULTIPLE-COMPONENT SUBSTRATE FOR A MICROELECTRONIC DEVICE 审中-公开
公开(公告)号：WO2018093521A1
公开(公告)日：2018-05-24
申请号：PCT/US2017/057224
申请日：2017-10-18
申请人： INTEL CORPORATION
发明人： LIM, Min Suet , CHANG, Mooi Ling , GOH, Eng Huat , TAN, Say Thong Tony , CHUAH, Tin Poay
IPC分类号： H01L25/065 , H01L25/07 , H01L23/498 , H01L23/00
CPC分类号： H01L23/49833 , H01L21/4853 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/5385 , H01L23/5386
摘要： Microelectronic devices having a multiple-component substrate assembly. A primary supports one or more integrated circuits, and an auxiliary substrate is coupled to, and makes electrical connections with, the primary substrate. The primary substrate will define a pinout for some or all contacts of the integrated circuit, and the auxiliary substrate will provide an additional pinout option. Different configurations of a single primary substrate may be adapted to different applications through use of different configurations of auxiliary substrates.

4. 发明申请

WO2018004850A1 SYSTEMS, METHODS, AND APPARATUSES FOR IMPLEMENTING A PAD ON SOLDER MASK (POSM) SEMICONDUCTOR SUBSTRATE PACKAGE 审中-公开
标题翻译：用于在焊料掩模（POSM）半导体衬底封装上实施焊盘的系统，方法和设备
公开(公告)号：WO2018004850A1
公开(公告)日：2018-01-04
申请号：PCT/US2017/032938
申请日：2017-05-16
申请人： INTEL CORPORATION
发明人： GOH, Eng Huat , SIR, Jiun Hann , LIM, Min Suet
IPC分类号： H01L23/00 , H01L23/498 , H01L23/31
摘要： In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing a Pad on Solder Mask (PoSM) semiconductor substrate package. For instance, in accordance with one embodiment, there is a substrate package having embodied therein a functional silicon die at a top layer of the substrate package; a solder resist layer beneath the functional silicon die of the substrate package; a plurality of die bumps at a bottom surface of the functional silicon die, the plurality of die bumps electrically interfacing the functional silicon die to a substrate through a plurality of solder balls at a top surface of the solder resist layer; each of the plurality of die bumps electrically interfaced to a nickel pad at least partially within the solder resist layer and beneath the solder balls; each of the plurality of die bumps electrically interfaced through the nickel pads to a conductive pad exposed at a bottom surface of the solder resist layer; and in which each of the conductive pads exposed at the bottom surface of the solder resist layer are electrically interfaced to an electrical trace at the substrate of the substrate package. Other related embodiments are disclosed.
摘要翻译：根据所公开的实施例，提供了用于实现焊盘上焊盘（PoSM）半导体衬底封装的系统，方法和设备。例如，根据一个实施例，存在一种衬底封装，其中在衬底封装的顶层处实现了功能硅芯片; 位于衬底封装的功能硅芯片下方的阻焊层; 在所述功能硅管芯的底表面处的多个管芯凸块，所述多个管芯凸块通过所述阻焊层的顶表面处的多个焊球将所述功能硅管芯与衬底电连接; 所述多个裸片凸块中的每一个至少部分地在所述阻焊层内并且在所述焊球下方电连接到镍垫; 多个管芯凸块中的每一个通过镍焊盘电连接到暴露在阻焊层的底表面处的导电焊盘; 并且其中暴露在阻焊层的底表面处的每个导电焊盘与在衬底封装的衬底处的电迹线电接口。披露了其他相关的实施例。

5. 发明申请

WO2017099931A1 REDUCED-HEIGHT MEMORY SYSTEM AND METHOD 审中-公开
标题翻译：减小高度存储器系统和方法
公开(公告)号：WO2017099931A1
公开(公告)日：2017-06-15
申请号：PCT/US2016/061043
申请日：2016-11-09
申请人： INTEL CORPORATION
发明人： GOH, Eng Huat , LIM, Min Suet , SIR, Jiun Hann
IPC分类号： H01L23/31 , H01L23/00 , H01L23/498
CPC分类号： H01L25/0657 , H01L23/3128 , H01L25/105 , H01L25/18 , H01L25/50 , H01L27/108 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2225/0651 , H01L2225/0652 , H01L2225/06548 , H01L2225/06586 , H01L2225/1023 , H01L2225/1058 , H01L2225/1088 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/1815 , H01L2924/18161 , H01L2924/00014
摘要： A computer memory module can include a molded layer disposed on a DRAM substrate. The molded layer can encapsulate a DRAM die and wire bonds that connect the DRAM die to the DRAM substrate, and can be shaped to include at least one cavity having a footprint sized to accommodate a system on chip (SOC) die. The DRAM module can attach to an SOC package so that the SOC die and the DRAM die are both positioned between the DRAM substrate and the SOC package, the DRAM substrate can form its electrical connections on only one side of the DRAM substrate, and the SOC die can fit at least partially into the cavity in the molded layer. This can reduce a package Z-height, compared to conventional DRAM packages in which the SOC die and the DRAM die are positioned on opposite sides of the DRAM substrate.
摘要翻译：计算机存储器模块可以包括设置在DRAM基板上的模制层。模制层可以封装DRAM管芯和将DRAM管芯连接至DRAM衬底的引线接合，并且可以被成形为包括至少一个具有尺寸适合于容纳片上系统（SOC）管芯的覆盖区的空腔。 DRAM模块可以连接到SOC封装，使得SOC裸片和DRAM裸片都位于DRAM衬底和SOC封装之间，DRAM衬底可以仅在DRAM衬底的一侧形成其电连接，并且SOC 模具可以至少部分地配合到模制层中的空腔中。与其中SOC裸片和DRAM裸片位于DRAM衬底的相对侧上的常规DRAM封装相比，这可以减小封装Z高度。

6. 发明申请

WO2017044246A1 MULTI-ORIENTATION DISPLAY DEVICE 审中-公开
标题翻译：多方位显示装置
公开(公告)号：WO2017044246A1
公开(公告)日：2017-03-16
申请号：PCT/US2016/046654
申请日：2016-08-12
申请人： INTEL CORPORATION
发明人： YEE, Chee Chun , BROWNING, David W. , CHEAH, Bok Eng , KONG, Jackson Chung Peng , LIM, Min Suet , LOO, Howe Yin , OH, Poh Tat
IPC分类号： G06F1/16 , H04M1/02
CPC分类号： G06F1/1652 , G06F1/1626 , G06F1/1641 , G06F1/1643 , G06F1/1675 , G06F3/041 , G06F2203/04102
摘要： A computing device includes a flexible display screen, a housing to house at least one processor device and at least one memory element, and a first wing to support a side portion of the display screen. The front face of the housing includes a center portion of the display screen. The first wing is connected to the housing by a hinge, the first wing configured to swivel about an axis defined by the hinge. The hinge is configured to lock the first wing in at least two wing positions, a first of the wing positions supports the side portion of the display screen in a first orientation, a second of the wing positions supports the side portion of the display screen in a second orientation, and the side portion of the display screen is active in the first orientation and hidden in the second orientation.
摘要翻译：计算设备包括柔性显示屏，用于容纳至少一个处理器设备和至少一个存储器元件的外壳，以及支撑显示屏幕的侧部的第一翼。壳体的前表面包括显示屏的中心部分。第一翼通过铰链连接到壳体，第一翼构造成围绕由铰链限定的轴线旋转。所述铰链被构造成将所述第一翼片锁定在至少两个翼位置中，所述机翼位置中的第一翼位置以第一方向支撑所述显示屏幕的侧部，所述机翼位置中的第二翼支撑所述显示屏幕的侧部第二取向，并且显示屏幕的侧部在第一取向中是有效的，并且在第二取向中被隐藏。

7. 发明申请

WO2015148057A1 LOW-PROFILE HINGE FOR AN ELECTRONIC DEVICE 审中-公开
标题翻译：用于电子设备的低剖面铰链
公开(公告)号：WO2015148057A1
公开(公告)日：2015-10-01
申请号：PCT/US2015/018204
申请日：2015-02-28
申请人： INTEL CORPORATION
发明人： LIM, Min Suet , CHEAH, Bok Eng , LOO, Howe Yin , KONG, Jackson Chung Peng , OH, Poh Tat
IPC分类号： H05K7/16 , G06F1/16
CPC分类号： G06F1/1681 , G06F1/1616 , G06F1/1618 , G06F1/1637 , Y10T16/547
摘要： Particular embodiments described herein provide for an electronic device, such as a notebook computer or laptop, that includes a circuit board coupled to a plurality of electronic components (which includes any type of components, elements, circuitry, etc.}. One particular example implementation of the electronic device may include a Sow-profile hinge design that includes a first segment that connects to a first element using a first coupler and to a second segment that connects to the first segment using a second coupler, where the second segment connects to a second element using a third coupler. The first coupler, the second coupler, and the third coupler may each have a first coupling arm and a second coupling arm and the first coupling arm can be offset from a plane of the second coupling arm by about five degrees to about forty-five degrees.
摘要翻译：本文描述的特定实施例提供了一种电子设备，例如笔记本电脑或笔记本电脑，其包括耦合到多个电子组件（其包括任何类型的组件，元件，电路等）的电路板。该电子设备可以包括母线型铰链设计，其包括使用第一耦合器连接到第一元件的第一段和使用第二耦合器连接到第一段的第二段，其中第二段连接到第一联接器，第二联接器和第三联接器可以各自具有第一联接臂和第二联接臂，并且第一联接臂可以从第二联接臂的平面偏移约五分之一度至约四十五度。

8. 发明申请

WO2018125503A1 STRANDED TRANSMISSION LINE AND USES THEREOF 审中-公开
公开(公告)号：WO2018125503A1
公开(公告)日：2018-07-05
申请号：PCT/US2017/063970
申请日：2017-11-30
申请人： INTEL CORPORATION
发明人： SONG, Wil Choon , YONG, Khang Choong , LIM, Min Suet , GOH, Eng Huat , KOH, Boon Ping
IPC分类号： H05K1/02 , H01P3/02
CPC分类号： H01P3/082 , H01P3/026 , H01P3/08 , H01P3/10 , H01P5/12 , H01P11/003 , H05K1/024 , H05K1/0242 , H05K1/0243 , H05K1/0245 , H05K2201/09254
摘要： Various embodiments disclosed relate to a circuit. The circuit includes a transceiver adapted to generate a signal. A stranded transmission line is connected to the transceiver. The signal is then transmitted through the first pair of conductive strands.

9. 发明申请

WO2018118321A1 SLOT ANTENNA ON A PRINTED CIRCUIT BOARD (PCB) 审中-公开
公开(公告)号：WO2018118321A1
公开(公告)日：2018-06-28
申请号：PCT/US2017/062759
申请日：2017-11-21
申请人： INTEL CORPORATION
发明人： GOH, Eng Huat , LIM, Min Suet , KOH, Boon Ping , SONG, Wil Choon , YONG, Khang Choong
IPC分类号： H01Q13/10 , H01Q1/38
摘要： Embodiments herein disclose techniques for apparatuses and methods for making a slot antenna on a PCB with a cutout. A PCB may include a metal layer. The metal layer may include a cavity to be a first radiating element of an antenna, and a slot to be a second radiating element of the antenna. In addition, the cavity may extend to be the cutout of the PCB through other layers of the PCB. The first and second radiating elements may provide a determined transmission frequency for the antenna. The metal layer may further include a portion of a transmission line of the antenna, and the transmission line is in contact with the cavity and the slot. A package may be affixed to the PCB, where a portion of the package may be within the cutout of the PCB. Other embodiments may be described and/or claimed.

10. 发明申请

WO2018063154A1 3D STACKED-IN-RECESS SYSTEM IN PACKAGE 审中-公开
标题翻译：包装中的3D堆叠入库系统
公开(公告)号：WO2018063154A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/053935
申请日：2016-09-27
申请人： INTEL CORPORATION , CHEAH, Bok Eng , LIM, Min Suet , KONG, Jackson Chung Peng , LOO, Howe Yin
发明人： CHEAH, Bok Eng , LIM, Min Suet , KONG, Jackson Chung Peng , LOO, Howe Yin
IPC分类号： H01L25/065 , H01L23/538 , H01L23/48 , H01L21/48 , H01L23/00
CPC分类号： H01L21/48 , H01L23/00 , H01L23/48 , H01L23/538 , H01L23/552 , H01L25/0652 , H01L25/0655 , H01L25/18 , H01L25/50 , H01L29/0657 , H01L2224/13025 , H01L2224/16146 , H01L2224/16225 , H01L2224/16235 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/1432 , H01L2924/1434 , H01L2924/15192 , H01L2924/15311 , H01L2924/3025
摘要： A system in package device includes a landed first die disposed on a package substrate. The landed first die includes a notch that is contoured and that opens the backside surface of the die to a ledge. A stacked die is mounted at the ledge and the two dice are each contacted by a through-silicon via (TSV). The system in package device also includes a landed subsequent die on the package substrate and a contoured notch in the landed subsequent die and the notch in the first die form a composite contoured recess into which the stacked die is seated.
摘要翻译：封装装置中的系统包括设置在封装衬底上的落地第一管芯。落地的第一模具包括具有轮廓的凹口并且将模具的背面表面打开成凸缘。堆叠式芯片安装在壁架上，并且两个芯片分别与硅通孔（TSV）接触。封装装置中的系统还包括位于封装衬底上的落地后续裸片，落地后续裸片中的轮廓凹槽和第一裸片中的凹槽形成组合轮廓凹槽，堆叠裸片位于该凹槽中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式