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1. 发明申请

WO2017099784A1 FLEXIBLE COMPUTING DEVICE THAT INCLUDES A PLURALITY OF DISPLAYS 审中-公开
标题翻译：灵活的计算设备，包括多个显示器
公开(公告)号：WO2017099784A1
公开(公告)日：2017-06-15
申请号：PCT/US2015/065080
申请日：2015-12-10
申请人： INTEL CORPORATION
发明人： KONG, Jackson Chung Peng , OOI, Kooi Chi , CHEAH, Bok Eng , GOH, Eng Huat
IPC分类号： G06F1/16 , G09F9/30
CPC分类号： G06F1/1652 , G06F1/163
摘要： A flexible electronic device that includes a flexible substrate having an upper surface and a lower surface and interconnects extending between the upper surface and the lower surface; a flexible display mounted directly to the upper surface of the flexible substrate such that the flexible display is electrically connected to the flexible substrate; a first encapsulant mounted to the upper surface of the flexible substrate such that the flexible display is at least partially embedded within the first encapsulant; an electronic component mounted to a lower surface of the flexible substrate such that the electronic component is electrically connected to the flexible substrate; a second encapsulant mounted to the lower surface of the flexible substrate such that the electronic component is at least partially embedded within the second encapsulant; a flexible casing that surrounds the electronic component and the second encapsulant.
摘要翻译：一种柔性电子装置，其包括具有上表面和下表面的柔性基板以及在所述上表面和所述下表面之间延伸的互连; 直接安装到所述柔性基板的上表面的柔性显示器，使得所述柔性显示器电连接到所述柔性基板; 第一密封剂，其安装到所述柔性衬底的上表面，使得所述柔性显示器至少部分地嵌入所述第一密封剂内; 电子部件，所述电子部件安装到所述柔性基板的下表面，使得所述电子部件电连接到所述柔性基板; 第二密封剂，所述第二密封剂安装到所述柔性基板的所述下表面，使得所述电子组件至少部分地嵌入所述第二密封剂内; 包围电子元件和第二密封剂的柔性外壳。

2. 发明申请

WO2017044246A1 MULTI-ORIENTATION DISPLAY DEVICE 审中-公开
标题翻译：多方位显示装置
公开(公告)号：WO2017044246A1
公开(公告)日：2017-03-16
申请号：PCT/US2016/046654
申请日：2016-08-12
申请人： INTEL CORPORATION
发明人： YEE, Chee Chun , BROWNING, David W. , CHEAH, Bok Eng , KONG, Jackson Chung Peng , LIM, Min Suet , LOO, Howe Yin , OH, Poh Tat
IPC分类号： G06F1/16 , H04M1/02
CPC分类号： G06F1/1652 , G06F1/1626 , G06F1/1641 , G06F1/1643 , G06F1/1675 , G06F3/041 , G06F2203/04102
摘要： A computing device includes a flexible display screen, a housing to house at least one processor device and at least one memory element, and a first wing to support a side portion of the display screen. The front face of the housing includes a center portion of the display screen. The first wing is connected to the housing by a hinge, the first wing configured to swivel about an axis defined by the hinge. The hinge is configured to lock the first wing in at least two wing positions, a first of the wing positions supports the side portion of the display screen in a first orientation, a second of the wing positions supports the side portion of the display screen in a second orientation, and the side portion of the display screen is active in the first orientation and hidden in the second orientation.
摘要翻译：计算设备包括柔性显示屏，用于容纳至少一个处理器设备和至少一个存储器元件的外壳，以及支撑显示屏幕的侧部的第一翼。壳体的前表面包括显示屏的中心部分。第一翼通过铰链连接到壳体，第一翼构造成围绕由铰链限定的轴线旋转。所述铰链被构造成将所述第一翼片锁定在至少两个翼位置中，所述机翼位置中的第一翼位置以第一方向支撑所述显示屏幕的侧部，所述机翼位置中的第二翼支撑所述显示屏幕的侧部第二取向，并且显示屏幕的侧部在第一取向中是有效的，并且在第二取向中被隐藏。

3. 发明申请

WO2016094024A1 VERTICAL TRENCH ROUTING IN A SUBSTRATE 审中-公开
标题翻译：在基板上垂直倾斜路由
公开(公告)号：WO2016094024A1
公开(公告)日：2016-06-16
申请号：PCT/US2015/060444
申请日：2015-11-12
申请人： INTEL CORPORATION
发明人： KONG, Jackson , CHEAH, Bok Eng , YONG, Khang Choong , HECK, Howard L. , CHEN, Kuan-Yu
IPC分类号： H05K1/02 , H05K3/00
CPC分类号： H01L21/486 , H01L21/4846 , H01L21/4857 , H01L23/49822 , H01L23/49827 , H01L24/10 , H01P3/003 , H01P3/026 , H01P3/04 , H01P3/08 , H01P3/082 , H01P5/028 , H05K1/0224 , H05K1/0242 , H05K1/0245 , H05K2201/0376
摘要： An interconnect topology that includes vertical trench routing in a substrate is disclosed. In one embodiment, the interconnect comprises a substrate having a plurality of layers including a first ground plane layer; a pair of signal conductors that form a differential signal pair, each conductor of the pair of signal conductors having a first portion and a second portion, the second portion extending from the first portion into at least one of the plurality of layers, wherein width of the second portion is less than width of the first portion; and wherein the first ground plane layer is only a first partial layer and has a first void region that is closer to the pair of signal conductors than the first partial layer.
摘要翻译：公开了一种在衬底中包括垂直沟槽布线的互连拓扑。在一个实施例中，互连包括具有包括第一接地平面层的多个层的衬底; 形成差分信号对的一对信号导体，所述一对信号导体中的每个导体具有第一部分和第二部分，所述第二部分从所述第一部分延伸到所述多个层中的至少一个层中，其中，第二部分小于第一部分的宽度; 并且其中所述第一接地层仅为第一部分层，并且具有比所述第一部分层更靠近所述一对信号导体的第一空隙区域。

4. 发明申请

WO2015148057A1 LOW-PROFILE HINGE FOR AN ELECTRONIC DEVICE 审中-公开
标题翻译：用于电子设备的低剖面铰链
公开(公告)号：WO2015148057A1
公开(公告)日：2015-10-01
申请号：PCT/US2015/018204
申请日：2015-02-28
申请人： INTEL CORPORATION
发明人： LIM, Min Suet , CHEAH, Bok Eng , LOO, Howe Yin , KONG, Jackson Chung Peng , OH, Poh Tat
IPC分类号： H05K7/16 , G06F1/16
CPC分类号： G06F1/1681 , G06F1/1616 , G06F1/1618 , G06F1/1637 , Y10T16/547
摘要： Particular embodiments described herein provide for an electronic device, such as a notebook computer or laptop, that includes a circuit board coupled to a plurality of electronic components (which includes any type of components, elements, circuitry, etc.}. One particular example implementation of the electronic device may include a Sow-profile hinge design that includes a first segment that connects to a first element using a first coupler and to a second segment that connects to the first segment using a second coupler, where the second segment connects to a second element using a third coupler. The first coupler, the second coupler, and the third coupler may each have a first coupling arm and a second coupling arm and the first coupling arm can be offset from a plane of the second coupling arm by about five degrees to about forty-five degrees.
摘要翻译：本文描述的特定实施例提供了一种电子设备，例如笔记本电脑或笔记本电脑，其包括耦合到多个电子组件（其包括任何类型的组件，元件，电路等）的电路板。该电子设备可以包括母线型铰链设计，其包括使用第一耦合器连接到第一元件的第一段和使用第二耦合器连接到第一段的第二段，其中第二段连接到第一联接器，第二联接器和第三联接器可以各自具有第一联接臂和第二联接臂，并且第一联接臂可以从第二联接臂的平面偏移约五分之一度至约四十五度。

5. 发明申请

WO2021061246A1 MOLDED INTERCONNECTS IN BRIDGES FOR INTEGRATED-CIRCUIT PACKAGES 审中-公开
公开(公告)号：WO2021061246A1
公开(公告)日：2021-04-01
申请号：PCT/US2020/039907
申请日：2020-06-26
申请人： INTEL CORPORATION
发明人： ONG, Jenny Shio Yin , LIM, Seok Ling , CHEAH, Bok Eng , KONG, Jackson Chung Peng
IPC分类号： H01L23/495 , H01L23/498 , H01L23/58
摘要： Disclosed embodiments include molded interconnect bridges that are in a molded frame, where the molded frame includes passive devices that couple to a metal buildup layer that includes at least one power rail and one ground rail. The molded interconnects bridge is embedded in an integrated-circuit package substrate between a die side and a land side, and closer to the die side.

6. 发明申请

WO2018125443A1 MULTI-CONDUCTOR INTERCONNECT STRUCTURE FOR A MICROELECTRONIC DEVICE 审中-公开
公开(公告)号：WO2018125443A1
公开(公告)日：2018-07-05
申请号：PCT/US2017/062973
申请日：2017-11-22
申请人： INTEL CORPORATION
发明人： OOI, Ping Ping , CHEAH, Bok Eng , KONG, Jackson Chung Peng , OOI, Kooi Chi
IPC分类号： H01L25/065 , H01L23/485 , H01L23/00
摘要： A multi-conductor interconnect for a microelectronic device incorporates multiple conductors and integrated shielding for the conductors. The multi-conductor interconnect includes first and second groups of conductors interleaved with one another within a dielectric structure. One of the groups of conductors may be coupled to a reference voltage node to provide shielding for the other group of conductors. The multi-conductor interconnect may further include a shield layer extending over some portion, or all, of the conductors of the first and second groups.

7. 发明申请

WO2018097924A1 INDUCTOR INTERCONNECT 审中-公开
公开(公告)号：WO2018097924A1
公开(公告)日：2018-05-31
申请号：PCT/US2017/058319
申请日：2017-10-25
申请人： INTEL CORPORATION
发明人： LIM, Min Suet , KUAN, Chin Lee , GOH, Eng Huat , YONG, Khang Choong , CHEAH, Bok Eng , KONG, Jackson Chung Peng , LOO, Howe Yin
IPC分类号： H01L25/07 , H01L23/538 , H01L49/02 , H01L23/498
摘要： A device and method of utilizing spiral interconnects for voltage and power regulation are shown. Examples of spiral interconnects include air core inductors. An integrated circuit package attached to a motherboard using spiral interconnects is shown. Methods of attaching an integrated circuit package to a motherboard using spiral interconnects are shown including air core inductors. Methods of attaching spiral interconnects include using electrically conductive adhesive or solder.

8. 发明申请

WO2017078717A1 STACKED PACKAGE ASSEMBLY WITH VOLTAGE REFERENCE PLANE 审中-公开
标题翻译：采用电压基准面的堆叠封装组件
公开(公告)号：WO2017078717A1
公开(公告)日：2017-05-11
申请号：PCT/US2015/059191
申请日：2015-11-05
申请人： INTEL CORPORATION
发明人： CHEAH, Bok Eng , KONG, Jackson, Chung Peng , OOI, Ping Ping , OOI, Kooi Chi , PERIAMAN, Shanggar
IPC分类号： H01L25/065 , H01L25/07 , H01L23/48
CPC分类号： H01L24/20 , H01L21/568 , H01L23/552 , H01L24/19 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06568 , H01L2225/1035 , H01L2225/1058 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/00012 , H01L2924/00
摘要： Embodiments of the present disclosure are directed toward a stacked package assembly for embedded dies and associated techniques and configurations. In one embodiment, stacked package assembly may comprise a first die package and a second die package stacked one upon the other with plural interconnections between them; and a voltage reference plane embedded in at least one of the first and second die packages in proximity and generally parallel to the other of the first and second die packages.
摘要翻译：本公开的实施例针对用于嵌入式裸片的堆叠封装组件以及相关技术和配置。在一个实施例中，堆叠封装组件可以包括彼此堆叠的第一管芯封装和第二管芯封装，其间具有多个互连; 以及嵌入第一和第二管芯封装中的至少一个中的电压参考平面，所述电压参考平面接近且大致平行于第一和第二管芯封装中的另一个。

9. 发明申请

WO2014003533A1 MULTI-DIE SEMICONDUCTOR STRUCTURE WITH INTERMEDIATE VERTICAL SIDE CHIP AND SEMICONDUCTOR PACKAGE FOR SAME 审中-公开
标题翻译：具有中间垂直侧芯片和半导体封装的多芯半导体结构
公开(公告)号：WO2014003533A1
公开(公告)日：2014-01-03
申请号：PCT/MY2012/000191
申请日：2012-06-25
申请人： INTEL CORPORATION , CHEAH, Bok Eng , PERIAMAN, Shanggar , OOI, Kooi Chi , KONG, Jackson Chung Peng
发明人： CHEAH, Bok Eng , PERIAMAN, Shanggar , OOI, Kooi Chi , KONG, Jackson Chung Peng
IPC分类号： H01L23/48 , H01L23/12
CPC分类号： H01L25/0652 , H01L23/3128 , H01L23/3142 , H01L23/481 , H01L23/5386 , H01L23/5389 , H01L24/02 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/73 , H01L24/80 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/02371 , H01L2224/02372 , H01L2224/0401 , H01L2224/0557 , H01L2224/06181 , H01L2224/06182 , H01L2224/06183 , H01L2224/06189 , H01L2224/06517 , H01L2224/131 , H01L2224/16137 , H01L2224/16145 , H01L2224/16225 , H01L2224/1703 , H01L2224/17181 , H01L2224/17183 , H01L2224/32225 , H01L2224/73204 , H01L2224/80894 , H01L2224/81815 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2225/06555 , H01L2225/06562 , H01L2225/06565 , H01L2924/00014 , H01L2924/10253 , H01L2924/12042 , H01L2924/1432 , H01L2924/1434 , H01L2924/1461 , H01L2924/15311 , H01L2924/15787 , H01L2924/18161 , H01L2924/351 , H01L2924/00012 , H01L2224/80 , H01L2924/014 , H01L2924/00 , H01L2224/05552
摘要： Semiconductor multi-die structures having intermediate vertical side chips, and packages housing such semiconductor multi-die structures, are described. In an example, a multi-die semiconductor structure includes a first main stacked dies (MSD) structure having a first substantially horizontal arrangement of semiconductor dies. A second MSD structure having a second substantially horizontal arrangement of semiconductor dies is also included. An intermediate vertical side chip (i-VSC) is disposed between and electrically coupled to the first and second MSD structures.
摘要翻译：描述了具有中间垂直侧芯片的半导体多管芯结构以及容纳这种半导体多管芯结构的封装。在一个示例中，多管芯半导体结构包括具有半导体管芯的第一基本水平布置的第一主堆叠管芯（MSD）结构。还包括具有半导体管芯的第二基本水平布置的第二MSD结构。中间垂直侧芯片（i-VSC）设置在电耦合到第一和第二MSD结构之间。

10. 发明申请

WO2018063684A1 3D HIGH-INDUCTIVE GROUND PLANE FOR CROSSTALK REDUCTION 审中-公开
标题翻译：用于减少串扰的3D高感应接地平面
公开(公告)号：WO2018063684A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/049222
申请日：2017-08-29
申请人： INTEL CORPORATION
发明人： KONG, Jackson Chung Peng , CHEAH, Bok Eng , YONG, Khang Choong , PARTHASARATHY, Ramasmamy
IPC分类号： H05K1/02 , H05K1/16
CPC分类号： H05K1/0222 , H05K1/0219 , H05K1/0224 , H05K2201/0707 , H05K2201/09672
摘要： Embodiments are generally directed to 3D high-inductive ground plane for crosstalk reduction. An embodiment of a printed circuit board includes a first signal trace and a second signal trace on a first layer, wherein the first signal trace and second signal trace are non-intersecting; a second layer below the first layer; a third layer below the second layer; and a three-dimensional (3D) ground plane, the 3D ground plane including a first plurality of segments on the third layer, a second plurality of segments on the second layer, and a plurality of metal vias to connect the first plurality of segments and the second plurality of segments in the ground plane.
摘要翻译：实施例通常针对用于减少串扰的3D高电感接地平面。印刷电路板的实施例包括第一层上的第一信号迹线和第二信号迹线，其中第一信号迹线和第二信号迹线不相交; 在第一层下面的第二层; 在第二层下面的第三层; 和三维（3D）接地平面，所述3D接地平面包括所述第三层上的第一多个段，所述第二层上的第二多个段，以及连接所述第一多个段的多个金属通孔以及地平面中的第二多个分段。

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