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1. 发明申请

WO2013095363A1 MICROELECTRONIC PACKAGE AND STACKED MICROELECTRONIC ASSEMBLY AND COMPUTING SYSTEM CONTAINING SAME 审中-公开
标题翻译：微电子封装和堆叠的微电子组件和包含其的计算系统
公开(公告)号：WO2013095363A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/066049
申请日：2011-12-20
申请人： INTEL CORPORATION , MALATKAR, Pramod , DELANEY, Drew W. , MANEPALLI, Rahul N. , SENEVIRATNE, Dilan
发明人： MALATKAR, Pramod , DELANEY, Drew W. , MANEPALLI, Rahul N. , SENEVIRATNE, Dilan
IPC分类号： H01L23/48 , H01L23/34 , H01L25/16
CPC分类号： H01L23/48 , H01L23/49816 , H01L23/49822 , H01L23/49894 , H01L23/562 , H01L25/105 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2225/1023 , H01L2225/1058 , H01L2225/1088 , H01L2924/01327 , H01L2924/15311 , H01L2924/1815 , H01L2924/18162 , H01L2924/00
摘要： A microelectronic package comprises a die (110, 210) and a plurality of electrically conductive layers (120, 220) and electrically insulating layers (130, 230), including a first electrically insulating layer (131, 231) closer to the die than any other electrically insulating layer) and second (132, 232) and third electrically insulating layers (233). Each electrically insulating layer has a corresponding glass transition temperature, coefficient of thermal expansion, and modulus of elasticity. The modulus of elasticity of the second electrically insulating layer is greater than that for the first electrically insulating layer, while CTE 1 for the second electrically insulating layer is greater than CTE 1 for the first. CTE 2 for the third electrically insulating layer is less than CTE 2 for the first electrically insulating layer. In an embodiment an electrically insulating layer is a glass cloth layer (140) that is an outermost layer of the microelectronic package.
摘要翻译：微电子封装包括管芯（110,210）和多个导电层（120,220）和电绝缘层（130,230），其包括比任一个更靠近管芯的第一电绝缘层（131,231）其它电绝缘层）和第二（132,232）和第三电绝缘层（233）。每个电绝缘层具有相应的玻璃化转变温度，热膨胀系数和弹性模量。第二电绝缘层的弹性模量大于第一电绝缘层的弹性模量，第二电绝缘层的CTE1大于第一电绝缘层的CTE1。用于第三电绝缘层的CTE2小于第一电绝缘层的CTE2。在一个实施例中，电绝缘层是作为微电子封装的最外层的玻璃布层（140）。

2. 发明申请

WO2017091211A1 ELECTRONIC PACKAGE THAT INCLUDES LAMINATION LAYER 审中-公开
标题翻译：电子封装，包括层压层
公开(公告)号：WO2017091211A1
公开(公告)日：2017-06-01
申请号：PCT/US2015/062397
申请日：2015-11-24
申请人： MALATKAR, Pramod , YAZZIE, Kyle , YAGNAMURTHY, Naga Sivakumar , HARRIES, Richard J. , SENEVIRATNE, Dilan , AKKINEPALLY, Praneeth , WAN, Xuefei , LI, Yonggang , SANKMAN, Robert L.
发明人： MALATKAR, Pramod , YAZZIE, Kyle , YAGNAMURTHY, Naga Sivakumar , HARRIES, Richard J. , SENEVIRATNE, Dilan , AKKINEPALLY, Praneeth , WAN, Xuefei , LI, Yonggang , SANKMAN, Robert L.
IPC分类号： H01L23/48 , H01L23/34
CPC分类号： H01L23/34 , H01L23/3128 , H01L23/48 , H01L23/562 , H01L25/105 , H01L2224/16225 , H01L2224/73204 , H01L2224/81203 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H01L2924/00012 , H01L2924/00014
摘要： An electronic package that includes a substrate and an electronic component attached to the substrate. A laminated layer is attached to an upper surface of the substrate such that the laminated layer covers the electronic component. The electronic package may further include a stiffener mounted on the laminated layer where the stiffener is over the electronic component.
摘要翻译：电子封装包括基板和附着到基板的电子组件。层压层附着到基板的上表面，使得层压层覆盖电子部件。电子封装还可以包括安装在层压层上的加强件，其中加强件位于电子部件上方。

3. 发明申请

WO2009120967A2 METHOD OF MANUFACTURING A SUBSTRATE FOR A MICROELECTRONIC DEVICE, AND SUBSTRATE FORMED THEREBY 审中-公开
标题翻译：制造微电子器件用基板的方法及其形成的基板
公开(公告)号：WO2009120967A2
公开(公告)日：2009-10-01
申请号：PCT/US2009/038571
申请日：2009-03-27
申请人： INTEL CORPORATION , JOMAA, Houssam , ALUR, Amruthavalli, P. , SENEVIRATNE, Dilan
发明人： JOMAA, Houssam , ALUR, Amruthavalli, P. , SENEVIRATNE, Dilan
CPC分类号： H05K3/387 , H05K3/0032 , H05K3/0055 , H05K3/108 , H05K3/465 , H05K3/4661 , H05K2203/066 , H05K2203/1152 , H05K2203/1383 , Y10T428/24355 , Y10T428/24612
摘要： A method of manufacturing a substrate for a microelectronic device comprises providing a dielectric material (120, 220, 920) as a build-up layer of the substrate, applying a primer (140, 240, 940) to a surface (121, 221, 921) of the dielectric material, and forming an electrically conductive layer (150, 250, 950) over the primer. In another embodiment, the method comprises providing the dielectric material, forming the feature extending into the dielectric material, forming the electrically conductive layer over the dielectric material, applying the primer to a surface of the electrically conductive layer and attaching a dielectric layer (960) to the primer.
摘要翻译：一种制造用于微电子器件的衬底的方法包括提供作为衬底的堆积层的电介质材料（120,220,920），将底漆（140,240,940）施加到表面（121,221， 921），并且在引物上形成导电层（150,250,950）。在另一个实施方案中，该方法包括提供电介质材料，形成延伸到电介质材料中的特征，在电介质材料上形成导电层，将引物施加到导电层的表面，并附着电介质层（960）到底漆。

4. 发明申请

WO2006014203A1 FUNCTIONAL MATERIAL FOR MICRO-MECHANICAL SYSTEMS 审中-公开
标题翻译：微机械系统的功能材料
公开(公告)号：WO2006014203A1
公开(公告)日：2006-02-09
申请号：PCT/US2005/018913
申请日：2005-05-27
申请人： MASSACHUSETTS INSTITUTE OF TECHNOLOGY , SENEVIRATNE, Dilan , NIELSON, Gregory, N. , BARBASTATHIS, George , TULLER, Harry, L.
发明人： SENEVIRATNE, Dilan , NIELSON, Gregory, N. , BARBASTATHIS, George , TULLER, Harry, L.
IPC分类号： B81B3/00
CPC分类号： B81B3/0016 , B81B3/0024 , B81B2201/032 , G11C23/00
摘要： A MEMS device includes a first material structure. A second material structure includes TiN. The second material structure is moveable relative to the first material structure.
摘要翻译： MEMS器件包括第一材料结构。第二种材料结构包括TiN。第二材料结构可相对于第一材料结构移动。

5. 发明申请

WO2018063198A1 FLEXIBLE PACKAGING FOR A WEARABLE ELECTRONIC DEVICE 审中-公开
标题翻译：用于可佩戴电子设备的柔性包装
公开(公告)号：WO2018063198A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054240
申请日：2016-09-28
申请人： ALEKSOV, Aleksandar , NGUYEN, Son V. , GOYAL, Rajat , LAMPNER, David B. , SENEVIRATNE, Dilan , LOPEZ, Albert S. , HEPPNER, Joshua D. , PIETAMBARAM, Srinivas V. , LIFF, Shawna M. , DABBY, Nadine L.
发明人： ALEKSOV, Aleksandar , NGUYEN, Son V. , GOYAL, Rajat , LAMPNER, David B. , SENEVIRATNE, Dilan , LOPEZ, Albert S. , HEPPNER, Joshua D. , PIETAMBARAM, Srinivas V. , LIFF, Shawna M. , DABBY, Nadine L.
IPC分类号： G04G17/04 , G04B37/14 , A44C5/00 , G06F1/16
摘要： The document discloses a stretchable packaging system for a wearable electronic device. The system includes a first electronic component and a flexible trace connected to the first electronic component. An elastomer layer having a variable thickness at least partially encapsulates the first electronic component and the flexible trace. A first region of the layer has a first thickness that is greater than a second thickness of a second region of the layer that at least partially encapsulates the trace.
摘要翻译：该文献公开了用于可穿戴电子设备的可拉伸包装系统。该系统包括第一电子部件和连接到第一电子部件的柔性迹线。具有可变厚度的弹性体层至少部分地封装第一电子部件和柔性迹线。该层的第一区域具有第一厚度，该第一厚度大于至少部分地封装迹线的层的第二区域的第二厚度。

6. 发明申请

WO2017052567A1 STRETCHABLE ELECTRONIC ASSEMBLY 审中-公开
标题翻译：可扩展的电子总成
公开(公告)号：WO2017052567A1
公开(公告)日：2017-03-30
申请号：PCT/US2015/052073
申请日：2015-09-24
申请人： ALEKSOV, Aleksandar , ELSHERBINI, Adel , SOTO GONZALEZ, Javier , SENEVIRATNE, Dilan , JAYWANT, Shruti R. , KANDANUR, Sashi S. , PIETAMBARAM, Srinivas , DABBY, Nadine L. , LATHROP, Braxton , GOYAL, Rajat , RAGHUNATHAN, Vivek
发明人： ALEKSOV, Aleksandar , ELSHERBINI, Adel , SOTO GONZALEZ, Javier , SENEVIRATNE, Dilan , JAYWANT, Shruti R. , KANDANUR, Sashi S. , PIETAMBARAM, Srinivas , DABBY, Nadine L. , LATHROP, Braxton , GOYAL, Rajat , RAGHUNATHAN, Vivek
IPC分类号： H01L23/12
CPC分类号： H01L23/5387 , H01L23/145 , H05K1/0283 , H05K3/205 , H05K2201/0133 , H05K2201/09263
摘要： Some forms relate to an example stretchable electronic assembly. The stretchable electronic assembly includes a stretchable body that includes electronic components. A plurality of meandering conductors electrically connect the electronic components. The plurality of meandering conductors may be exposed from the stretchable body. A plurality of conductive pads are electrically connected to at least one of the electronic components or some of the plurality of meandering conductors. The plurality of conductive pads may be exposed from the stretchable body. The stretchable body includes an upper surface and lower surface. The plurality of meandering conductors may be exposed from the lower surface (in addition to, or alternatively to, the upper surface) of the stretchable body.
摘要翻译：一些形式涉及示例性可拉伸电子组件。可拉伸电子组件包括包括电子部件的可拉伸体。多个曲折导体电连接电子部件。多个曲折导体可以从可拉伸体露出。多个导电焊盘电连接到至少一个电子部件或多个蜿蜒导体中的一些。多个导电垫可以从可拉伸体露出。伸缩体包括上表面和下表面。多个曲折导体可以从可伸展体的下表面（除了或可替代地，上表面）暴露。

7. 发明申请

WO2014098965A1 BUMPLESS BUILD-UP LAYER PACKAGE INCLUDING A RELEASE LAYER 审中-公开
标题翻译：不包括建筑层包，包括一个释放层
公开(公告)号：WO2014098965A1
公开(公告)日：2014-06-26
申请号：PCT/US2013/044069
申请日：2013-06-04
申请人： INTEL CORPORATION
发明人： JIN, Liwen , SENEVIRATNE, Dilan
IPC分类号： H01L21/301 , H01L21/58
CPC分类号： H01L24/82 , H01L21/6835 , H01L23/49822 , H01L23/49894 , H01L23/5389 , H01L24/19 , H01L2221/68345 , H01L2224/04105 , H01L2224/73267 , H01L2224/82002 , H01L2224/82031 , H01L2224/821 , H01L2224/82375 , H01L2224/82399 , H01L2224/82862 , H05K1/185 , H05K3/4682 , H05K2203/0152
摘要： An example includes a die package including a microelectronic die having a lower die surface, an upper die surface parallel to the lower die surface, and a die side, the microelectronic die including an active region and an inactive region. The example optionally includes a release layer having a lower release layer surface, an upper release layer surface parallel to the lower release layer surface, and at least one release layer side, the release layer coupled with the upper surface of the microelectronic die in thermal communication with the inactive region of the die and electrically insulated from the active region. The example optionally includes an encapsulation material encapsulating the die side and the release layer side and lower release layer surface, the encapsulation material including a lower surface substantially parallel to the die lower surface and an upper surface substantially parallel to the die upper surface.
摘要翻译：一个实例包括包括具有下模表面的微电子管芯，平行于下模表面的上模表面和管芯侧的管芯封装，该微电子管芯包括有源区和非活性区。该实施例可选地包括具有较低释放层表面的释放层，平行于下释放层表面的上释放层表面，以及至少一个剥离层侧，该释放层与微电子管芯的上表面热连通具有裸片的非活性区域并与活性区电绝缘。该实施例可选地包括封装模具侧和剥离层侧和下剥离层表面的封装材料，该封装材料包括基本上平行于模具下表面的下表面和基本上平行于模具上表面的上表面。

8. 发明申请

WO2018182595A1 EMBEDDED DIE MICROELECTRONIC DEVICE WITH MOLDED COMPONENT 审中-公开
公开(公告)号：WO2018182595A1
公开(公告)日：2018-10-04
申请号：PCT/US2017/024780
申请日：2017-03-29
申请人： INTEL CORPORATION
发明人： PIETAMBARAM, Srinivas V. , MANEPALLI, Rahul N. , AKKINEPALLY, Praneeth , JONES, Jesse C. , KANAOKA, Yosuke , SENEVIRATNE, Dilan
IPC分类号： H01L23/31 , H01L21/56 , H01L21/67
摘要： Described are microelectronic devices including an embedded die substrate including a molded component formed on or over a surface of a laminated substrate that provides a planar outer surface independent of the contour of the adjacent laminated substrate surface. The molded component may be formed over at least a portion of the embedded die. In other examples, the molded component and resulting planar outer surface may alternatively be on the backside of the substrate, away from the embedded die. The molded component may include an epoxy mold compound; and may be formed through processes including compression molding and transfer molding.

9. 发明申请

WO2018169543A1 DIELECTRIC FILM WITH PRESSURE SENSITIVE MICROCAPSULES OF ADHESION PROMOTER 审中-公开
公开(公告)号：WO2018169543A1
公开(公告)日：2018-09-20
申请号：PCT/US2017/022898
申请日：2017-03-17
申请人： INTEL CORPORATION
发明人： AKKINEPALLY, Praneeth , TRUONG, Frank , SENEVIRATNE, Dilan
IPC分类号： C09J7/02 , B32B15/09 , B32B15/20 , B32B7/12
摘要： Embodiments are generally directed to dielectric film with pressure sensitive microcapsules of adhesion promoter. An embodiment of an apparatus includes a dielectric film, the dielectric film including a dielectric material layer; a layer of pressure sensitive microcapsules on a first side of the dielectric material layer, the microcapsules including an adhesion promoter; and a cover material on the layer of microcapsules. The pressure sensitive microcapsules are to rupture upon application of a certain rupture pressure.

10. 发明申请

WO2018013311A1 PACKAGE WITH PASSIVATED INTERCONNECTS 审中-公开
标题翻译：包装与被钝化的相互连接
公开(公告)号：WO2018013311A1
公开(公告)日：2018-01-18
申请号：PCT/US2017/038656
申请日：2017-06-22
申请人： INTEL CORPORATION
发明人： BOYAPATI, Sri Ranga Sai , MANEPALLI, Rahul N. , SENEVIRATNE, Dilan , PIETAMBARAM, Srinivas V. , DARMAWIKARTA, Kristof , MAY, Robert Alan , SALAMA, Islam A.
IPC分类号： H01L23/485 , H01L23/48 , H01L23/31 , H01L25/065
摘要： The passivation layer may be any suitable dielectric material that may overlie a build-up dielectric layer and metal traces of an interconnect layer in a semiconductor package. Via holes may be formed in the build-up dielectric and the passivation layer may be removed from the bottom of the via hole. By removing the passivation layer at the bottom of the via hole, any residual build-up dielectric may also be removed from the bottom of the via hole. Thus removal of the residual build-up dielectric may not require a desmear process that would otherwise roughen metal and/or dielectric surfaces. The resulting smoother metal and/or dielectric surfaces enabled by the use of the passivation layer may allow greater process latitude and/or flexibility to fabricate relatively smaller dimensional interconnect features and/or relatively improved signaling frequency and integrity.
摘要翻译：钝化层可以是可以覆盖半导体封装中的互连层的构建介电层和金属迹线的任何合适的介电材料。可以在增层介质中形成通孔，并且可以从通孔的底部去除钝化层。通过去除通孔底部的钝化层，还可以从通孔底部去除任何残留的积累电介质。因此去除残余积层电介质可能不需要否则会使金属和/或电介质表面变粗糙的去污处理。通过使用钝化层实现的更平滑的金属和/或电介质表面可以允许更大的工艺宽容度和/或灵活性来制造相对较小的尺寸互连特征和/或相对提高的信号频率和完整性。

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