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1. 发明申请

WO2017105388A1 SUBSTRATE INTEGRATED WAVEGUIDE 审中-公开
标题翻译：基片集成波导
公开(公告)号：WO2017105388A1
公开(公告)日：2017-06-22
申请号：PCT/US2015/065511
申请日：2015-12-14
申请人： INTEL CORPORATION
发明人： MAY, Robert Alan , DARMAWIKARTA, Kristof , JAIN, Rahul , BOYAPATI, Sri Ranga Sai , MOUSSALLEM, Maroun , MANEPALLI, Rahul N. , PIETAMBARAM, Srinivas
IPC分类号： G02B6/132
CPC分类号： G02B6/122 , G02B6/132 , G02B6/134
摘要： This document discusses, among other things, a waveguide including a first metal having an outer surface proximate a dielectric material and an inner surface defining a path of the waveguide, a method of receiving an optical signal at the inner surface of the waveguide and transmitting the optical signal along at least a portion of the path of the waveguide. A method of integrating a waveguide in a substrate includes depositing sacrificial metal on a first surface of a carrier substrate to form a core of the waveguide, depositing a first metal over the sacrificial metal and at least a portion of the first surface of the carrier substrate, forming an outer surface of the waveguide and a conductor separate from the sacrificial metal, and depositing dielectric material over the first surface of the carrier substrate about the conductor.
摘要翻译：该文献尤其讨论了一种波导，该波导包括第一金属和第二金属，该第一金属具有接近介电材料的外表面和限定波导的路径的内表面，在该接收器处接收光信号的方法所述波导的内表面并且沿着所述波导的所述路径的至少一部分传输所述光信号。一种将波导集成在衬底中的方法包括在载体衬底的第一表面上沉积牺牲金属以形成波导的核心，在牺牲金属上沉积第一金属以及载体衬底的第一表面的至少一部分，形成波导的外表面和与牺牲金属分开的导体，并且在载体衬底的第一表面上围绕导体沉积介电材料。

2. 发明申请

WO2018182652A1 SEMICONDUCTOR PACKAGE HAVING A COAXIAL FIRST LAYER INTERCONNECT 审中-公开
公开(公告)号：WO2018182652A1
公开(公告)日：2018-10-04
申请号：PCT/US2017/025199
申请日：2017-03-30
申请人： INTEL CORPORATION
发明人： VADLAMANI, Sai , ALEKSOV, Aleksandar , JAIN, Rahul , LEE, Kyu Oh , DARMAWIKARTA, Kristof Kuwawi , MAY, Robert Alan , BOYAPATI, Sri Ranga Sai , KAMGAING, Telesphor
IPC分类号： H01L23/00 , H01L23/522
摘要： Semiconductor packages having a first layer interconnect portion that includes a coaxial interconnect between a die and a package substrate are described. In an example, the package substrate includes a substrate-side coaxial interconnect electrically connected to a signal line. The die is mounted on the package substrate and includes a die-side coaxial interconnect coupled to the substrate-side coaxial interconnect. The coaxial interconnects can be joined by a solder bond between respective central conductors and shield conductors.

3. 发明申请

WO2018182654A1 PACKAGE SUBSTRATE HAVING POLYMER-DERIVED CERAMIC CORE 审中-公开
公开(公告)号：WO2018182654A1
公开(公告)日：2018-10-04
申请号：PCT/US2017/025201
申请日：2017-03-30
申请人： INTEL CORPORATION
发明人： CHEN, Lisa Ying Ying , LINK, Lauren Ashley , MAY, Robert Alan , ALUR, Amruthavalli Pallavi , DARMAWIKARTA, Kristof Kuwawi , ALUR, Siddharth K. , BOYAPATI, Sri Ranga Sai , BROWN, Andrew James , MAY, Lilia
IPC分类号： H01L23/373 , H01L23/12 , H01L23/48
摘要： Semiconductor packages including package substrates having polymer-derived ceramic cores are described. In an example, a package substrate includes a core layer including a polymer-derived ceramic. The polymer-derived ceramic may include filler particles to control shrinkage and reduce warpage of the core layer during fabrication and use of the package substrate. The core layer may include counterbores or blind holes to embed a contact pad or an electrical interconnect in the core layer. A semiconductor die may be mounted on the package substrate and may be electrically connected to the contact pad or the electrical interconnect.

4. 发明申请

WO2018182653A1 RFIC HAVING COAXIAL INTERCONNECT AND MOLDED LAYER 审中-公开
公开(公告)号：WO2018182653A1
公开(公告)日：2018-10-04
申请号：PCT/US2017/025200
申请日：2017-03-30
申请人： INTEL CORPORATION
发明人： PIETAMBARAM, Srinivas V. , MANEPALLI, Rahul N. , DARMAWIKARTA, Kristof Kuwawi , MAY, Robert Alan , ALEKSOV, Aleksandar , KAMGAING, Telesphor
IPC分类号： H01L23/66 , H01L23/522 , H01L23/485 , H01L23/00
摘要： Semiconductor packages having a die electrically connected to an antenna by a coaxial interconnect are described. In an example, a semiconductor package includes a molded layer between a first antenna patch and a second antenna patch of the antenna. The first patch may be electrically connected to the coaxial interconnect, and the second patch may be mounted on the molded layer. The molded layer may be formed from a molding compound, and may have a stiffness to resist warpage during fabrication and use of the semiconductor package.

5. 发明申请

WO2018125184A1 PACKAGE SUBSTRATE WITH HIGH-DENSITY INTERCONNECT LAYER HAVING PILLAR AND VIA CONNECTIONS FOR FAN OUT SCALING 审中-公开
公开(公告)号：WO2018125184A1
公开(公告)日：2018-07-05
申请号：PCT/US2016/069377
申请日：2016-12-30
申请人： INTEL CORPORATION
发明人： MAY, Robert Alan , BOYAPATI, Sri Ranga Sai , DARMAWIKARTA, Kristof Kuwawi , PIETAMBARAM, Srinivas V. , SOTO GONZALEZ, Javier , LIM, Kwangmo Chris , ALEKSOV, Aleksandar
IPC分类号： H01L23/498 , H01L23/00 , H01L23/522 , H01L23/538 , H01L23/525
摘要： Integrated circuit package substrates with high-density interconnect architecture for scaling high-density routing, as well as related structures, devices, and methods, are generally presented. More specifically, integrated circuit package substrates with fan out routing based on a high-density interconnect layer that may include pillars and vias, and integrated cavities for die attachment are presented. Additionally, integrated circuit package substrates with self-aligned pillars and vias formed on the high-density interconnect layer as well as related methods are presented.

6. 发明申请

WO2017204789A1 PACKAGE SUBSTRATES WITH INTEGRAL DEVICES 审中-公开
标题翻译：包装基板与整体设备
公开(公告)号：WO2017204789A1
公开(公告)日：2017-11-30
申请号：PCT/US2016/034016
申请日：2016-05-25
申请人： INTEL CORPORATION
发明人： MAY, Robert Alan , DARMAWIKARTA, Kristof Kuwawi , BOYAPATI, Sri Ranga Sai
IPC分类号： H01L23/538 , H01L23/522 , H01L23/525 , H01L23/498
CPC分类号： H01L23/5389 , H01L21/4846 , H01L23/498 , H01L23/49822 , H01L23/49838 , H01L23/522 , H01L23/525 , H01L23/538 , H01L23/5384 , H01L27/1218 , H01L28/60 , H01L29/786 , H01L2224/16225 , H01L2924/15192 , H01L2924/15311
摘要： Disclosed herein are package substrates with integrated components, as well as related apparatuses and methods. For example, in some embodiments, an integrated circuit (IC) package, may include: a substrate having opposing first and second faces, an insulating material disposed between the first and second faces, and a thin film transistor (TFT) disposed between the first and second faces, wherein a conductive portion of the TFT is disposed on a layer of the insulating material, and the conductive portion of the TFT is a gate, source, or drain of the TFT; and a die coupled to the first face of the substrate.
摘要翻译：这里公开了具有集成组件的封装基板以及相关的装置和方法。例如，在一些实施例中，集成电路（IC）封装可以包括：具有相对的第一和第二面的基板，设置在第一和第二面之间的绝缘材料以及设置在第一和第二面之间的薄膜晶体管（TFT）所述薄膜晶体管的导电部分设置在所述绝缘材料层上，所述薄膜晶体管的导电部分为所述薄膜晶体管的栅极，源极或漏极; 以及耦合到基板的第一面的管芯。

7. 发明申请

WO2017160459A1 PLASMA ETCHING OF SOLDER RESIST OPENINGS 审中-公开
标题翻译：等离子刻蚀抗焊剂开口
公开(公告)号：WO2017160459A1
公开(公告)日：2017-09-21
申请号：PCT/US2017/018195
申请日：2017-02-16
申请人： INTEL CORPORATION
发明人： DARMAWIKARTA, Kristof , JAIN, Rahul , MAY, Robert Alan , LI, Sheng , BOYAPATI, Sri Ranga Sai
IPC分类号： H01L21/3065 , H01L21/027 , H01L21/3213 , H01L21/225
CPC分类号： H05K3/0041 , H05K1/0313 , H05K1/09 , H05K3/0055 , H05K3/3452 , H05K2203/0502 , H05K2203/0548 , H05K2203/0562 , H05K2203/0588 , H05K2203/095
摘要： A method of forming an electronic assembly. The method includes covering a patterned conductive layer that is on a dielectric layer with a solder resist; depositing a metal layer on to the solder resist; depositing a photo resist onto the metal layer; patterning the photo resist; etching the metal layer that is exposed from the photo resist to form a metal mask; removing the photo resist; and plasma etching the solder resist that is exposed from the metal mask. An electronic assembly for securing for an electronic card. The electronic assembly includes a patterned conductive layer that is on a dielectric layer; and a solder resist covering the patterned conductive layer and the dielectric layer, wherein the solder resist includes openings that expose the patterned conductive layer, wherein the openings in the solder resist only have organic material on side walls of the respective openings.
摘要翻译：
一种形成电子组件的方法。该方法包括用阻焊剂覆盖介电层上的图案化导电层; 在所述阻焊剂上沉积金属层; 在所述金属层上沉积光刻胶; 构图光刻胶; 蚀刻从光致抗蚀剂暴露的金属层以形成金属掩模; 去除光刻胶; 并等离子蚀刻从金属掩模暴露的阻焊层。用于电子卡安全保护的电子组件。该电子组件包括位于电介质层上的图案化导电层; 以及覆盖图案化导电层和介电层的阻焊剂，其中阻焊剂包括暴露图案化导电层的开口，其中阻焊剂中的开口仅在各个开口的侧壁上具有有机材料。

8. 发明申请

WO2019132992A1 PATCH ACCOMODATING EMBEDDED DIES HAVING DIFFERENT THICKNESSES 审中-公开
公开(公告)号：WO2019132992A1
公开(公告)日：2019-07-04
申请号：PCT/US2017/069060
申请日：2017-12-29
申请人： INTEL CORPORATION
发明人： PIETAMBARAM, Srinivas , MAY, Robert Alan , DARMAWIKARTA, Kristof , TANAKA, Hiroki , MANEPALLI, Rahul N. , BOYAPATI, Sri Ranga Sai
IPC分类号： H01L25/07 , H01L25/065 , H01L23/538 , H01L23/498 , H01L23/485
摘要： Techniques for a patch to couple one or more surface dies to an interposer or motherboard are provided. In an example, the patch can include multiple embedded dies. In an example, a microelectronic device can be formed to include a patch on an interposer, where the patch can include multiple embedded dies and each die can have a different thickness.

9. 发明申请

WO2018182597A1 MICROELECTRONIC DEVICE WITH EMBEDDED DIE SUBSTRATE ON INTERPOSER 审中-公开
公开(公告)号：WO2018182597A1
公开(公告)日：2018-10-04
申请号：PCT/US2017/024795
申请日：2017-03-29
申请人： INTEL CORPORATION , MAY, Robert Alan , SALAMA, Islam A. , BOYAPATI, Sri Ranga Sai , LI, Sheng , DARMAWIKARTA, Kristof , SANKMAN, Robert L. , ALUR, Amruthavalli Pallavi
发明人： MAY, Robert Alan , SALAMA, Islam A. , BOYAPATI, Sri Ranga Sai , LI, Sheng , DARMAWIKARTA, Kristof , SANKMAN, Robert L. , ALUR, Amruthavalli Pallavi
IPC分类号： H01L25/065 , H01L23/00 , H01L25/07
摘要： A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die.

10. 发明申请

WO2018013311A1 PACKAGE WITH PASSIVATED INTERCONNECTS 审中-公开
标题翻译：包装与被钝化的相互连接
公开(公告)号：WO2018013311A1
公开(公告)日：2018-01-18
申请号：PCT/US2017/038656
申请日：2017-06-22
申请人： INTEL CORPORATION
发明人： BOYAPATI, Sri Ranga Sai , MANEPALLI, Rahul N. , SENEVIRATNE, Dilan , PIETAMBARAM, Srinivas V. , DARMAWIKARTA, Kristof , MAY, Robert Alan , SALAMA, Islam A.
IPC分类号： H01L23/485 , H01L23/48 , H01L23/31 , H01L25/065
摘要： The passivation layer may be any suitable dielectric material that may overlie a build-up dielectric layer and metal traces of an interconnect layer in a semiconductor package. Via holes may be formed in the build-up dielectric and the passivation layer may be removed from the bottom of the via hole. By removing the passivation layer at the bottom of the via hole, any residual build-up dielectric may also be removed from the bottom of the via hole. Thus removal of the residual build-up dielectric may not require a desmear process that would otherwise roughen metal and/or dielectric surfaces. The resulting smoother metal and/or dielectric surfaces enabled by the use of the passivation layer may allow greater process latitude and/or flexibility to fabricate relatively smaller dimensional interconnect features and/or relatively improved signaling frequency and integrity.
摘要翻译：钝化层可以是可以覆盖半导体封装中的互连层的构建介电层和金属迹线的任何合适的介电材料。可以在增层介质中形成通孔，并且可以从通孔的底部去除钝化层。通过去除通孔底部的钝化层，还可以从通孔底部去除任何残留的积累电介质。因此去除残余积层电介质可能不需要否则会使金属和/或电介质表面变粗糙的去污处理。通过使用钝化层实现的更平滑的金属和/或电介质表面可以允许更大的工艺宽容度和/或灵活性来制造相对较小的尺寸互连特征和/或相对提高的信号频率和完整性。

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