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1. 发明申请

WO2012040075A3 NON-PLANAR DEVICE HAVING UNIAXIALLY STRAINED FIN AND METHOD OF MAKING SAME 审中-公开
标题翻译：具有非均匀应变FIN的非平面设备及其制造方法
公开(公告)号：WO2012040075A3
公开(公告)日：2012-06-07
申请号：PCT/US2011052084
申请日：2011-09-19
申请人： INTEL CORP , CEA STEPHEN M , KOTLYAR ROZA , KAVALIEROS JACK T , GILES MARTIN D , GHANI TAHIR , KUHN KELIN J , KUHN MARKUS , ZELICK NANCY M
发明人： CEA STEPHEN M , KOTLYAR ROZA , KAVALIEROS JACK T , GILES MARTIN D , GHANI TAHIR , KUHN KELIN J , KUHN MARKUS , ZELICK NANCY M
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L29/1054 , H01L29/66795 , H01L29/7849 , H01L29/785
摘要： A method and a device made according to the method. The method comprises providing a substrate including a first material, and providing a fin including a second material, the fin being disposed on the substrate and having a device active portion, the first material and the second material presenting a lattice mismatch between respective crystalline structures thereof. Providing the fin includes providing a biaxially strained film including the second material on the substrate; and removing parts of the biaxially strained film to form a substantially uniaxially strained fin therefrom.
摘要翻译：根据该方法制造的方法和装置。该方法包括提供包括第一材料的基底，并且提供包括第二材料的翅片，所述翅片设置在所述基底上并且具有器件活性部分，所述第一材料和所述第二材料在其各自的结晶结构之间呈现晶格失配。提供散热片包括在基板上提供包括第二材料的双轴应变膜; 并除去双轴应变膜的部分以形成基本上单轴应变的翅片。

2. 发明申请

WO2012087581A3 TRANSISTORS WITH HIGH CONCENTRATION OF BORON DOPED GERMANIUM 审中-公开
标题翻译：高浓度硼掺杂锗的晶体管
公开(公告)号：WO2012087581A3
公开(公告)日：2012-09-07
申请号：PCT/US2011063813
申请日：2011-12-07
申请人： INTEL CORP , MURTHY ANAND S , GLASS GLENN A , GHANI TAHIR , PILLARISETTY RAVI , MUKHERJEE NILOY , KAVALIEROS JACK T , KOTLYAR ROZA , RACHMADY WILLY , LIU MARK Y
发明人： MURTHY ANAND S , GLASS GLENN A , GHANI TAHIR , PILLARISETTY RAVI , MUKHERJEE NILOY , KAVALIEROS JACK T , KOTLYAR ROZA , RACHMADY WILLY , LIU MARK Y
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0676 , H01L21/02532 , H01L21/28512 , H01L21/28525 , H01L21/3215 , H01L21/76831 , H01L23/535 , H01L27/092 , H01L27/0924 , H01L29/0615 , H01L29/0847 , H01L29/086 , H01L29/165 , H01L29/167 , H01L29/36 , H01L29/41791 , H01L29/42392 , H01L29/45 , H01L29/456 , H01L29/4966 , H01L29/66477 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66681 , H01L29/66931 , H01L29/7785 , H01L29/78 , H01L29/7816 , H01L29/7833 , H01L29/7848 , H01L29/785 , H01L29/7851
摘要： Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm-3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.
摘要翻译：公开了用于形成具有高浓度硼掺杂锗的源区和漏区的晶体管器件的技术。在一些实施例中，使用选择性外延沉积在源极和漏极区域及其相应的尖端区域中提供原位硼掺杂的锗或替代地掺杂有重硼掺杂的锗层的硼掺杂硅锗。在一些这样的情况下，锗浓度可以例如超过50原子％并且高达100原子％，并且硼浓度可以例如超过1E20cm-3。提供分级锗和/或硼浓度的缓冲液可用于更好地连接不同层。在外延金属界面处掺杂在锗中的硼的浓度有效地降低了寄生电阻而不降低尖端陡峭性。该技术可以例如在平面或非平面晶体管器件中体现。

3. 发明申请

WO2009079159A2 SYSTEMS AND METHODS TO INCREASE UNIAXIAL COMPRESSIVE STRESS IN TRI-GATE TRANSISTORS 审中-公开
标题翻译：用于增加三栅极晶体管中的单轴压缩应力的系统和方法
公开(公告)号：WO2009079159A2
公开(公告)日：2009-06-25
申请号：PCT/US2008084344
申请日：2008-11-21
申请人： INTEL CORP , RAKSHIT TITASH , GILES MARTIN D , GHANI TAHIR , MURTHY ANAND , CEA STEPHEN M
发明人： RAKSHIT TITASH , GILES MARTIN D , GHANI TAHIR , MURTHY ANAND , CEA STEPHEN M
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L21/823437 , H01L21/26506 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： A transistor structure that increases uniaxial compressive stress on the channel region of a tri-gate transistor comprises at least two semiconductor bodies formed on a substrate, each semiconductor body having a pair of laterally opposite sidewalls and a top surface, a common source region formed on one end of the semiconductor bodies, wherein the common source region is coupled to all of the at least two semiconductor bodies, a common drain region formed on another end of the semiconductor bodies, wherein the common drain region is coupled to all of the at least two semiconductor bodies, and a common gate electrode formed over the at least two semiconductor bodies, wherein the common gate electrode provides a gate electrode for each of the at least two semiconductor bodies and wherein the common gate electrode has a pair of laterally opposite sidewalls that are substantially perpendicular to the sidewalls of the semiconductor bodies.
摘要翻译：一种增加三栅极晶体管的沟道区上的单轴压缩应力的晶体管结构包括至少两个形成在衬底上的半导体本体，每个半导体本体具有一对横向相对的侧壁和顶表面，形成在其上的公共源极区半导体本体的一端，其中公共源极区域耦合到所有至少两个半导体本体;公共漏极区域，形成在半导体本体的另一端上，其中公共漏极区域耦合到所有的至少一个两个半导体本体以及形成在所述至少两个半导体本体上方的公共栅电极，其中所述公共栅电极为所述至少两个半导体本体中的每一个提供栅电极，并且其中所述公共栅电极具有一对横向相对的侧壁，基本垂直于半导体本体的侧壁。

4. 发明申请

WO2011075257A3 SPIN TORQUE MAGNETIC INTEGRATED CIRCUITS AND DEVICES THEREFOR 审中-公开
标题翻译：自旋转矩磁集成电路及其装置
公开(公告)号：WO2011075257A3
公开(公告)日：2011-09-29
申请号：PCT/US2010056735
申请日：2010-11-15
申请人： INTEL CORP , NIKONOV DMITRI E , BOURIANOFF GEORGE I , GHANI TAHIR
发明人： NIKONOV DMITRI E , BOURIANOFF GEORGE I , GHANI TAHIR
IPC分类号： G11C11/15 , G11C11/16
CPC分类号： H01L43/08 , B82Y25/00 , B82Y40/00 , G01R33/093 , G01R33/1284 , G11C11/161 , H01F10/133 , H01F10/3254 , H01F10/329 , H01F41/307 , H01L27/22 , H01L27/228 , H01L43/12
摘要： Spin torque magnetic integrated circuits and devices therefor are described. A spin torque magnetic integrated circuit includes a first free ferromagnetic layer disposed above a substrate. A non-magnetic layer is disposed above the first free ferromagnetic layer. A plurality of write pillars and a plurality of read pillars are included, each pillar disposed above the non-magnetic layer and including a fixed ferromagnetic layer.
摘要翻译：描述自旋转矩磁集成电路及其器件。自旋扭矩磁集成电路包括设置在衬底上方的第一自由铁磁层。非磁性层设置在第一自由铁磁层上方。包括多个写入柱和多个读取柱，每个柱布置在非磁性层上方并且包括固定铁磁层。

5. 发明申请

WO2011090571A3 SELF-ALIGNED CONTACTS 审中-公开
标题翻译：自我对准的联系人
公开(公告)号：WO2011090571A3
公开(公告)日：2011-11-17
申请号：PCT/US2010059302
申请日：2010-12-07
申请人： INTEL CORP , BOHR MARK T , GHANI TAHIR , RAHHAL-ORABI NADIA M , JOSHI SUBHASH , STEIGERWALD JOSEPH M , KLAUS JASON W , HWANG JACK , MACKIEWICZ RYAN
发明人： BOHR MARK T , GHANI TAHIR , RAHHAL-ORABI NADIA M , JOSHI SUBHASH , STEIGERWALD JOSEPH M , KLAUS JASON W , HWANG JACK , MACKIEWICZ RYAN
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336
CPC分类号： H01L21/76897 , H01L21/28123 , H01L21/28229 , H01L21/28255 , H01L21/283 , H01L21/28562 , H01L21/31105 , H01L21/76802 , H01L21/76831 , H01L21/76849 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L23/535 , H01L29/0847 , H01L29/16 , H01L29/42364 , H01L29/456 , H01L29/495 , H01L29/4966 , H01L29/512 , H01L29/517 , H01L29/518 , H01L29/66477 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/78 , H01L29/785 , H01L2029/7858 , H01L2924/0002 , H01L2924/00
摘要： A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.
摘要翻译：一种晶体管，包括：衬底;衬底上的一对间隔物;衬底上以及所述一对间隔物之间的栅极电介质层;栅极电介质层上以及所述一对间隔物之间的栅极电极层; 栅电极层之间以及所述一对间隔物之间，以及与所述一对间隔物相邻的一对扩散区。绝缘盖层形成与栅极自对准的蚀刻停止结构，并防止接触蚀刻暴露栅电极，从而防止栅极与接触之间的短路。绝缘体覆盖层能够实现自对准接触，允许初始构图更宽的接触，这对于图案化限制更加稳健。

6. 发明申请

WO2012087660A2 SEMICONDUCTOR DEVICE CONTACTS 审中-公开
标题翻译：半导体器件联系人
公开(公告)号：WO2012087660A2
公开(公告)日：2012-06-28
申请号：PCT/US2011064604
申请日：2011-12-13
申请人： INTEL CORP , HAVERTY MICHAEL G , SHANKAR SADASIVAN , GHANI TAHIR , PARK SEONGJUN
发明人： HAVERTY MICHAEL G , SHANKAR SADASIVAN , GHANI TAHIR , PARK SEONGJUN
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/41791 , H01L21/283 , H01L21/3205 , H01L23/482 , H01L23/485 , H01L29/0895 , H01L29/456 , H01L29/7851 , H01L2924/0002 , H01L2924/00
摘要： Techniques are disclosed for forming contacts in silicon semiconductor devices. In some embodiments, a transition layer forms a non-reactive interface with the silicon semiconductor contact surface. In some such cases, a conductive material provides the contacts and the material forming a non-reactive interface with the silicon surface. In other cases, a thin semiconducting or insulting layer provides the non-reactive interface with the silicon surface and is coupled to conductive material of the contacts. The techniques can be embodied, for instance, in planar or non-planar (e.g., double-gate and tri-gate FinFETs) transistor devices.
摘要翻译：公开了用于在硅半导体器件中形成接触的技术。在一些实施例中，过渡层与硅半导体接触表面形成非反应性界面。在一些这种情况下，导电材料提供触点和与硅表面形成非反应性界面的材料。在其他情况下，薄的半导体或绝缘层提供与硅表面的非反应性界面并且耦合到触点的导电材料。这些技术可以例如在平面或非平面（例如，双栅极和三栅极FinFET））晶体管器件中实现。

7. 发明申请

WO2011084262A3 SEMICONDUCTOR DEVICE HAVING DOPED EPITAXIAL REGION AND ITS METHODS OF FABRICATION 审中-公开
标题翻译：具有垄断外来地区的半导体器件及其制造方法
公开(公告)号：WO2011084262A3
公开(公告)日：2011-09-09
申请号：PCT/US2010058199
申请日：2010-11-29
申请人： INTEL CORP , MURTHY ANAND S , AUBERTINE DANIEL BOURNE , GHANI TAHIR , PETHE ABHIJIT JAYANT
发明人： MURTHY ANAND S , AUBERTINE DANIEL BOURNE , GHANI TAHIR , PETHE ABHIJIT JAYANT
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/7834 , H01L21/02057 , H01L21/02381 , H01L21/0243 , H01L21/02529 , H01L21/02532 , H01L21/02576 , H01L21/0262 , H01L21/02636 , H01L21/28079 , H01L29/0847 , H01L29/165 , H01L29/495 , H01L29/66545 , H01L29/66636 , H01L29/66795 , H01L29/78 , H01L29/7848 , H01L29/785 , H01L29/7853
摘要： Embodiments of the present invention describe a epitaxial region on a semiconductor device. In one embodiment, the epitaxial region is deposited onto a substrate via cyclical deposition-etch process. Cavities created underneath the spacer during the cyclical deposition-etch process are backfilled by an epitaxial cap layer. The epitaxial region and epitaxial cap layer improves electron mobility at the channel region, reduces short channel effects and decreases parasitic resistance.
摘要翻译：本发明的实施例描述了半导体器件上的外延区域。在一个实施例中，通过循环沉积蚀刻工艺将外延区域沉积到衬底上。在循环沉积 - 蚀刻工艺期间在间隔物下方产生的腔被外延盖层回填。外延区和外延盖层改善沟道区的电子迁移率，减少短沟道效应并降低寄生电阻。

8. 发明申请

WO9829897A3 WELL BOOSTING THRESHOLD VOLTAGE ROLLUP 审中-公开
标题翻译：良好的升压阈值电压滚动
公开(公告)号：WO9829897A3
公开(公告)日：1998-09-11
申请号：PCT/US9722400
申请日：1997-12-08
申请人： INTEL CORP
发明人： THOMPSON SCOTT E , PACKAN PAUL A , GHANI TAHIR , STETTLER MARK , AHMED SHAHRIAR S , BOHR MARK T
IPC分类号： H01L21/265 , H01L21/336 , H01L29/10 , H01L
CPC分类号： H01L29/66492 , H01L21/26586 , H01L29/1045 , H01L29/1083 , H01L29/66537 , H01L29/6659
摘要： An improved well boosting implant which provides better characteristics than traditional halo implants particularly for short channel devices (e.g., 0,25 microns or less). In effect, an implant is distributed across the entire channel with higher concentrations occurring in the center of the channel of the devices having gate lengths less than the critical dimension. This is done by using very large tilt angles (e.g., 30-50 DEG ) with a relatively light dopant species and by using a relatively high energy when compared to the traditional halo implants. 00000
摘要翻译：改进的促进良好的植入物，特别是对于短通道装置（例如，0.25微米或更小），提供比传统的晕轮植入物更好的特性。实际上，植入物分布在整个通道上，较高的浓度出现在栅极长度小于临界尺寸的器件的通道的中心。这通过使用具有相对较轻的掺杂物质的非常大的倾斜角（例如，30-50°）和与传统的晕轮植入物相比使用相当高的能量来完成。 00000

9. 发明申请

WO2014051728A3 STRAINED GATE-ALL-AROUND SEMICONDUCTOR DEVICES FORMED ON GLOBALLY OR LOCALLY ISOLATED SUBSTRATES 审中-公开
标题翻译：在全球或局部隔离基板上形成的应变栅极全能型半导体器件
公开(公告)号：WO2014051728A3
公开(公告)日：2014-09-12
申请号：PCT/US2013045217
申请日：2013-06-11
申请人： INTEL CORP
发明人： CAPPELLANI ANNALISA , PETHE ABHIJIT JAYANT , GHANI TAHIR , GOMEZ HARRY , KIM SEIYON
IPC分类号： H01L29/78 , H01L21/20
CPC分类号： H01L29/42392 , B82Y10/00 , H01L21/30604 , H01L21/845 , H01L29/0649 , H01L29/0673 , H01L29/0847 , H01L29/401 , H01L29/41725 , H01L29/42356 , H01L29/66439 , H01L29/66545 , H01L29/775 , H01L29/7848 , H01L29/785 , H01L29/78696
摘要： Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional channel region is disposed above the insulating structure. Source and drain regions are disposed on either side of the three-dimensional channel region and on an epitaxial seed layer. The epitaxial seed layer is composed of a semiconductor material different from the three-dimensional channel region and disposed on the insulating structure. A gate electrode stack surrounds the three-dimensional channel region with a portion disposed on the insulating structure and laterally adjacent to the epitaxial seed layer.
摘要翻译：描述了在全局或局部隔离衬底上形成的应变全栅半导体器件。例如，半导体器件包括半导体衬底。绝缘结构设置在半导体衬底上方。三维沟道区域设置在绝缘结构上方。源极和漏极区域设置在三维沟道区域的任一侧上以及外延籽晶层上。外延籽晶层由与三维沟道区不同的半导体材料构成，并设置在绝缘结构上。栅电极叠层围绕三维沟道区，其中一部分设置在绝缘结构上并且横向邻近外延籽晶层。

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