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1. 发明申请

WO02069345A2 METHOD FOR PRODUCTION OF A MEMORY CAPACITOR 审中-公开
标题翻译：用于生产存储器用电容器
公开(公告)号：WO02069345A2
公开(公告)日：2002-09-06
申请号：PCT/DE0200436
申请日：2002-02-06
申请人： INFINEON TECHNOLOGIES AG , SELL BERNHARD , SAENGER ANNETTE , SCHUMANN DIRK
发明人： SELL BERNHARD , SAENGER ANNETTE , SCHUMANN DIRK
IPC分类号： H01L21/02 , H01L21/285 , H01L21/316 , H01L21/8242 , H01L27/108 , G11C15/00
CPC分类号： H01L27/10861 , H01L21/28518 , H01L21/31604 , H01L27/10814 , H01L28/60
摘要： The invention relates to a novel method for production of a memory capacitor, embodied as a trench or laminar condenser and is used, in particular, in a DRAM memory cell. Said method comprises the following steps: a lower metallic condenser electrode (13), a storage dielectric (14) and an upper condenser electrode (15) are formed, whereby the lower metallic condenser electrode (13) is formed in a self-justified manner on a silicon base material (1), then a free silicon region is formed in those positions where the lower condenser electrode is to be formed and then metal silicide (13) is formed selectively on the free silicon.
摘要翻译：本发明涉及一种用于存储电容器，其被设计为沟槽或叠层电容器，特别是用于在DRAM的存储单元的制备的新方法。本发明方法包括在上一个硅基底材料的自对准的方式形成下金属电容器电极（13），存储介质（14）和上电容器电极（15），所述下部金属电容器电极（13）的步骤（1）形成是，首先在在该下电容器电极是该位置的所有暴露的硅区中形成，产生，然后施加到金属硅化物（13）的暴露的硅区域上选择性地形成。

2. 发明申请

WO02069375A3 TRENCH CONDENSER AND METHOD FOR PRODUCTION THEREOF 审中-公开
标题翻译：抓斗电容器及其制造方法
公开(公告)号：WO02069375A3
公开(公告)日：2003-03-13
申请号：PCT/DE0200515
申请日：2002-02-13
申请人： INFINEON TECHNOLOGIES AG , SELL BERNHARD , SAENGER ANNETTE , SCHUMANN DIRK
发明人： SELL BERNHARD , SAENGER ANNETTE , SCHUMANN DIRK
IPC分类号： H01L21/8242 , H01L27/12
CPC分类号： H01L27/10861 , H01L27/1203
摘要： The invention relates to a trench condenser for use in a DRAM memory cell and a method for production of said trench condenser. Said trench condenser comprises a lower condenser electrode (10), a memory dielectric (12) and an upper condenser electrode (18), at least partly arranged in a trench (5), whereby the lower condenser electrode (10) lies adjacent to a wall of the trench in the lower region of the trench, whilst in the upper region of the trench, a spacer layer (9), made from an insulating material, is provided adjacent to the wall of the trench. The upper electrode (18) comprises at least two layers (13, 14, 15), of which at least one is metallic, with the proviso that the upper electrode does not comprise two layers of which the lower is tungsten silicide and the upper doped polymeric silicon, whereby the layers (13, 14, 15) of the upper electrode run along the walls and the floor of the trench (5) at least as far as the upper edge of the spacer layer.
摘要翻译：本发明涉及一种在DRAM存储单元中的严重电容器使用和用于制造这样的Grabenkondensators.Der发明严重电容器包括下电容器电极（10），存储介质（12）和上电容器电极（18）的方法，至少部分地在的沟槽（5）被布置，其中，在所述上严重区域被提供而邻近于所述沟槽间隔件的壁中的层（9）由绝缘材料制成的下电容器电极（10）的下严重区域与沟槽的壁相邻，和上电极（18）的至少两个层（13，14，15），其中之一至少是金属的，与上部电极不是由两个层，其中一个是较低的硅化钨和上部掺杂多晶硅的条件，其中上部电极未的层（13，14，15）沿着每个壁的延伸到所述沟槽（5）的底部，以至少间隔件（9）D的上边缘上。

3. 发明申请

WO0118849A3 INTEGRATED CIRCUIT ARRANGEMENT WITH AT LEAST A CAPACITOR AND A METHOD FOR THE PRODUCTION OF THE SAID 审中-公开
标题翻译：具有至少一个电容器的集成电路装置及其制造方法
公开(公告)号：WO0118849A3
公开(公告)日：2001-06-14
申请号：PCT/DE0003123
申请日：2000-09-06
申请人： INFINEON TECHNOLOGIES AG , SCHUMANN DIRK , SELL BERNHARD , WILLER JOSEF
发明人： SCHUMANN DIRK , SELL BERNHARD , WILLER JOSEF
IPC分类号： H01L21/8242 , H01L21/02 , H01L27/108
CPC分类号： H01L28/91 , H01L27/10852
摘要： The capacitor is arranged on the surface of a substrate (1). A first capacitor electrode has a middle part (M) and a side part (ST),which point vertically upwards, are arranged beside each other and are connected with each other via an upper part (O) located above said middle part (M) and said side part (ST). The middle part (M) is longer than the side part (ST) and is connected with other components of the circuit arrangement located below said middle part (M) and said side part (ST). The first capacitor electrode is provided with a capacitor dielectric (KD). A second capacitor electrode (P) borders the capacitor dielectric (KD).
摘要翻译：电容器设置在衬底（1）的表面上。第一电容器电极具有基本竖直延伸的中央部分（M）和侧部分（ST），彼此相邻布置并且经由布置在上方的上部分（O）彼此连接。中间部分（M）比侧面部分（ST）长并连接到布置在电路装置下方的另一个部件。第一电容器电极配备有电容器电介质（KD）。第二电容器电极（P）邻接电容器电介质（KD）。

4. 发明申请

WO03079362A3 CIRCUIT ARRANGEMENT FOR SENSING AND EVALUATING A CHARGE STATE AND REWRITING THE LATTER TO A MEMORY CELL 审中-公开
标题翻译：电路进行读取，费率和重读的净电荷状态。CELL
公开(公告)号：WO03079362A3
公开(公告)日：2003-11-13
申请号：PCT/DE0300887
申请日：2003-03-18
申请人： INFINEON TECHNOLOGIES AG , GOLDBACH MATTHIAS , SELL BERNHARD
发明人： GOLDBACH MATTHIAS , SELL BERNHARD
IPC分类号： G11C7/06 , G11C11/4091 , G11C29/12 , G11C29/38 , G11C29/50 , G11C29/00
CPC分类号： G11C7/062 , G11C7/065 , G11C11/4091 , G11C11/41 , G11C29/12 , G11C29/38 , G11C29/50
摘要： The invention relates to a circuit arrangement comprising a bit line (10), a reference bit line (12), a sense amplifier equipped with two cross-coupled CMOS inverters, each of the latter having an n-channel transistor (20, 22) and a p-channel field effect transistor (30, 32), in addition to two respective voltage sources (40, 42) at the source connections, the voltage source (40) that is connected to the n-channel field effect transistors being traversed by a voltage rising from low to high and the voltage source (42) that is connected to the p-channel field effect transistors (30, 32) being traversed by a voltage reducing from high to low. Said circuit arrangement allows three different charge states to be stored in the memory cell (4) on the bit line (10), if the cut-off voltages (UTH1, UTH2) in the transistors are selected to be greater than half the voltage differential between the lower and upper voltage potential. This can be achieved technically during production or for example by the modification of the substrate bias voltage. The third charge state can be used for binary logic or to detect a defect in the memory cell (4).
摘要翻译：该电路装置包括一个位线（10），参考位线（12），其具有两个交叉耦合的CMOS反相器的读出放大器，每一个都包括n沟道晶体管（20，22）和一个p沟道场效应晶体管（30，32），以及至2个电压源（40,42），各自的源极端子，其中的拴从较低至（上电势的n沟道场效应晶体管的电压源（40）和p沟道场效应晶体管30 从上到下通过电位移动尾32）的电压源（42）。利用这种电路装置3个不同的电荷状态可以被存储在所述位线（10）如果阈值电压（值U TH1，Uth2）在晶体管选定小于下和上的电压电势之间的一半的电压差越大，存储单元（4）。这可以通过改变衬底偏置实现制造技术或例如。电荷的第三状态可用于二进制或逻辑在存储单元（4）检测缺陷。

5. 发明申请

WO03017342A2 METHOD FOR THE PRODUCTION OF A SELF-ADJUSTED STRUCTURE ON A SEMICONDUCTOR WAFER 审中-公开
标题翻译：用于生产自调节结构在半导体晶片
公开(公告)号：WO03017342A2
公开(公告)日：2003-02-27
申请号：PCT/DE0202651
申请日：2002-07-18
申请人： INFINEON TECHNOLOGIES AG , GOLDBACH MATTHIAS , HECHT THOMAS , LUETZEN JOERN , SELL BERNHARD
发明人： GOLDBACH MATTHIAS , HECHT THOMAS , LUETZEN JOERN , SELL BERNHARD
IPC分类号： G03F7/20 , H01L21/027 , H01L21/60 , H01L21/768 , H01L21/8242
CPC分类号： H01L27/10867 , H01L21/0274
摘要： A structure on a layer surface of the semiconductor wafer comprises at least one first surface (8,9) area reflecting electromagnetic radiation and at least one second substantially non-reflecting surface area (10,11,12). A transparent insulating layer (13) and a light-sensitive layer are produced on said layer surface. Electromagnetic radiation is directed at the light-sensitive layer at an incident angle &thetas; and the structure of the layer surface is imaged onto the light-sensitive layer with a lateral replacement.
摘要翻译：在半导体晶片的表面层的结构具有至少一个反射电磁辐射的第一区域（8,9）和至少一个第二基本上非反射区域的区域（10,11,12）。在该表面层的透明绝缘层（13）和一光敏层被产生。的电磁辐射是在入射角θ驱动＆; 引导到感光层，并准备在层表面的结构与在感光层中的横向更换。

6. 发明申请

WO2006039641A2 IMPROVING SHORT CHANNEL EFFECT OF MOS DEVICES BY RETROGRADE WELL ENGINEERING USING TILTED DOPANT IMPLANTATION INTO RECESSED SOURCE/DRAIN REGIONS 审中-公开
标题翻译：利用倾斜掺杂剂植入回流源/漏区改善MOS器件的逆流井工程的短沟道效应
公开(公告)号：WO2006039641A2
公开(公告)日：2006-04-13
申请号：PCT/US2005035474
申请日：2005-09-29
申请人： INTEL CORP , HOFFMANN THOMAS , TYAGI SUNIT , CURELLO GIUSEPPE , SELL BERNHARD , AUTH CHRISTOPHER
发明人： HOFFMANN THOMAS , TYAGI SUNIT , CURELLO GIUSEPPE , SELL BERNHARD , AUTH CHRISTOPHER
IPC分类号： H01L21/336 , H01L21/265 , H01L29/78
CPC分类号： H01L29/66636 , H01L21/26586 , H01L29/1083 , H01L29/41783 , H01L29/66492 , H01L29/7834 , H01L29/7848
摘要： A method of providing a halo implant region in a substrate of a MOS device having a gate electrode thereon and defining source/drain regions, a MOS device fabricated according to the above method, and a system comprising the MOS device. The method comprises: defining undercut recesses in the substrate at the source/drain regions thereof, the undercut recesses extending beneath the gate electrode; creating a halo implant region beneath the gate electrode between the recesses; and providing raised source/drain structures in the undercut recesses after creating the halo implant region.
摘要翻译：一种在其上具有栅极并限定源极/漏极区的MOS器件的衬底中提供晕环注入区的方法，根据上述方法制造的MOS器件以及包括该MOS器件的系统。该方法包括：在衬底的源/漏区处限定底切凹槽，底切凹槽在栅电极下方延伸; 在凹槽之间的栅电极下方形成晕环注入区; 以及在形成光晕注入区之后在底切凹槽中提供凸起的源极/漏极结构。

7. 发明申请

WO2010002718A2 METHOD OF FORMING STACKED TRENCH CONTACTS AND STRUCTURES FORMED THEREBY 审中-公开
标题翻译：形成堆叠的TRENCH联系人及其形成的结构的方法
公开(公告)号：WO2010002718A2
公开(公告)日：2010-01-07
申请号：PCT/US2009048764
申请日：2009-06-26
申请人： INTEL CORP , SELL BERNHARD , GOLONZKA OLEG
发明人： SELL BERNHARD , GOLONZKA OLEG
IPC分类号： H01L21/28
CPC分类号： H01L23/535 , H01L21/28052 , H01L21/28123 , H01L21/76805 , H01L21/76889 , H01L21/76895 , H01L21/76897 , H01L21/823425 , H01L21/823468 , H01L21/823475 , H01L23/485 , H01L23/5226 , H01L23/528 , H01L23/53257 , H01L23/53266 , H01L27/088 , H01L29/0847 , H01L29/4175 , H01L29/4925 , H01L29/66666 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an IlD disposed on a top surface of a metal gate disposed on the substrate.
摘要翻译：描述形成微电子器件的方法和相关结构。这些方法可以包括形成包括设置在基板的源极/漏极接触件上的第一接触金属和设置在第一接触金属的顶表面上的第二接触金属的结构，其中第二接触金属设置在设置的IID内在设置在基板上的金属栅极的顶面上。

8. 发明申请

WO2009017997A9 METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING ABRUPT ULTRA SHALLOW EPI-TIP REGIONS 审中-公开
标题翻译：形成具有突跳超浅触地区的半导体器件的方法
公开(公告)号：WO2009017997A9
公开(公告)日：2009-03-19
申请号：PCT/US2008070604
申请日：2008-07-21
申请人： INTEL CORP , RACHMADY WILLY , KEATING STEVEN , SELL BERNHARD
发明人： RACHMADY WILLY , KEATING STEVEN , SELL BERNHARD
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/823814 , H01L29/165 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： A method for forming a semiconductor device having abrupt ultra shallow epi-tip regions comprises forming a gate stack on a crystalline substrate, performing a first ion implantation process to amorphisize a first pair of regions of the substrate disposed adjacent to and on laterally opposite sides of the gate stack, forming a pair of spacers on the substrate disposed on laterally opposite sides of the gate stack, performing a second ion implantation process to amorphisize a second pair of regions of the substrate that are disposed on laterally opposite sides of the gate stack and adjacent to the spacers, applying a selective wet etch chemistry to remove the amorphisized first and second pair of regions and form a pair of cavities on laterally opposite sides of the gate stack, and depositing a silicon alloy in the pair of cavities to form source and drain regions and source and drain epi-tip regions.
摘要翻译：一种用于形成具有陡峭的超浅外延尖区域的半导体器件的方法包括：在晶体衬底上形成栅极堆叠，执行第一离子注入工艺以将衬底的第一对区域非晶化，所述第一对区域邻近并布置在横向相对侧所述栅极叠层在设置在所述栅极叠层的横向相对侧上的所述衬底上形成一对间隔物;执行第二离子注入工艺以使设置在所述栅极叠层的横向相对侧上的所述衬底的第二对区域非晶化;以及邻近间隔物，施加选择性湿法蚀刻化学物质以去除非晶化的第一和第二对区域，并在栅极堆叠的横向相对侧上形成一对空腔，并且在这对空腔中沉积硅合金以形成源极和漏极区域以及源极和漏极外延区域。

9. 发明申请

WO2005117130A2 STEPPED TIP JUNCTION WITH SPACER LAYER 审中-公开
标题翻译：带有间隔层的步进接头
公开(公告)号：WO2005117130A2
公开(公告)日：2005-12-08
申请号：PCT/US2005014969
申请日：2005-04-29
申请人： INTEL CORP , BAN IBRAHIM , SELL BERNHARD , NATARAJAN SANJAY , BOHR MARK
发明人： BAN IBRAHIM , SELL BERNHARD , NATARAJAN SANJAY , BOHR MARK
IPC分类号： H01L21/336 , H01L29/76 , H01L29/78
CPC分类号： H01L29/6659 , H01L29/6656 , H01L29/7833 , Y10S257/90
摘要： Embodiments of the invention provides a stepped tip junction region between a source/drain region of a transistor and a gate. In some embodiments, a spacer of the transistor includes a tip junction spacer layer and a source/drain spacer lacer.
摘要翻译：本发明的实施例提供了在晶体管的源极/漏极区域和栅极之间的阶梯形尖端结区域。在一些实施例中，晶体管的间隔物包括尖端连接间隔层和源极/漏极间隔物隔离器。

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