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1. 发明申请

WO2013019678A3 FIELD PROGRAMMABLE GATE ARRAY UTILIZING TWO-TERMINAL NON-VOLATILE MEMORY 审中-公开
公开(公告)号：WO2013019678A3
公开(公告)日：2013-02-07
申请号：PCT/US2012/048712
申请日：2012-07-27
申请人： CROSSBAR, INC. , NAZARIAN, Hagop , NGUYEN, Sang Thanh , KUMAR, Tanmay
发明人： NAZARIAN, Hagop , NGUYEN, Sang Thanh , KUMAR, Tanmay
IPC分类号： H03K19/173 , G11C13/00
摘要： Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.

2. 发明申请

WO2013003856A2 AMORPHOUS SILICON RRAM WITH NON-LINEAR DEVICE AND OPERATION 审中-公开
标题翻译：具有非线性器件和操作的无定形硅片
公开(公告)号：WO2013003856A2
公开(公告)日：2013-01-03
申请号：PCT/US2012/045312
申请日：2012-07-02
申请人： CROSSBAR, INC. , KUMAR, Tanmay
发明人： KUMAR, Tanmay
CPC分类号： G11C13/004 , G11C13/0007 , G11C13/003 , G11C13/0069 , G11C2013/0042 , G11C2013/0073 , G11C2213/33 , G11C2213/72 , G11C2213/74 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/14 , H01L45/148
摘要： A non-volatile memory device includes a resistive switching device having a first electrode, a second electrode, and a resistive switching element, wherein the resistive switching element comprises a silicon material disposed in an overlapping region between the first electrode and the second electrode, wherein the second electrode comprises at least a metal material physically and electrically in contact with the resistive switching material, wherein the resistive switching element is characterized by a resistance depending on an electric field in the resistive switching element, and a non-linear device coupled between the first electrode and the resistive switching element, wherein the non-linear device is configured to conduct electric current when a voltage greater than a first voltage is applied to the second electrode, wherein the resistive switching device is configured to change from a first state to a second state in response to the first voltage.
摘要翻译：非易失性存储装置包括具有第一电极，第二电极和电阻开关元件的电阻开关装置，其中电阻开关元件包括设置在第一电极和第二电极之间的重叠区域中的硅材料，第一电极和第二电极，其中所述第二电极至少包括与所述电阻切换材料物理和电接触的金属材料，其中所述电阻切换元件的特征在于取决于所述电阻切换元件中的电场的电阻，以及耦合在所述第一电极和所述电阻开关元件之间的非线性器件，其中所述非线性器件被配置为当大于第一电压的电压被施加到所述第二电极时传导电流，其中所述电阻开关器件被配置响应于第一电压从第一状态改变到第二状态。

3. 发明申请

WO2010074785A1 DUAL INSULATING LAYER DIODE WITH ASYMMETRIC INTERFACE STATE AND METHOD OF FABRICATION 审中-公开
标题翻译：具有不对称界面状态的双绝缘层二极管和制造方法
公开(公告)号：WO2010074785A1
公开(公告)日：2010-07-01
申请号：PCT/US2009/058858
申请日：2009-09-29
申请人： SANDISK 3D LLC , CHEN, Xiying , SEKAR, Deepak, Chandra , CLARK, Mark , NGUYEN, Dat , KUMAR, Tanmay
发明人： CHEN, Xiying , SEKAR, Deepak, Chandra , CLARK, Mark , NGUYEN, Dat , KUMAR, Tanmay
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L27/2481 , H01L27/2418 , H01L45/00
摘要： An integrated circuit including vertically oriented diode structures between conductors and methods of fabricating the same are provided. The diode is a metal-insulator diode having a first metal layer, a first insulating layer, a second insulating layer and a second metal layer. At least one asymmetric interface state is provided at the intersection of at least two of the layers to increase the ratio of the diode's on-current to its reverse bias leakage current. In various examples, the asymmetric interface state is formed by a positive or negative sheet charge that alters the barrier height and/or electric field at one or more portions of the diode. Two-terminal devices such as passive element memory cells can utilize the diode as a steering element in series with a state change element. The devices can be formed using pillar structures at the intersections of upper and lower conductors.
摘要翻译：提供了一种在导体之间包括垂直取向的二极管结构的集成电路及其制造方法。二极管是具有第一金属层，第一绝缘层，第二绝缘层和第二金属层的金属绝缘体二极管。在至少两个层的交叉点处提供至少一个非对称界面状态，以增加二极管的导通电流与其反向偏置漏电流的比率。在各种实施例中，非对称界面状态由改变二极管的一个或多个部分处的势垒高度和/或电场的正或负片材电荷形成。诸如无源元件存储单元的两端器件可以将二极管用作与状态改变元件串联的转向元件。可以在上下导体的交点处使用支柱结构形成装置。

4. 发明申请

WO2009002476A2 NONVOLATILE MEMORY DEVICE CONTAINING CARBON OR NITROGEN DOPED DIODE AND METHOD OF MAKING THEREOF 审中-公开
标题翻译：含有碳或氮的二极管的非易失性存储器件及其制造方法
公开(公告)号：WO2009002476A2
公开(公告)日：2008-12-31
申请号：PCT/US2008/007801
申请日：2008-06-23
申请人： SANDISK 3D LLC , HERNER, S., Brad , CLARK, Mark, H. , KUMAR, Tanmay
发明人： HERNER, S., Brad , CLARK, Mark, H. , KUMAR, Tanmay
IPC分类号： H01L27/102 , H01L29/868 , G11C11/36 , H01L29/861 , H01L29/161 , H01L29/167 , H01L29/26
CPC分类号： H01L29/868 , G11C11/5692 , G11C17/06 , G11C17/16 , G11C17/165 , G11C2213/33 , G11C2213/71 , G11C2213/72 , H01L27/0688 , H01L27/1021 , H01L29/04 , H01L29/161 , H01L29/167 , H01L29/66136 , H01L29/8615
摘要： A nonvolatile memory device includes at least one nonvolatile memory cell which comprises a silicon, germanium or silicon-germanium diode which is doped with at least one of carbon or nitrogen in a concentration greater than an unavoidable impurity level concentration.
摘要翻译：非易失性存储器件包括至少一个非易失性存储单元，其包括硅，锗或硅 - 锗二极管，其掺杂有浓度大于不可避免的杂质水平浓度的碳或氮中的至少一种。

5. 发明申请

WO2007062022A1 REVERSIBLE RESISTIVITY-SWITCHING METAL OXIDE OR NITRIDE LAYER WITH ADDED METAL 审中-公开
标题翻译：具有添加金属的可逆电阻开关金属氧化物或氮化物层
公开(公告)号：WO2007062022A1
公开(公告)日：2007-05-31
申请号：PCT/US2006/045034
申请日：2006-11-20
申请人： SANDISK 3D LLC , HERNER, S., Brad , KUMAR, Tanmay
发明人： HERNER, S., Brad , KUMAR, Tanmay
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L45/145 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1625 , H01L45/165 , H01L45/1658 , H01L45/1675
摘要： A layer of resistivity-switching metal oxide or nitride can attain at least two stable resistivity states. Such a layer may be used in a state-change element in a nonvolatile memory cell, storing its data state, for example a "0" or a "1", in this resistivity state. Including additional metal atoms in a layer of such a resistivity-switching metal oxide or nitride compound decreases the current required to cause switching between resistivity states, reducing power requirements for an array of memory cells storing data in the resistivity state of such a layer. In various embodiments a memory cell may include a layer of resistivity-switching metal oxide or nitride compound with added metal formed in series with another element, such as a diode or a transistor.
摘要翻译：电阻率切换金属氧化物或氮化物层可达到至少两个稳定的电阻率状态。这种层可以用在非易失性存储单元中的状态变化元件中，在该电阻率状态下存储其数据状态，例如“0”或“1”。在这种电阻率切换金属氧化物或氮化物化合物的层中包括额外的金属原子降低了在电阻率状态之间导致切换所需的电流，从而降低了存储在这种层的电阻率状态下的数据的存储单元阵列的功率需求。在各种实施例中，存储器单元可以包括电阻率切换金属氧化物或具有与另一元件（例如二极管或晶体管）串联形成的附加金属的氮化物化合物层。

6. 发明申请

WO2010080332A1 METHOD OF PROGRAMMING A NONVOLATILE MEMORY DEVICE CONTAINING A CARBON STORAGE MATERIAL 审中-公开
标题翻译：编制含有碳储存材料的非易失性存储器件的方法
公开(公告)号：WO2010080332A1
公开(公告)日：2010-07-15
申请号：PCT/US2009/067602
申请日：2009-12-11
申请人： SANDISK 3D LLC , KUMAR, Tanmay , CHEN, Xiying
发明人： KUMAR, Tanmay , CHEN, Xiying
IPC分类号： G11C13/00 , G11C16/02
CPC分类号： G11C13/025 , B82Y10/00 , G11C13/00 , G11C13/0004 , G11C13/0069 , G11C2013/0092 , G11C2213/35 , G11C2213/72 , H01L27/24
摘要： A nonvolatile memory cell includes a steering element located in series with a storage element, where the storage element comprises a carbon material. A method of programming the cell includes applying a reset pulse to change a resistivity state of the carbon material from a first state to a second state which is higher than the first state, and applying a set pulse to change a resistivity state of the carbon material from the second state to a third state which is lower than the second state. A fall time of the reset pulse is shorter than a fall time of the set pulse.
摘要翻译：非易失性存储单元包括与存储元件串联定位的转向元件，其中存储元件包括碳材料。一种对单元进行编程的方法包括施加复位脉冲以将碳材料的电阻率状态从第一状态改变到高于第一状态的第二状态，并且施加设定脉冲以改变碳材料的电阻率状态从第二状态到低于第二状态的第三状态。复位脉冲的下降时间比设定脉冲的下降时间短。

7. 发明申请

WO2010006000A1 CARBON-BASED RESISTIVITY-SWITCHING MATERIALS AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：基于碳的电阻率切换材料及其形成方法
公开(公告)号：WO2010006000A1
公开(公告)日：2010-01-14
申请号：PCT/US2009/049854
申请日：2009-07-07
申请人： SANDISK 3D, LLC , XU, Huiwen , CHEN, Xiying , SCHEUERLEIN, Roy, E. , PING, Er-Xuan , KUMAR, Tanmay , ILKBAHAR, Alper
发明人： XU, Huiwen , CHEN, Xiying , SCHEUERLEIN, Roy, E. , PING, Er-Xuan , KUMAR, Tanmay , ILKBAHAR, Alper
IPC分类号： H01L45/00 , C23C14/06 , G11C13/02
CPC分类号： B82Y10/00 , B82Y30/00 , C23C16/26 , G11C13/0014 , G11C13/025 , G11C2213/19 , G11C2213/35 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/124 , H01L45/149 , H01L45/1616
摘要： Memory devices including a carbon-based resistivity-switchable material, and methods of forming such memory devices are provided, the methods including introducing a processing gas into a processing chamber, wherein the processing gas includes a hydrocarbon compound and a carrier gas, and generating a plasma of the processing gas to deposit a layer of the carbon-based switchable material on a substrate within the processing chamber. Numerous additional aspects are provided.
摘要翻译：提供了包括碳基电阻率可切换材料的存储器件以及形成这种存储器件的方法，所述方法包括将处理气体引入处理室，其中处理气体包括烃化合物和载气，并产生处理气体的等离子体，以在处理室内的基板上沉积碳基可切换材料层。还提供了许多其他方面。

8. 发明申请

WO2009134324A1 REDUCTION OF LEAKAGE CURRENT IN A VERTICAL DIODE 审中-公开
标题翻译：降低垂直二极管中的漏电流
公开(公告)号：WO2009134324A1
公开(公告)日：2009-11-05
申请号：PCT/US2009/002402
申请日：2009-04-17
申请人： SANDISK 3D LLC , CHEN, Xiying , CLARK, Mark, H. , HERNER, S., Brad , KUMAR, Tanmay
发明人： CHEN, Xiying , CLARK, Mark, H. , HERNER, S., Brad , KUMAR, Tanmay
IPC分类号： H01L29/868 , H01L29/861
CPC分类号： H01L29/868 , H01L29/1606 , H01L29/8615
摘要： One embodiment of the invention provides a semiconductor diode device including a first conductivity type region, a second conductivity type region, where the second conductivity type is different from the first conductivity type, an intrinsic region located between the first conductivity type region and the second conductivity type region; a first halo region of the first conductivity type located between the second conductivity type region and the intrinsic region, and optionally a second halo region of the second conductivity type located between the first conductivity type region and the intrinsic region.
摘要翻译：本发明的一个实施例提供一种半导体二极管器件，其包括第一导电类型区域和第二导电类型区域，其中第二导电类型不同于第一导电类型，位于第一导电类型区域和第二导电类型之间的本征区域类型区域位于第二导电类型区域和本征区域之间的第一导电类型的第一晕区，以及任选地位于第一导电类型区域和本征区域之间的第二导电类型的第二晕区域。

9. 发明申请

WO2007126679A2 HETEROJUNCTION DEVICE COMPRISING A SEMICONDUCTOR AND A RESISTIVITY-SWITCHING OXIDE OR NITRIDE 审中-公开
标题翻译：包含半导体和电阻率切换氧化物或氮化物的异质结构
公开(公告)号：WO2007126679A2
公开(公告)日：2007-11-08
申请号：PCT/US2007/007155
申请日：2007-03-22
申请人： SANDISK 3D LLC , KUMAR, Tanmay , HERNER, S., Brad
发明人： KUMAR, Tanmay , HERNER, S., Brad
IPC分类号： H01L27/102 , H01L29/861 , H01L29/868 , H01L29/417
CPC分类号： H01L29/868 , H01L21/84 , H01L27/1021 , H01L27/2409 , H01L29/165 , H01L29/22 , H01L29/267 , H01L29/417 , H01L29/737 , H01L29/8615 , H01L45/04 , H01L45/1233 , H01L45/146
摘要： In the present invention a metal oxide or nitride compound which is a wide¬ band-gap semiconductor abuts a silicon, germanium, or alloy of silicon and/or germanium of the opposite conductivity type to form a p-n heteroj unction. This p-n heteroj unction can be used to advantage in various devices. In preferred embodiments, one terrninal of a vertically oriented p-i-n heterojunction diode is a metal oxide or nitride layer, while the rest of the diode is formed of a silicon or silicon-germanium resistor; for example a diode may include a heavily doped n-type silicon region, an intrinsic silicon region, and a nickel oxide layer serving as the p-type terminal. Many of these metal oxides and nitrides exhibit resistivity-switching behavior, and such a heterojunction diode can be used in a nonvolatile memory cell, for example in a monc-lithic three dimensional memory array.
摘要翻译：在本发明中，作为宽带隙半导体的金属氧化物或氮化物化合物与相反导电型的硅和/或锗的硅，锗或合金相接触以形成p-n异质结。这种p-n异质结可以用于各种装置中。在优选实施例中，垂直取向的p-i-n异质结二极管的一个栅极是金属氧化物或氮化物层，而二极管的其余部分由硅或硅 - 锗电阻器形成; 例如，二极管可以包括重掺杂的n型硅区，本征硅区和用作p型端的氧化镍层。这些金属氧化物和氮化物中的许多表现出电阻率切换行为，并且这种异质结二极管可以用在非易失性存储单元中，例如在单晶三维存储器阵列中。

10. 发明申请

WO2007058845A2 VERTICAL DIODE DOPED WITH ANTIMONY TO AVOID OR LIMIT DOPANT DIFFUSION 审中-公开
标题翻译：用反抗避免或限制痰液扩散的垂直二极管
公开(公告)号：WO2007058845A2
公开(公告)日：2007-05-24
申请号：PCT/US2006/043482
申请日：2006-11-08
申请人： SANDISK 3D LLC , KUMAR, Tanmay , HERNER, S., Brad
发明人： KUMAR, Tanmay , HERNER, S., Brad
IPC分类号： H01L29/861 , H01L29/868 , H01L21/329 , H01L29/167 , H01L27/102 , H01L27/12 , H01L21/84
CPC分类号： H01L27/1021 , H01L29/167 , H01L29/861
摘要： Use of antimony as an n-type conductivity-enhancing dopant in semiconductor structures having a vertical dopant profile is described. Dopants tend to diffuse, and steep dopant gradients can be difficult to maintain. Specifically, when a silicon layer is doped with phosphorus or arsenic, both n-type dopants, dopant atoms tend to seek the surface as undoped silicon is deposited on top of the n- doped layer, rising through the undoped silicon during deposition. Antimony does not have this tendency, and also diffuses more slowly than either phosphorus or arsenic, and this is advantageously used to dope such structures.
摘要翻译：描述了在具有垂直掺杂剂分布的半导体结构中使用锑作为n型导电性增强掺杂剂。掺杂剂倾向于扩散，并且陡峭的掺杂剂梯度可能难以维持。具体地说，当硅层掺杂有磷或砷时，n型掺杂剂掺杂剂原子倾向于寻找表面，因为未掺杂的硅沉积在n掺杂层的顶部，在沉积期间通过未掺杂的硅上升。锑不具有这种倾向，并且也比磷或砷更慢地扩散，并且有利地用于掺杂这种结构。

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