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1. 发明申请

WO2010074785A1 DUAL INSULATING LAYER DIODE WITH ASYMMETRIC INTERFACE STATE AND METHOD OF FABRICATION 审中-公开
标题翻译：具有不对称界面状态的双绝缘层二极管和制造方法
公开(公告)号：WO2010074785A1
公开(公告)日：2010-07-01
申请号：PCT/US2009/058858
申请日：2009-09-29
申请人： SANDISK 3D LLC , CHEN, Xiying , SEKAR, Deepak, Chandra , CLARK, Mark , NGUYEN, Dat , KUMAR, Tanmay
发明人： CHEN, Xiying , SEKAR, Deepak, Chandra , CLARK, Mark , NGUYEN, Dat , KUMAR, Tanmay
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L27/2481 , H01L27/2418 , H01L45/00
摘要： An integrated circuit including vertically oriented diode structures between conductors and methods of fabricating the same are provided. The diode is a metal-insulator diode having a first metal layer, a first insulating layer, a second insulating layer and a second metal layer. At least one asymmetric interface state is provided at the intersection of at least two of the layers to increase the ratio of the diode's on-current to its reverse bias leakage current. In various examples, the asymmetric interface state is formed by a positive or negative sheet charge that alters the barrier height and/or electric field at one or more portions of the diode. Two-terminal devices such as passive element memory cells can utilize the diode as a steering element in series with a state change element. The devices can be formed using pillar structures at the intersections of upper and lower conductors.
摘要翻译：提供了一种在导体之间包括垂直取向的二极管结构的集成电路及其制造方法。二极管是具有第一金属层，第一绝缘层，第二绝缘层和第二金属层的金属绝缘体二极管。在至少两个层的交叉点处提供至少一个非对称界面状态，以增加二极管的导通电流与其反向偏置漏电流的比率。在各种实施例中，非对称界面状态由改变二极管的一个或多个部分处的势垒高度和/或电场的正或负片材电荷形成。诸如无源元件存储单元的两端器件可以将二极管用作与状态改变元件串联的转向元件。可以在上下导体的交点处使用支柱结构形成装置。

2. 发明申请

WO2008134253A1 REDUCING POWER CONSUMPTION DURING READ OPERATIONS IN NON-VOLATILE STORAGE 审中-公开
标题翻译：在非易失存储器中阅读操作期间降低功耗
公开(公告)号：WO2008134253A1
公开(公告)日：2008-11-06
申请号：PCT/US2008/060630
申请日：2008-04-17
申请人： SANDISK CORPORATION , SEKAR, Deepak, Chandra , MOKHLESI, Nima , SO, Hock, C.
发明人： SEKAR, Deepak, Chandra , MOKHLESI, Nima , SO, Hock, C.
IPC分类号： G11C11/56 , G11C16/04 , G11C16/26
CPC分类号： G11C16/0483 , G11C11/5628 , G11C11/5642 , G11C16/26 , G11C16/3418 , G11C16/3459 , G11C2211/5621 , G11C2211/5634 , G11C2211/5648 , G11C2211/565
摘要： Power consumption in a non-volatile storage device is reduced by providing reduced read pass voltages on unselected word lines during a read operation. A programming status of one or more unselected word lines which are after a selected word line on which storage elements are being read is checked to determine whether the unselected word lines contain programmed storage elements. When an unprogrammed word line is identified, reduced read pass voltages are provided on that word line and other word lines which are after that word line in a programming order. The programming status can be determined by a flag stored in the word line, for instance, or by reading the word line at the lowest read state. The unselected word lines which are checked can be predetermined in a set of word lines, or determined adaptively based on a position of the selected word line.
摘要翻译：在读取操作期间通过在未选择的字线上提供减小的读取通过电压来减少非易失性存储设备中的功耗。检查在其上正在读取存储元件的所选字线之后的一个或多个未选字线的编程状态，以确定未选择的字线是否包含编程的存储元件。当识别出未编程的字线时，在该字线和在该字线之后的编程顺序中的其它字线提供减小的读通道电压。编程状态可以通过例如存储在字线中的标志来确定，或者通过在最低读取状态下读取字线来确定。被检查的未选择的字线可以在一组字线中预先确定，或者基于所选字线的位置自适应地确定。

3. 发明申请

WO2011115926A1 BOTTOM ELECTRODES FOR USE WITH METAL OXIDE RESISTIVITY SWITCHING LAYERS 审中-公开
标题翻译：使用金属氧化物电阻切换层的底部电极
公开(公告)号：WO2011115926A1
公开(公告)日：2011-09-22
申请号：PCT/US2011/028396
申请日：2011-03-14
申请人： SANDISK 3D, LLC , SEKAR, Deepak, Chandra , KREUPL, Franz , MAKALA, Raghuveer, S.
发明人： SEKAR, Deepak, Chandra , KREUPL, Franz , MAKALA, Raghuveer, S.
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L45/146 , H01L27/2409 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/1675
摘要： A MIM stack (200a) is provided that includes (1) a first conductive layer (108) comprising a first metal - silicide layer (108a) and a second metal - silicide layer (108b); (2) a resistivity- switching layer (104) comprising a metal oxide layer formed above the first conductive layer; and (3) a second conductive layer (106) formed above the resistivity- switching layer. A memory cell may be formed from the MIM stack. Numerous other aspects are provided.
摘要翻译：提供MIM堆叠（200a），其包括（1）包括第一金属硅化物层（108a）和第二金属硅化物层（108b）的第一导电层（108）（2）包含形成在所述第一导电层上方的金属氧化物层的电阻率切换层（104）和（3）形成在电阻率切换层上方的第二导电层（106）。存储单元可以由MIM堆叠形成。提供了许多其他方面。

4. 发明申请

WO2008121535A1 NON-VOLATILE MEMORY AND METHOD FOR COMPENSATION FOR VOLTAGE DROPS ALONG A WORD LINE 审中-公开
标题翻译：非挥发性记忆和方法，用于补偿字线上的电压降
公开(公告)号：WO2008121535A1
公开(公告)日：2008-10-09
申请号：PCT/US2008/056975
申请日：2008-03-14
申请人： SANDISK CORPORATION , SEKAR, Deepak Chandra , MUI, Man Lung , MOKHLESI, Nima
发明人： SEKAR, Deepak Chandra , MUI, Man Lung , MOKHLESI, Nima
IPC分类号： G11C16/12 , G11C16/04 , G11C11/56
CPC分类号： G11C16/12 , G11C7/18 , G11C8/14 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/24 , G11C16/30
摘要： Variation in programming efficacy due to variation in time constants along a word line that spans across a memory plane is compensated by adjusting the bit line voltages across the plane to modify the programming rates. In this way, the variation in programming efficacy is substantially reduced during programming of a group of memory cells coupled to the word line. This will allow uniform optimization of programming across the group of memory cells and reduce the number of programming pulses required to program the group of memory cells, thereby improving performance. In one embodiment, during programming, the bit lines in a first half of the memory plane closer to a source of word line voltage is set to a first voltage by a first voltage shifter and the bit lines in a second half of the memory plane further from the source of word line voltage is set to a second voltage by a second voltage shifter.
摘要翻译：由跨越存储器平面的字线的时间常数变化引起的编程效能的变化通过调整整个平面上的位线电压来修正编程速率来补偿。以这种方式，在编程耦合到字线的一组存储器单元的编程期间，编程功效的变化显着降低。这将允许对存储器单元组进行编程的均匀优化，并且减少编程存储器单元组所需的编程脉冲数，从而提高性能。在一个实施例中，在编程期间，更靠近字线电压源的存储器平面的前半部分中的位线被第一电压移位器设置为第一电压，并且存储器平面的后半部分中的位线进一步从第二电压转换器将字线电压源设定为第二电压。

5. 发明申请

WO2011115924A1 BOTTOM ELECTRODES FOR USE WITH METAL OXIDE RESISTIVITY SWITCHING LAYERS 审中-公开
标题翻译：使用金属氧化物电阻切换层的底部电极
公开(公告)号：WO2011115924A1
公开(公告)日：2011-09-22
申请号：PCT/US2011/028394
申请日：2011-03-16
申请人： SANDISK 3D, LLC , SEKAR, Deepak Chandra , KREUPL, Franz , MAKALA, Raghuveer S.
发明人： SEKAR, Deepak Chandra , KREUPL, Franz , MAKALA, Raghuveer S.
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L45/146 , H01L27/2409 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/1675
摘要： A metal - insulator-metal (MIM) stack is provided that includes ( 1 ) a first conductive layer comprising a silicon - germanium (SiGe) alloy; ( 2 ) a resistivity- switching layer comprising a metal oxide layer formed above the first conductive layer; and ( 3 ) a second conductive layer formed above the resistivity- switching layer. A memory cell may be formed from the MIM stack.
摘要翻译：提供了一种金属 - 绝缘体 - 金属（MIM）堆叠，其包括（1）包含硅 - 锗（SiGe）合金的第一导电层; （2）电阻率切换层，包括在所述第一导电层上形成的金属氧化物层; 和（3）形成在电阻率切换层上方的第二导电层。存储单元可以由MIM堆叠形成。

6. 发明申请

WO2009082637A1 REGULATION OF SOURCE POTENTIAL TO COMBAT CELL SOURCE IR DROP 审中-公开
标题翻译：源电位对调节细胞来源红细胞减少的调节
公开(公告)号：WO2009082637A1
公开(公告)日：2009-07-02
申请号：PCT/US2008/086694
申请日：2008-12-12
申请人： SANDISK CORPORATION , LEE, Dana , MOKHLESI, Nima , SEKAR, Deepak Chandra
发明人： LEE, Dana , MOKHLESI, Nima , SEKAR, Deepak Chandra
IPC分类号： G11C16/30
CPC分类号： G11C16/30
摘要： Techniques are presented for dealing with possible source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits of a non-volatile memory. The error is caused by a voltage drop across the resistance of the source path to the chip's ground when current flows. For this purpose, the memory device includes a source potential regulation circuit, including an active circuit element having a first input connected to a reference voltage and having a second input connected as a feedback loop that is connectable to the aggregate node from which the memory cells of a structural block have their current run to ground. A variation includes a non-linear resistive element connectable between the aggregate node and ground.
摘要翻译：提出用于处理可能的源极偏置的技术是由非易失性存储器的读/写电路的接地回路中的非零电阻引入的误差。误差是由电流流动时芯片接地源极路径的电阻上的电压降引起的。为此，存储器件包括源极电位调节电路，其包括有源电路元件，该有源电路元件具有连接到参考电压的第一输入端，并且具有连接到反馈回路的第二输入端，该反馈回路可连接到汇集节点，存储器单元的结构块现在已经跑到地面上了。变化包括可在聚集节点和地之间连接的非线性电阻元件。

7. 发明申请

WO2015084971A1 REDUCED CURRENT MEMORY DEVICE 审中-公开
标题翻译：减少电流存储器件
公开(公告)号：WO2015084971A1
公开(公告)日：2015-06-11
申请号：PCT/US2014/068394
申请日：2014-12-03
申请人： RAMBUS INC. , SEKAR, Deepak Chandra , HAUKNESS, Brent S. , BATEMAN, Bruce L.
发明人： SEKAR, Deepak Chandra , HAUKNESS, Brent S. , BATEMAN, Bruce L.
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C11/1659 , G11C11/1675 , G11C13/003 , G11C13/0097 , H01L27/2409 , H01L27/2436 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1226 , H01L45/144 , H01L45/146
摘要： A memory device includes a local bit line coupled to a plurality of memory cells and a global bit line through first and second selectable parallel paths having first and second impedances, respectively. The first path is active in at least one of a set operation or a forming operation and the second path is active in a reset operation. A select device to select a memory element includes a drain having a first doping level and a source having a second doping level lower than the first doping level, wherein the device is configured to provide a first on impedance or a second on impedance to the resistive memory element in response to a control signal.
摘要翻译：存储器件包括分别耦合到多个存储器单元的本地位线和通过分别具有第一和第二阻抗的第一和第二可选择并行路径的全局位线。第一路径在设置操作或形成操作中的至少一个中有效，并且第二路径在复位操作中有效。选择存储器元件的选择器件包括具有第一掺杂级别的漏极和具有低于第一掺杂级别的第二掺杂级的源极，其中该器件被配置为向电阻器提供第一导通阻抗或第二阻抗存储元件响应于控制信号。

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