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1. 发明申请

WO2004072660A2 COMPRESSING TEST RESPONSES USING A COMPACTOR 审中-公开
标题翻译：使用压缩机压缩测试响应
公开(公告)号：WO2004072660A2
公开(公告)日：2004-08-26
申请号：PCT/US2004/004271
申请日：2004-02-13
申请人： MENTOR GRAPHICS CORPORATION , RAJSKI, Janusz , TYSZER, Jerzy , WANG, Chen , MRUGALSKI, Grzegorz , POGIEL, Artur
发明人： RAJSKI, Janusz , TYSZER, Jerzy , WANG, Chen , MRUGALSKI, Grzegorz , POGIEL, Artur
IPC分类号： G01R
CPC分类号： G01R31/318566 , G01R31/31703 , G01R31/318536 , G01R31/318583 , G01R31/31921 , G11C29/40 , G11C29/48 , G11C2029/3202
摘要： The present disclosure describes embodiments of a compactor for compressing test results in an integrated circuit and methods for using and designing such embodiments. The disclosed compactors can be utilized, for example, as part of any scan-based design. Moreover, any of the disclosed compactors can be designed, simulated, and/or verified in a computer-executed application, such as an electronic-design-automation ("EDA") software tool. Embodiments of a method for diagnosing faults in the disclosed compactor embodiments are also described.
摘要翻译：本公开描述了用于压缩集成电路中的测试结果的压实机的实施例以及用于使用和设计这些实施例的方法。所公开的压实机可以用作例如任何基于扫描的设计的一部分。此外，任何公开的压实机可以在诸如电子设计自动化（“EDA”）软件工具的计算机执行的应用中被设计，模拟和/或验证。还描述了在公开的压实机实施例中用于诊断故障的方法的实施例。

2. 发明申请

WO2009039316A3 FAULT DIAGNOSIS IN A MEMORY BIST ENVIRONMENT USING A LINEAR FEEDBACK SHIFT REGISTER 审中-公开
标题翻译：使用线性反馈移位寄存器的记忆体环境中的故障诊断
公开(公告)号：WO2009039316A3
公开(公告)日：2009-08-20
申请号：PCT/US2008076911
申请日：2008-09-18
申请人： MENTOR GRAPHICS CORP , MUKHERJEE NILANJAN , POGIEL ARTUR , RAJSKI JANUSZ , TYSZER JERZY
发明人： MUKHERJEE NILANJAN , POGIEL ARTUR , RAJSKI JANUSZ , TYSZER JERZY
IPC分类号： G11C29/56 , G11C29/40
CPC分类号： G11C29/56 , G11C29/40 , G11C29/44 , G11C29/56008 , G11C2029/1208
摘要： Disclosed are methods and devices for temporally compacting test response signatures of failed memory tests in a memory built-in self -test environment, to provide the ability to carry on memory built-in self-test operations even with the detection of multiple time related memory test failures. In some implementations of the invention, the compacted test response signatures are provided to an automated test equipment device along with memory location information. According to various implementations of the invention, an integrated circuit with embedded memory (204) and a memory BIST controller (206) also includes a linear feedback structure (410) for use as a signature register that can temporally compact test response signatures from the embedded memory array during a test step of a memory test. In various implementations the integrated circuit may also include a failing words counter (211), a failing column indicator (213), and/or a failing row indicator (214) to collect memory location information for a failing test response.
摘要翻译：公开了用于在存储器内置自测环境中暂时压缩失败存储器测试的测试响应特征的方法和设备，以提供即使在检测到多个时间相关存储器的情况下进行存储器内置自检操作的能力测试失败。在本发明的一些实施方案中，将压实的测试响应签名与存储器位置信息一起提供给自动测试设备设备。根据本发明的各种实施方式，具有嵌入式存储器（204）和存储器BIST控制器（206）的集成电路还包括用作签名寄存器的线性反馈结构（410），其可以临时压缩来自嵌入式在内存测试的测试步骤中的内存阵列。在各种实现中，集成电路还可以包括故障字计数器（211），故障列指示器（213）和/或故障行指示器（214），以收集故障测试响应的存储器位置信息。

3. 发明申请

WO2007098167A2 MULTI-STAGE TEST RESPONSE COMPACTORS 审中-公开
标题翻译：多级测试响应压缩机
公开(公告)号：WO2007098167A2
公开(公告)日：2007-08-30
申请号：PCT/US2007/004422
申请日：2007-02-19
申请人： MENTOR GRAPHICS CORPORATION , MRUGALSKI, Grzegorz , RAJSKI, Janusz , TYSZER, Jerzy , CHENG, Wu-tung , MUKHERJEE, Nilanjan , KASSAB, Mark
发明人： MRUGALSKI, Grzegorz , RAJSKI, Janusz , TYSZER, Jerzy , CHENG, Wu-tung , MUKHERJEE, Nilanjan , KASSAB, Mark
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/3177 , G01R31/2851 , G01R31/31723 , G01R31/31727 , G01R31/318547 , G01R31/318563 , G01R31/318566
摘要： Disclosed herein are exemplary embodiments of a so-called "X-press" test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 100Ox. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.
摘要翻译：这里公开了所谓的“X-press”测试响应压实机的示例性实施例。所公开的压实机的某些实施例包括过驱动部分和扫描链选择逻辑。所公开技术的某些实施方案提供大约1000x的压实比。所公开的压实机的示例性实施例可以保持与常规的基于扫描的测试场景相同的覆盖范围和大致相同的诊断分辨率。扫描链选择方案的一些实施例可以显着地减少或完全消除在进入压实机的测试响应中发生的未知状态。本文还公开了片上比较器电路和用于产生用于屏蔽选择电路的控制电路的方法的实施例。

4. 发明申请

WO2004072660A3 COMPRESSING TEST RESPONSES USING A COMPACTOR 审中-公开
标题翻译：使用压缩机压缩测试响应
公开(公告)号：WO2004072660A3
公开(公告)日：2005-04-28
申请号：PCT/US2004004271
申请日：2004-02-13
申请人： MENTOR GRAPHICS CORP , RAJSKI JANUSZ , TYSZER JERZY , WANG CHEN , MRUGALSKI GRZEGORZ , POGIEL ARTUR
发明人： RAJSKI JANUSZ , TYSZER JERZY , WANG CHEN , MRUGALSKI GRZEGORZ , POGIEL ARTUR
IPC分类号： G01R31/3185 , G01R31/319 , G11C29/40 , G11C29/48 , G06F11/00 , G01R31/28
CPC分类号： G01R31/318566 , G01R31/31703 , G01R31/318536 , G01R31/318583 , G01R31/31921 , G11C29/40 , G11C29/48 , G11C2029/3202
摘要： The present disclosure describes embodiments of a compactor (706) for compressing test results in an integrated circuit (704) and methods for using and designing such embodiments. The disclosed compactors can be utilized, for example, as part of any scan-based design. Moreover, any of the disclosed compactors can be designed, simulated, and/or verified in a computer-executed application, such as an electronic-design-automation ("EDA") software tool. Embodiments of a method for diagnosing faults in the disclosed compactor embodiments are also described.
摘要翻译：本公开描述了用于压缩集成电路（704）中的测试结果的压实器（706）的实施例以及用于使用和设计这些实施例的方法。所公开的压实机可以例如用作任何基于扫描的设计的一部分。此外，任何公开的压实机可以在诸如电子设计自动化（“EDA”）软件工具的计算机执行的应用中被设计，模拟和/或验证。还描述了在公开的压实机实施例中用于诊断故障的方法的实施例。

5. 发明申请

WO2012150970A1 TEST SCHEDULING WITH PATTERN-INDEPENDENT TEST ACCESS MECHANISM 审中-公开
标题翻译：具有独特的测试访问机制的测试调度
公开(公告)号：WO2012150970A1
公开(公告)日：2012-11-08
申请号：PCT/US2012/021575
申请日：2012-01-17
申请人： MENTOR GRAPHICS CORPORATION , RAJSKI, Janusz , KASSAB, Mark, A. , GRZEGORZ, Mrugalski , MUKHERJEE, Nilanjan , JANICKI, Jakub , TYSZER, Jerzy , DUTTA, Avijit
发明人： RAJSKI, Janusz , KASSAB, Mark, A. , GRZEGORZ, Mrugalski , MUKHERJEE, Nilanjan , JANICKI, Jakub , TYSZER, Jerzy , DUTTA, Avijit
IPC分类号： G06F11/263 , G01R31/3183 , G01R31/319 , G06F11/07 , G06F11/22
CPC分类号： H04L43/50 , G01R31/318335 , G06F11/263
摘要： Disclosed are representative embodiments of methods, apparatus, and systems for test scheduling for testing a plurality of cores in a system on circuit. Test data are encoded to derive compressed test patterns that require small numbers of core input channels. Core input/output channel requirement information for each of the compressed test patterns is determined accordingly. The compressed patterns are grouped into test pattern classes. The formation of the test pattern classes is followed by allocation circuit input and output channels and test application time slots that may comprise merging complementary test pattern classes into clusters that can work with a particular test access mechanism. The test access mechanism may be designed independent of the test data.
摘要翻译：公开了用于在电路系统中测试多个核的测试调度的方法，装置和系统的代表性实施例。编码测试数据以导出需要少量核心输入通道的压缩测试模式。相应地确定每个压缩测试图案的核心输入/输出通道要求信息。压缩的模式被分组成测试模式类。测试模式类的形成之后是分配电路输入和输出通道以及测试应用时隙，其可以包括将互补测试模式类合并成可以与特定测试访问机制一起工作的集群。可以独立于测试数据设计测试访问机制。

6. 发明申请

WO2010102235A1 FAULT DIAGNOSIS FOR NON-VOLATILE MEMORIES 审中-公开
标题翻译：故障诊断非易失性存储器
公开(公告)号：WO2010102235A1
公开(公告)日：2010-09-10
申请号：PCT/US2010/026403
申请日：2010-03-05
申请人： MENTOR GRAPHICS CORPORATION , MUKHERJEE, Nilanjan , POGIEL, Artur , RAJSKI, Janusz , TYSZER, Jerzy
发明人： MUKHERJEE, Nilanjan , POGIEL, Artur , RAJSKI, Janusz , TYSZER, Jerzy
IPC分类号： G11C29/20 , G11C29/40 , G11C29/56
CPC分类号： G11C29/40 , G11C16/04 , G11C17/14 , G11C29/20 , G11C29/56 , G11C29/56008 , G11C2029/0401 , G11C2029/1208 , G11C2029/5606
摘要： Fault diagnosis techniques for non-volatile memories are disclosed. The techniques are based on deterministic partitioning of rows and/or columns of cells in a memory array. Through deterministic partitioning, signatures are generated for identification of failing rows, columns and single memory cells. A row/column selector or a combined row and column selector may be built on chip to implement the process of deterministic partitioning. An optional shadow register may be used to transfer obtained signatures to an automated test equipment (ATE).
摘要翻译：公开了用于非易失性存储器的故障诊断技术。这些技术基于对存储器阵列中的单元格行和/或列的确定性划分。通过确定性分区，生成签名以识别失败的行，列和单个存储单元。行/列选择器或组合的行和列选择器可以构建在芯片上以实现确定性分区的过程。可以使用可选的影子寄存器将获得的签名转移到自动测试设备（ATE）。

7. 发明申请

WO2008100520A3 LOW POWER SCAN TESTING TECHNIQUES AND APPARATUS 审中-公开
标题翻译：低功耗扫描测试技术与设备
公开(公告)号：WO2008100520A3
公开(公告)日：2008-12-11
申请号：PCT/US2008001866
申请日：2008-02-12
申请人： MENTOR GRAPHICS CORP , LIN XIJIANG , CZYSZ DARIUSZ , KASSAB MARK , MRUGALSKI GRZEGORZ , RAJSKI JANUSZ , TYSZER JERZY
发明人： LIN XIJIANG , CZYSZ DARIUSZ , KASSAB MARK , MRUGALSKI GRZEGORZ , RAJSKI JANUSZ , TYSZER JERZY
IPC分类号： G06F11/00
CPC分类号： G01R31/318575
摘要： Disclosed below are representative embodiments of methods, apparatus, and systems used to reduce power consumption during integrated circuit testing. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures {e.g., an embedded deterministic test ("EDT") architecture). Among the disclosed embodiments are integrated circuits having programmable test stimuli selectors, programmable scan enable circuits, programmable clock enable circuits, programmable shift enable circuits, and/or programmable reset enable circuits. Exemplary test pattern generation methods that can be used to generate test patterns for use with any of the disclosed embodiments are also disclosed.
摘要翻译：下面公开了用于在集成电路测试期间降低功耗的方法，设备和系统的代表性实施例。所公开的技术的实施例可以用于提供低功率测试方案并且可以与各种压缩硬件体系结构（例如，嵌入式确定性测试（“EDT”体系结构））集成。在所公开的实施例中，具有可编程测试激励选择器，可编程扫描使能电路，可编程时钟使能电路，可编程移位使能电路和/或可编程复位使能电路的集成电路。还公开了可以用于生成供任何所公开的实施例使用的测试模式的示例性测试模式生成方法。

8. 发明申请

WO2010102228A1 COMPRESSION BASED ON DETERMINISTIC VECTOR CLUSTERING OF INCOMPATIBLE TEST CUBES 审中-公开
标题翻译：基于不确定性测试结果的确定矢量聚类的压缩
公开(公告)号：WO2010102228A1
公开(公告)日：2010-09-10
申请号：PCT/US2010/026392
申请日：2010-03-05
申请人： MENTOR GRAPHICS CORPORATION , MRUGALSKI, Grzegorz , MUKHERJEE, Nilanjan , RAJSKI, Janusz , CZYSZ, Dariusz , TYSZER, Jerzy
发明人： MRUGALSKI, Grzegorz , MUKHERJEE, Nilanjan , RAJSKI, Janusz , CZYSZ, Dariusz , TYSZER, Jerzy
IPC分类号： G01R31/3185 , G01R31/319
CPC分类号： G01R31/31921 , G01R31/318547
摘要： The test data compression scheme is based on deterministic vector clustering. Test cubes that feature many similar specified bits are merged into a parent pattern in the presence of conflicts. The parent pattern along with a control pattern and incremental patterns representing conflicting bits are encoded efficiently. A tri-modal decompressor may be used to decompress the test data.
摘要翻译：测试数据压缩方案基于确定性向量聚类。在存在冲突的情况下，具有许多类似指定位的测试立方体将合并到父模式中。父模式以及表示冲突位的控制模式和增量模式被有效地编码。三模式解压缩器可用于解压缩测试数据。

9. 发明申请

WO2009039316A2 FAULT DIAGNOSIS IN A MEMORY BIST ENVIRONMENT 审中-公开
标题翻译：记忆环境中的故障诊断
公开(公告)号：WO2009039316A2
公开(公告)日：2009-03-26
申请号：PCT/US2008/076911
申请日：2008-09-18
申请人： MENTOR GRAPHICS CORPORATION , MUKHERJEE, Nilanjan , POGIEL, Artur , RAJSKI, Janusz , TYSZER, Jerzy
发明人： MUKHERJEE, Nilanjan , POGIEL, Artur , RAJSKI, Janusz , TYSZER, Jerzy
IPC分类号： G06F11/25
CPC分类号： G11C29/56 , G11C29/40 , G11C29/44 , G11C29/56008 , G11C2029/1208
摘要： Disclosed are methods and devices for temporally compacting test response signatures of failed memory tests in a memory built-in self-test environment, to provide the ability to carry on memory built-in self-test operations even with the detection of multiple time related memory test failures. In some implementations of the invention, the compacted test response signatures are provided to an automated test equipment device along with memory location information. According to various implementations of the invention, an integrated circuit with embedded memory and a memory BIST controller also includes a linear feedback structure for use as a signature register that can temporally compact test response signatures from the embedded memory array during a test step of a memory test. In various implementations the integrated circuit may also include a failing words counter, a failing column indicator, and/or a failing row indicator to collect memory location information for a failing test response.
摘要翻译：公开的是用于在存储器内置自检环境中暂时压缩失败存储器测试的测试响应签名的方法和设备，以提供即使在检测多个时间相关存储器的情况下进行存储器内置自检操作的能力测试失败。在本发明的一些实施方案中，将压实的测试响应签名与存储器位置信息一起提供给自动测试设备设备。根据本发明的各种实现方式，具有嵌入式存储器和存储器BIST控制器的集成电路还包括用作签名寄存器的线性反馈结构，其可以在存储器的测试步骤期间临时压缩来自嵌入式存储器阵列的测试响应签名测试。在各种实现中，集成电路还可以包括故障字计数器，故障列指示符和/或故障行指示符以收集故障测试响应的存储器位置信息。

10. 发明申请

WO2008100520A2 LOW POWER SCAN TESTING TECHNIQUES AND APPARATUS 审中-公开
标题翻译：低功率扫描测试技术和设备
公开(公告)号：WO2008100520A2
公开(公告)日：2008-08-21
申请号：PCT/US2008/001866
申请日：2008-02-12
申请人： MENTOR GRAPHICS CORPORATION , LIN, Xijiang , CZYSZ, Dariusz , KASSAB, Mark , MRUGALSKI, Grzegorz , RAJSKI, Janusz , TYSZER, Jerzy
发明人： LIN, Xijiang , CZYSZ, Dariusz , KASSAB, Mark , MRUGALSKI, Grzegorz , RAJSKI, Janusz , TYSZER, Jerzy
IPC分类号： G01R31/02 , G06F19/00
CPC分类号： G01R31/318575
摘要： Disclosed below are representative embodiments of methods, apparatus, and systems used to reduce power consumption during integrated circuit testing. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures {e.g., an embedded deterministic test ("EDT") architecture). Among the disclosed embodiments are integrated circuits having programmable test stimuli selectors, programmable scan enable circuits, programmable clock enable circuits, programmable shift enable circuits, and/or programmable reset enable circuits. Exemplary test pattern generation methods that can be used to generate test patterns for use with any of the disclosed embodiments are also disclosed.
摘要翻译：以下公开了用于在集成电路测试期间降低功耗的方法，装置和系统的代表性实施例。所公开的技术的实施例可以用于提供低功率测试方案，并且可以与各种压缩硬件架构（例如，嵌入式确定性测试（“EDT”）架构）集成。在所公开的实施例中，具有可编程测试刺激选择器，可编程扫描使能电路，可编程时钟使能电路，可编程移位使能电路和/或可编程复位使能电路的集成电路。还公开了可用于产生用于与所公开的任何实施例一起使用的测试图案的示例性测试图案生成方法。

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