专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2020171800A1 RADIO EQUIPMENT TEST DEVICE 审中-公开
公开(公告)号：WO2020171800A1
公开(公告)日：2020-08-27
申请号：PCT/US2019/018546
申请日：2019-02-19
申请人： MENTOR GRAPHICS CORPORATION
发明人： VIERIMAA, Kari , VALASMA, Harri
IPC分类号： H04B17/17 , G01R29/10 , H04B17/29 , G01R29/105 , H04B17/26
摘要： A single radio equipment test device (TA) comprising: a control unit (CT) for testing a plurality of antennas, e.g., an antenna array, the control unit (CT) comprising a first interface (I1) to operatively couple the control unit (CT) to an antenna under test (AUT), preferably arranged in a test chamber (TC), the control unit (CT) comprising a second interface (I1) to operatively couple the control unit (CT) to a reference antenna (REA), preferably also arranged in said test chamber (TC), wherein the control unit (CT) serves for controlling and/or monitoring the antenna under test (AUT) and the reference antenna (REA).

2. 发明申请

WO2020167753A1 BIDIRECTIONAL SCAN CELLS FOR SINGLE-PATH REVERSIBLE SCAN CHAINS 审中-公开
公开(公告)号：WO2020167753A1
公开(公告)日：2020-08-20
申请号：PCT/US2020/017642
申请日：2020-02-11
申请人： MENTOR GRAPHICS CORPORATION
发明人： CHENG, Wu-Tung , HUANG, Yu
IPC分类号： G11C29/32 , G01R31/3185
摘要： A circuit comprises a plurality of scan chains. The plurality of scan chains comprisies bidirectional scan cells. Each of the bidirectional scan cells comprises two serial input-output ports serving as either a serial data input port or a serial data output port based on a control signal. Each of the plurality of scan chains is configured to perform a shift operation in either a first direction or a second direction based on the control signal. The first direction is opposite to the second direction.

3. 发明申请

WO2020077086A1 APPARATUS, SYSTEM AND METHOD FOR TESTING RADIO EQUIPMENT 审中-公开
公开(公告)号：WO2020077086A1
公开(公告)日：2020-04-16
申请号：PCT/US2019/055623
申请日：2019-10-10
申请人： MENTOR GRAPHICS CORPORATION
发明人： VIERIMAA, Kari
IPC分类号： H04W24/00 , H04W24/06 , H04W24/08
摘要： A method of testing radio equipment (BBU, RRH, UE), comprising: Receiving (S0), by way of a radio channel test apparatus (10), a baseband signal representing I/Q data of one or more radio channels, Processing (S1), by way of the radio channel test apparatus (10), the baseband signal representing I/Q data according to one or more radio channel models, Transmitting (S2), by way of the radio channel test apparatus (10), the processed baseband data representing I/Q data to a radio equipment under test.

4. 发明申请

WO2012150970A1 TEST SCHEDULING WITH PATTERN-INDEPENDENT TEST ACCESS MECHANISM 审中-公开
标题翻译：具有独特的测试访问机制的测试调度
公开(公告)号：WO2012150970A1
公开(公告)日：2012-11-08
申请号：PCT/US2012/021575
申请日：2012-01-17
申请人： MENTOR GRAPHICS CORPORATION , RAJSKI, Janusz , KASSAB, Mark, A. , GRZEGORZ, Mrugalski , MUKHERJEE, Nilanjan , JANICKI, Jakub , TYSZER, Jerzy , DUTTA, Avijit
发明人： RAJSKI, Janusz , KASSAB, Mark, A. , GRZEGORZ, Mrugalski , MUKHERJEE, Nilanjan , JANICKI, Jakub , TYSZER, Jerzy , DUTTA, Avijit
IPC分类号： G06F11/263 , G01R31/3183 , G01R31/319 , G06F11/07 , G06F11/22
CPC分类号： H04L43/50 , G01R31/318335 , G06F11/263
摘要： Disclosed are representative embodiments of methods, apparatus, and systems for test scheduling for testing a plurality of cores in a system on circuit. Test data are encoded to derive compressed test patterns that require small numbers of core input channels. Core input/output channel requirement information for each of the compressed test patterns is determined accordingly. The compressed patterns are grouped into test pattern classes. The formation of the test pattern classes is followed by allocation circuit input and output channels and test application time slots that may comprise merging complementary test pattern classes into clusters that can work with a particular test access mechanism. The test access mechanism may be designed independent of the test data.
摘要翻译：公开了用于在电路系统中测试多个核的测试调度的方法，装置和系统的代表性实施例。编码测试数据以导出需要少量核心输入通道的压缩测试模式。相应地确定每个压缩测试图案的核心输入/输出通道要求信息。压缩的模式被分组成测试模式类。测试模式类的形成之后是分配电路输入和输出通道以及测试应用时隙，其可以包括将互补测试模式类合并成可以与特定测试访问机制一起工作的集群。可以独立于测试数据设计测试访问机制。

5. 发明申请

WO2011046989A1 GENERALIZATION OF SHOT DEFINITIONS FOR MASK AND WAFER PATTERNING TOOLS 审中-公开
标题翻译：用于掩模和波纹图案工具的SHOT定义的一般化
公开(公告)号：WO2011046989A1
公开(公告)日：2011-04-21
申请号：PCT/US2010/052410
申请日：2010-10-12
申请人： MENTOR GRAPHICS CORPORATION , SAHOURIA, Emile, Y. , SCHULZE, Steffen, F.
发明人： SAHOURIA, Emile, Y. , SCHULZE, Steffen, F.
IPC分类号： H01J37/317 , G03F7/20 , G03F1/00
CPC分类号： G03F7/2063 , B82Y10/00 , B82Y40/00 , G03F1/50 , G03F1/76 , G03F1/78 , G03F7/2045 , G03F7/70466 , H01J37/3174 , H01L21/0274 , H01L21/26
摘要： The invention relates to techniques for reducing the number of shots required by a radiation beam writing tool to write a pattern, such as fractured layout design, onto a substrate. One or more apertures are employed by a radiation beam writing tool to write a desired pattern onto a substrate using L- shaped images, T-shaped images, or some combination of both. For example, some implementations of the invention may analyze the atomic shapes in a pattern to identify adjacent rectangular atomic shapes that can be combined into an L -shape or a T -shape. The radiation beam writing tool can then write these atomic shapes onto a substrate in a single shot by forming an image on the substrate corresponding to the L -shape or T -shape.
摘要翻译：本发明涉及用于减少辐射束写入工具所需的镜头数目的技术，以将诸如断裂布局设计的图案写入衬底。辐射束写入工具使用一个或多个孔，以使用L形图像，T形图像或两者的某种组合将期望的图案写入基板。例如，本发明的一些实现可以分析图案中的原子形状以识别可以组合成L形或T形的相邻矩形原子形状。然后，辐射束写入工具可以通过在与L形或T形形状相对应的衬底上形成图像，将这些原子形状在单次照射中写入到衬底上。

6. 发明申请

WO2010124148A1 AT-SPEED SCAN TESTING WITH CONTROLLED SWITCHING ACTIVITY 审中-公开
标题翻译：具有控制切换活动的AT速度扫描测试
公开(公告)号：WO2010124148A1
公开(公告)日：2010-10-28
申请号：PCT/US2010/032136
申请日：2010-04-22
申请人： MENTOR GRAPHICS CORPORATION , RAJSKI, Janusz , MOGHADDAM, Elham, K. , MUKHERJEE, Nilanjan , KASSAB, Mark, A. , XIJIANG, Lin
发明人： RAJSKI, Janusz , MOGHADDAM, Elham, K. , MUKHERJEE, Nilanjan , KASSAB, Mark, A. , XIJIANG, Lin
IPC分类号： G01R31/3185
CPC分类号： G01R31/318547 , G01R31/318575
摘要： Test patterns for at-speed scan tests are generated by filling unspecified bits of test cubes with functional background data. Functional background data are scan cell values observed when switching activity of the circuit under test is near a steady state. Hardware implementations in EDT (embedded deterministic test) environment are also disclosed.
摘要翻译：通过用功能背景数据填充测试立方体的未指定位来生成速度扫描测试的测试模式。功能背景数据是当被测电路的开关活动接近稳定状态时观察到的扫描单元值。还公布了EDT（嵌入式确定性测试）环境中的硬件实现。

7. 发明申请

WO2010102235A1 FAULT DIAGNOSIS FOR NON-VOLATILE MEMORIES 审中-公开
标题翻译：故障诊断非易失性存储器
公开(公告)号：WO2010102235A1
公开(公告)日：2010-09-10
申请号：PCT/US2010/026403
申请日：2010-03-05
申请人： MENTOR GRAPHICS CORPORATION , MUKHERJEE, Nilanjan , POGIEL, Artur , RAJSKI, Janusz , TYSZER, Jerzy
发明人： MUKHERJEE, Nilanjan , POGIEL, Artur , RAJSKI, Janusz , TYSZER, Jerzy
IPC分类号： G11C29/20 , G11C29/40 , G11C29/56
CPC分类号： G11C29/40 , G11C16/04 , G11C17/14 , G11C29/20 , G11C29/56 , G11C29/56008 , G11C2029/0401 , G11C2029/1208 , G11C2029/5606
摘要： Fault diagnosis techniques for non-volatile memories are disclosed. The techniques are based on deterministic partitioning of rows and/or columns of cells in a memory array. Through deterministic partitioning, signatures are generated for identification of failing rows, columns and single memory cells. A row/column selector or a combined row and column selector may be built on chip to implement the process of deterministic partitioning. An optional shadow register may be used to transfer obtained signatures to an automated test equipment (ATE).
摘要翻译：公开了用于非易失性存储器的故障诊断技术。这些技术基于对存储器阵列中的单元格行和/或列的确定性划分。通过确定性分区，生成签名以识别失败的行，列和单个存储单元。行/列选择器或组合的行和列选择器可以构建在芯片上以实现确定性分区的过程。可以使用可选的影子寄存器将获得的签名转移到自动测试设备（ATE）。

8. 发明申请

WO2009105788A2 IMPROVING THE PERFORMANCE OF SIGNATURE BASED DIAGNOSIS FOR LOGIC BIST 审中-公开
标题翻译：改进基于签名的LOGIC BIST诊断的性能
公开(公告)号：WO2009105788A2
公开(公告)日：2009-08-27
申请号：PCT/US2009/034933
申请日：2009-02-23
申请人： MENTOR GRAPHICS CORPORATION , CHENG, Wu-tung , SHARMA, Manish , RINDERKNECHT, Thomas, H.
发明人： CHENG, Wu-tung , SHARMA, Manish , RINDERKNECHT, Thomas, H.
IPC分类号： G01R31/3185
CPC分类号： G06F11/277 , G01R31/318547
摘要： Techniques are disclosed for reducing the set of initial candidates in signature based diagnosis methodology. These techniques are based on a unique way of making optimum use of information from logic back-cone tracing along with equations that describe the test response compactor.
摘要翻译：公开了用于减少基于签名的诊断方法中的初始候选者的集合的技术。这些技术基于一种独特的方式，从逻辑后锥跟踪中最佳地利用信息以及描述测试响应压实器的方程式。

9. 发明申请

WO2009036133A1 FRACTURE SHOT COUNT REDUCTION 审中-公开
标题翻译：断裂拍摄减少
公开(公告)号：WO2009036133A1
公开(公告)日：2009-03-19
申请号：PCT/US2008/075968
申请日：2008-09-11
申请人： MENTOR GRAPHICS CORPORATION , SAHOURIA, Emile , WANG, Jianlin
发明人： SAHOURIA, Emile , WANG, Jianlin
IPC分类号： G03F1/14 , G03F7/20
CPC分类号： G03F7/70433 , G03F1/36 , G03F1/68
摘要： Techniques are described for reducing the number of shots in a fractured layout design. Each polygon in a layout design is examined for "jogs." For each identified jog, the surrounding region is examined to determine if there is an opposing jog or parallel edge that can be aligned with the identified jog. The surrounding region then is examined for any polygon features, such as edges or vertices, which might restrict or prevent the alignment of the identified jog with the opposing jog or edge. If the identified jog can be aligned with an opposing jog or edge without violating a specified alignment constraint, then those jogs are deemed an alignable jog pair. Next, one or more of the alignable jog pairs is selected for alignment. The alignable jog pairs may be selected for alignment based upon their impact on the size of the polygon when aligned. Once one or more of the alignable jog pairs have been selected, then the layout design data will be modified to align the selected jog pairs.
摘要翻译：描述了用于减少断裂布局设计中的拍摄张数的技术。检查布局设计中的每个多边形的“慢跑”。对于每个识别的点动，检查周围区域以确定是否存在可以与所识别的点动对准的相对的点动或平行边缘。然后检查周围区域的任何多边形特征，例如边缘或顶点，其可以限制或阻止所识别的慢跑与相对的点动或边缘的对准。如果识别的点动可以与相对的点动或边缘对齐，而不违反指定的对准约束，则这些点动被认为是可对准的点对。接下来，选择一个或多个可对准的点对对进行对准。可以选择可对准的点对对，以便在对齐时基于它们对多边形的尺寸的影响进行对准。一旦选择了一个或多个可对准的点对对，则将修改布局设计数据以对齐所选择的点对。

10. 发明申请

WO2008063651A2 MODEL-BASED DESIGN VERIFICATION 审中-公开
标题翻译：基于模型的设计验证
公开(公告)号：WO2008063651A2
公开(公告)日：2008-05-29
申请号：PCT/US2007/024303
申请日：2007-11-20
申请人： MENTOR GRAPHICS CORPORATION , PIKUS, Fedor, G. , ABERCROMBIE, David, A.
发明人： PIKUS, Fedor, G. , ABERCROMBIE, David, A.
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： An analog design-rule-check tool analyzes a microdevice design, such as an integrated circuit design, to identify occurrences of geometric elements that share a specified relationship. When the tool identifies such an occurrence of these geometric elements, it will associate or "cluster" these geometric elements together into an identifiable unit. For specified "clusters" of geometric elements, the analog design-rule-check tool will then determine the value of a measurement or measurements required by a user. Once the analog design-rule-check tool has determined the necessary measurement values, it will use those values to evaluate the function describing a model.
摘要翻译：模拟设计规则检查工具分析微设备设计（例如集成电路设计），以识别出共享指定关系的几何元素的出现。当工具识别出这些几何元素出现时，它会将这些几何元素关联或“聚类”成一个可识别的单元。对于指定的几何元素“簇”，模拟设计规则检查工具将确定用户所需的一个或多个测量值。一旦模拟设计规则检查工具确定了必要的测量值，它将使用这些值来评估描述模型的函数。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式