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1. 发明申请

WO2008100520A2 LOW POWER SCAN TESTING TECHNIQUES AND APPARATUS 审中-公开
标题翻译：低功率扫描测试技术和设备
公开(公告)号：WO2008100520A2
公开(公告)日：2008-08-21
申请号：PCT/US2008/001866
申请日：2008-02-12
申请人： MENTOR GRAPHICS CORPORATION , LIN, Xijiang , CZYSZ, Dariusz , KASSAB, Mark , MRUGALSKI, Grzegorz , RAJSKI, Janusz , TYSZER, Jerzy
发明人： LIN, Xijiang , CZYSZ, Dariusz , KASSAB, Mark , MRUGALSKI, Grzegorz , RAJSKI, Janusz , TYSZER, Jerzy
IPC分类号： G01R31/02 , G06F19/00
CPC分类号： G01R31/318575
摘要： Disclosed below are representative embodiments of methods, apparatus, and systems used to reduce power consumption during integrated circuit testing. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures {e.g., an embedded deterministic test ("EDT") architecture). Among the disclosed embodiments are integrated circuits having programmable test stimuli selectors, programmable scan enable circuits, programmable clock enable circuits, programmable shift enable circuits, and/or programmable reset enable circuits. Exemplary test pattern generation methods that can be used to generate test patterns for use with any of the disclosed embodiments are also disclosed.
摘要翻译：以下公开了用于在集成电路测试期间降低功耗的方法，装置和系统的代表性实施例。所公开的技术的实施例可以用于提供低功率测试方案，并且可以与各种压缩硬件架构（例如，嵌入式确定性测试（“EDT”）架构）集成。在所公开的实施例中，具有可编程测试刺激选择器，可编程扫描使能电路，可编程时钟使能电路，可编程移位使能电路和/或可编程复位使能电路的集成电路。还公开了可用于产生用于与所公开的任何实施例一起使用的测试图案的示例性测试图案生成方法。

2. 发明申请

WO2009137727A1 SCAN CELL USE WITH REDUCED POWER CONSUMPTION 审中-公开
标题翻译：扫描电池使用减少功耗
公开(公告)号：WO2009137727A1
公开(公告)日：2009-11-12
申请号：PCT/US2009/043214
申请日：2009-05-07
申请人： MENTOR GRAPHICS CORPORATION , LIN, Xijiang , HUANG, Yu , RAJSKI, Janusz
发明人： LIN, Xijiang , HUANG, Yu , RAJSKI, Janusz
IPC分类号： G01R31/3185
CPC分类号： G01R31/318575
摘要： Selective blocking is applied to discrete segments of scan chains in the integrated circuit device. In some implementations, locking components associated with the scan segments are selectively activated according to blocking data incorporated in test pattern data. In other implementations, selective blocking is applied to the scan cells identified as causing the highest power consumption. Selective incorporation of blocking components in an integrated circuit device is based on statistical estimation of scan cell transition rates. When the blocking components are enabled, pre-selected signal values are presented to the functional logic of the integrated circuit device. At the same time, propagation of output value transitions that may take place in the scan cells is prevented.
摘要翻译：选择性阻塞被应用于集成电路器件中的扫描链的离散段。在一些实施方式中，根据结合在测试图案数据中的阻塞数据来选择性地激活与扫描段相关联的锁定组件。在其他实现中，选择性阻塞被应用于被识别为导致最高功耗的扫描单元。在集成电路器件中选择性地并入阻塞元件是基于扫描电池转换速率的统计估计。当阻塞组件被使能时，预先选择的信号值被呈现给集成电路设备的功能逻辑。同时，可以防止在扫描单元中发生的输出值转换的传播。

3. 发明申请

WO2008100520A3 LOW POWER SCAN TESTING TECHNIQUES AND APPARATUS 审中-公开
标题翻译：低功耗扫描测试技术与设备
公开(公告)号：WO2008100520A3
公开(公告)日：2008-12-11
申请号：PCT/US2008001866
申请日：2008-02-12
申请人： MENTOR GRAPHICS CORP , LIN XIJIANG , CZYSZ DARIUSZ , KASSAB MARK , MRUGALSKI GRZEGORZ , RAJSKI JANUSZ , TYSZER JERZY
发明人： LIN XIJIANG , CZYSZ DARIUSZ , KASSAB MARK , MRUGALSKI GRZEGORZ , RAJSKI JANUSZ , TYSZER JERZY
IPC分类号： G06F11/00
CPC分类号： G01R31/318575
摘要： Disclosed below are representative embodiments of methods, apparatus, and systems used to reduce power consumption during integrated circuit testing. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures {e.g., an embedded deterministic test ("EDT") architecture). Among the disclosed embodiments are integrated circuits having programmable test stimuli selectors, programmable scan enable circuits, programmable clock enable circuits, programmable shift enable circuits, and/or programmable reset enable circuits. Exemplary test pattern generation methods that can be used to generate test patterns for use with any of the disclosed embodiments are also disclosed.
摘要翻译：下面公开了用于在集成电路测试期间降低功耗的方法，设备和系统的代表性实施例。所公开的技术的实施例可以用于提供低功率测试方案并且可以与各种压缩硬件体系结构（例如，嵌入式确定性测试（“EDT”体系结构））集成。在所公开的实施例中，具有可编程测试激励选择器，可编程扫描使能电路，可编程时钟使能电路，可编程移位使能电路和/或可编程复位使能电路的集成电路。还公开了可以用于生成供任何所公开的实施例使用的测试模式的示例性测试模式生成方法。

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