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1. 发明申请

WO2007126670A1 SUBSTRATE HAVING CONDUCTIVE TRACES ISOLATED BY LASER TO ALLOW ELECTRICAL INSPECTION 审中-公开
标题翻译：具有通过激光隔离的导电路径的基板允许电气检查
公开(公告)号：WO2007126670A1
公开(公告)日：2007-11-08
申请号：PCT/US2007/007111
申请日：2007-03-22
申请人： SANDISK CORPORATION , LIAO, Chih-Chin , TAKIAR, Hem , YU, Cheeman
发明人： LIAO, Chih-Chin , TAKIAR, Hem , YU, Cheeman
IPC分类号： H01L21/48
CPC分类号： H01L21/4846 , H01L2224/48091 , H01L2224/48227 , H05K1/117 , H05K3/242 , H05K2203/107 , H05K2203/162 , H05K2203/175 , H01L2924/00014
摘要： A semiconductor die substrate panel, and method of forming same, are disclosed wherein plating bars are severed for example by a laser after electroplating of the substrate. Severing the plating bars allows electrical testing of the substrate prior to attachment of electronic components.
摘要翻译：公开了一种半导体管芯衬底面板及其形成方法，其中电镀棒在电镀电镀之后例如通过激光切断。切割电镀棒允许在电子部件附着之前对基板进行电气测试。

2. 发明申请

WO2007079122A3 STRIP FOR INTEGRATED CIRCUIT PACKAGES HAVING A MAXIMIZED USABLE AREA 审中-公开
标题翻译：具有最大可用面积的集成电路封装的条带
公开(公告)号：WO2007079122A3
公开(公告)日：2007-09-07
申请号：PCT/US2006049379
申请日：2006-12-27
申请人： SANDISK CORP , TAKIAR HEM , THAVARAJAH MANICKAM , WANG KEN JIAN MING , LIAO CHIH-CHIN , MCKENZIE ANDRE , BHAGATH SHRIKAR , CHEN HAN-SHIAO , CHIU CHIN-TIEN
发明人： TAKIAR HEM , THAVARAJAH MANICKAM , WANG KEN JIAN MING , LIAO CHIH-CHIN , MCKENZIE ANDRE , BHAGATH SHRIKAR , CHEN HAN-SHIAO , CHIU CHIN-TIEN
IPC分类号： H01L21/56 , H01L23/495 , H01L23/544
CPC分类号： H01L23/544 , H01L21/4857 , H01L21/50 , H01L21/561 , H01L23/49565 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/85 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2223/54486 , H01L2224/2929 , H01L2224/293 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/83801 , H01L2224/83851 , H01L2224/85 , H01L2224/97 , H01L2225/06568 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/0102 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/0781 , H01L2924/12041 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , Y10T29/49117 , H01L2924/00012 , H01L2924/3512 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A strip (40) on which a plurality of integrated circuit package outlines (42) may be fabricated 'within a plurality of process tools. The strip includes one or more fiducial, notches (44) and/or guide pin notches (46) formed in an outer edge of the strip. The one or more fiducial and/or guide pin notches allow a position of the strip to be identified within at least one process tool of the plurality of process tools. By forming the notches in the outer periphery of the strip, the usable area on the strip on which integrated circuit package outlines may be formed is increased. The strip may alternatively include conventional fiducial and/or guide pin holes (24, 26), with the molding compound applied at least partially around the holes on one or more sides of the strip. The strip may further alternatively include fiducial holes (92) filled with a translucent material that provides stability to the strip while allowing the strip to be used with an optical recognition sensor.
摘要翻译：在多个处理工具中可在其上制造多个集成电路封装轮廓（42）的条（40）。该条带包括形成在条的外边缘中的一个或多个基准，凹口（44）和/或引导销凹口（46）。一个或多个基准和/或引导销凹口允许在多个处理工具的至少一个处理工具内识别条带的位置。通过在带的外周形成切口，可以形成集成电路封装轮廓的带上的可用区域。替代地，带可以包括常规的基准和/或引导销孔（24,26），其中模制化合物至少部分地围绕带的一侧或多侧上的孔施加。带还可以包括填充有半透明材料的基准孔（92），其为条带提供稳定性，同时允许带与光学识别传感器一起使用。

3. 发明申请

WO2007079122A2 STRIP FOR INTEGRATED CIRCUIT PACKAGES HAVING A MAXIMIZED USABLE AREA 审中-公开
标题翻译：具有最大可用面积的集成电路封装的条带
公开(公告)号：WO2007079122A2
公开(公告)日：2007-07-12
申请号：PCT/US2006/049379
申请日：2006-12-27
申请人： SANDISK CORPORATION , TAKIAR, Hem , THAVARAJAH, Manickam , WANG, Ken Jian, Ming , LIAO, Chih-chin , MCKENZIE, Andre , BHAGATH, Shrikar , CHEN, Han-shiao , CHIU, Chin- Tien
发明人： TAKIAR, Hem , THAVARAJAH, Manickam , WANG, Ken Jian, Ming , LIAO, Chih-chin , MCKENZIE, Andre , BHAGATH, Shrikar , CHEN, Han-shiao , CHIU, Chin- Tien
CPC分类号： H01L23/544 , H01L21/4857 , H01L21/50 , H01L21/561 , H01L23/49565 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/85 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2223/54486 , H01L2224/2929 , H01L2224/293 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/83801 , H01L2224/83851 , H01L2224/85 , H01L2224/97 , H01L2225/06568 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/0102 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/0781 , H01L2924/12041 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , Y10T29/49117 , H01L2924/00012 , H01L2924/3512 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A strip on which a plurality of integrated circuit package outlines may be fabricated within a plurality of process tools. The strip includes one or more fiducial, notches and/or guide pin notches formed in an outer edge of the strip. The one or more fiducial and/or guide pin notches allow a position of the strip to be identified within at least one process tool of the plurality of process tools. By forming the notches in the outer periphery of the strip, the usable area on the strip on which integrated circuit package outlines may be formed is increased. The strip may alternatively include conventional fiducial and/or guide pin holes, with the molding compound applied at least partially around the holes on one or more sides of the strip. The strip may further alternatively include fiducial holes filled with a translucent material that provides stability to the strip while allowing the strip to be used with an optical recognition sensor.
摘要翻译：其上可以在多个处理工具内制造多个集成电路封装轮廓的条带。带材包括形成在带材的外边缘中的一个或多个基准，凹口和/或导向销切口。一个或多个基准和/或引导销凹口允许在多个处理工具的至少一个处理工具内识别条带的位置。通过在带的外周形成切口，可以形成集成电路封装轮廓的带上的可用区域。条带可替代地包括常规的基准和/或引导销孔，模制化合物至少部分地围绕带的一侧或多侧上的孔施加。条带还可以包括填充有半透明材料的基准孔，其为条带提供稳定性，同时允许条带与光学识别传感器一起使用。

4. 发明申请

WO2007011511A2 DIE PACKAGE WITH ASYMMETRIC LEADFRAME CONNECTION 审中-公开
标题翻译：具有不对称铅球连接的模具包装
公开(公告)号：WO2007011511A2
公开(公告)日：2007-01-25
申请号：PCT/US2006025302
申请日：2006-06-28
申请人： SANDISK CORP , LEE MING HSUN , LIAO CHIH-CHIN , YU CHEEMEN , TAKIAR HEM
发明人： LEE MING HSUN , LIAO CHIH-CHIN , YU CHEEMEN , TAKIAR HEM
IPC分类号： H01L23/495
CPC分类号： H01L23/4951 , H01L23/49551 , H01L23/49558 , H01L23/49575 , H01L24/48 , H01L24/73 , H01L2224/05553 , H01L2224/32145 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/49109 , H01L2224/73265 , H01L2225/06562 , H01L2924/00014 , H01L2924/01087 , H01L2924/10161 , H01L2924/14 , H01L2924/181 , H01L2924/18165 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A leadframe for a semiconductor package is disclosed including electrical leads which extend from one side of the leadframe to an opposite side of the leadframe, where electrical connection may be made with the semiconductor die at the second side of the leadframe. The semiconductor die may be supported on the leads extending across the leadframe. The package may further include a spacer layer affixed to the electrical leads to fortify the semiconductor package and to prevent exposure of the electrical leads during the molding of the package.
摘要翻译：公开了一种用于半导体封装的引线框架，其包括从引线框架的一侧延伸到引线框架的相反侧的电引线，其中可以在引线框架的第二侧与半导体管芯进行电连接。半导体管芯可以被支撑在延伸穿过引线框架的引线上。该封装可以进一步包括固定到电引线的间隔层，以加固半导体封装并防止在引线封装成型期间电引线的暴露。

5. 发明申请

WO2007136651A3 SEMICONDUCTOR DEVICE WITH A DISTRIBUTED PLATING PATTERN 审中-公开
标题翻译：具有分布式电镀图案的半导体器件
公开(公告)号：WO2007136651A3
公开(公告)日：2008-03-13
申请号：PCT/US2007011728
申请日：2007-05-16
申请人： SANDISK CORP , LIAO CHIH-CHIN , CHEN HAN-SHIAO , CHIU CHIN-TIEN , YU CHEEMEN , TAKIAR HEM
发明人： LIAO CHIH-CHIN , CHEN HAN-SHIAO , CHIU CHIN-TIEN , YU CHEEMEN , TAKIAR HEM
IPC分类号： H01L23/498
CPC分类号： H01L23/49838 , H01L23/3121 , H01L2924/0002 , H01L2924/1433 , H05K1/0271 , H05K3/108 , H05K3/28 , H05K2201/0373 , H05K2201/09736 , H01L2924/00
摘要： A substrate, and a semiconductor die package formed therefrom, are disclosed which include a distributed plating pattern for reducing mechanical stress on the semiconductor die. The substrate according to embodiments of the invention may include traces and contact pads plated in a double image plating process. Additionally, the substrate may include dummy plating areas including plating material. The plated vias and/or traces and the plating material within the dummy plating areas provide a plating pattern which is evenly distributed across the surface of the substrate. The even distribution of the plating pattern prevents peaks and valleys in the finished substrate.
摘要翻译：公开了一种基板和由其形成的半导体管芯封装，其包括用于减小半导体管芯上的机械应力的分布电镀图案。根据本发明的实施例的衬底可以包括以双映像电镀工艺电镀的迹线和接触焊盘。此外，基板可以包括包括电镀材料的虚拟电镀区域。电镀通孔和/或迹线以及虚拟电镀区域内的电镀材料提供均匀分布在基板表面上的电镀图案。电镀图案的均匀分布防止成品基板中的峰和谷。

6. 发明申请

WO2007056013A2 HIGH DENSITY THREE DIMENSIONAL SEMICONDUCTOR DIE PACKAGE 审中-公开
标题翻译：高密度三维半导体芯片封装
公开(公告)号：WO2007056013A2
公开(公告)日：2007-05-18
申请号：PCT/US2006/042664
申请日：2006-11-01
申请人： SANDISK CORPORATION , YU, Cheemen , LIAO, Chih-Chin , TAKIAR, Hem
发明人： YU, Cheemen , LIAO, Chih-Chin , TAKIAR, Hem
CPC分类号： H01L25/0657 , G11C5/02 , G11C5/04 , G11C5/143 , G11C8/12 , H01L21/485 , H01L23/5382 , H01L25/50 , H01L2225/06527 , H01L2225/06579 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor package is disclosed including a plurality semiconductor die mounted on stacked and bonded layers of substrate, for example polyimide tape used in tape automated bonding processes. The tape may have a plurality of repeating patterns of traces and contact pads formed thereon. The traces each include aligned interconnect pads on the respective top and bottom surfaces of the substrate for bonding the traces of one pattern to the traces of another pattern after the patterns have been singulated from the substrate, aligned and stacked. Semiconductor die such as flash memory and a controller die are mounted on the traces of the respective patterns on the substrate. In order for the controller die to uniquely address a specific flash memory die in the stack, a group of traces on each substrate supporting the memory die are used as address pins and punched in a unique layout relative to the layout of the traces other substrates. By providing each flash memory semiconductor die on a substrate with a unique layout of address traces, each memory die may be selectively addressed by the controller die.
摘要翻译：公开了一种半导体封装，其包括安装在基板的堆叠和接合层上的多个半导体管芯，例如用于带自动接合工艺中的聚酰亚胺带。该带可以具有形成在其上的迹线和接触垫的多个重复图案。每个迹线包括在衬底的相应顶部和底部表面上的对准的互连焊盘，用于在图案从衬底单片化，对准和堆叠之后，将一个图案的迹线结合到另一个图案的迹线。诸如闪存和控制器管芯的半导体管芯安装在衬底上的各个图案的迹线上。为了使控制器裸片唯一地寻址堆叠中的特定闪存裸片，将支持存储器裸片的每个衬底上的一组迹线用作地址引脚并且以相对于其他衬底的布局布局的独特布局进行冲压。通过在衬底上为每个快闪存储器半导体管芯提供唯一的地址迹线布局，每个存储器管芯可以由控制器管芯选择性寻址。

7. 发明申请

WO2013007029A1 CHIP-ON-PACKAGE STRUCTURE FOR MULTIPLE DIE STACKS 审中-公开
标题翻译：多芯片堆叠芯片封装结构
公开(公告)号：WO2013007029A1
公开(公告)日：2013-01-17
申请号：PCT/CN2011/077134
申请日：2011-07-14
申请人： SANDISK SEMICONDUCTOR (SHANGHAI) CO., LTD. , SANDISK INFORMATION TECHNOLOGY (SHANGHAI) CO., LTD. , LIAO, Chih Chin , CHIU, Chin-Tien , YU, Cheeman , UPADHYAYULA, Suresh Kumar , LI, Wen Cheng , LU, Zhong
发明人： LIAO, Chih Chin , CHIU, Chin-Tien , YU, Cheeman , UPADHYAYULA, Suresh Kumar , LI, Wen Cheng , LU, Zhong
IPC分类号： H01L25/065 , H01L25/16 , H01L25/18 , H01L25/00
CPC分类号： H01L25/0657 , H01L24/73 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2224/49171 , H01L2224/73265 , H01L2225/06562 , H01L2924/01322 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： A multi-die semiconductor device (100) is disclosed. The device (100) may include one or more first-sized dies on a substrate (104) and one or more second-sized dies (126) affixed over the one or more first-sized dies. The second-sized die (126) may have a larger footprint than the first-sized die. An internal molding compound (120) may be provided on the substrate (104) having a footprint the same size as the second-sized die (126). The second-sized die (126) may be supported on the internal molding compound (120). Thereafter, the first and second-sized dies and the internal molding compound (120) may be encapsulated in an external molding compound.
摘要翻译：公开了一种多芯片半导体器件（100）。装置（100）可以包括在一个或多个第一尺寸的模具上的衬底（104）上的一个或多个第一尺寸的模具和一个或多个第二尺寸的模具（126）。第二尺寸的模具（126）可以具有比第一尺寸的模具更大的占地面积。可以在衬底（104）上提供内部模制化合物（120），其具有与第二尺寸模具（126）相同尺寸的足迹。第二尺寸的模具（126）可以被支撑在内部模塑料（120）上。此后，第一和第二尺寸的模具和内部模塑料（120）可以封装在外部模塑料中。

8. 发明申请

WO2008154371A3 TWO-SIDED SUBSTRATE LEAD CONNECTION FOR MINIMIZING KERF WIDTH ON A SEMICONDUCTOR SUBSTRATE PANEL 审中-公开
公开(公告)号：WO2008154371A3
公开(公告)日：2008-12-18
申请号：PCT/US2008/066100
申请日：2008-06-06
申请人： SANDISK CORPORATION , LIAO, Chih-chin , YE, Ning , YU, Cheeman , CHIEN, Jack, Chang , TAKIAR, Hem
发明人： LIAO, Chih-chin , YE, Ning , YU, Cheeman , CHIEN, Jack, Chang , TAKIAR, Hem
IPC分类号： H01L21/60
摘要： A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages.

9. 发明申请

WO2008154371A2 TWO-SIDED SUBSTRATE LEAD CONNECTION FOR MINIMIZING KERF WIDTH ON A SEMICONDUCTOR SUBSTRATE PANEL 审中-公开
标题翻译：用于在半导体衬底面板上最小化KERF宽度的两面衬底引线连接
公开(公告)号：WO2008154371A2
公开(公告)日：2008-12-18
申请号：PCT/US2008066100
申请日：2008-06-06
申请人： SANDISK CORP , LIAO CHIH-CHIN , YE NING , YU CHEEMAN , CHIEN JACK CHANG , TAKIAR HEM
发明人： LIAO CHIH-CHIN , YE NING , YU CHEEMAN , CHIEN JACK CHANG , TAKIAR HEM
IPC分类号： H01L21/60
CPC分类号： H01L23/49838 , H01L21/4846 , H01L21/561 , H01L23/3121 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01057 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/19105 , H05K3/0052 , H05K3/242 , H05K2201/09781 , H05K2203/175 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages.
摘要翻译：公开了半导体管芯衬底面板，其包括在面板上相邻的半导体封装轮廓之间的最小间隙宽度，同时确保电镀电端子的电隔离。通过减小相邻封装轮廓之间的边界的宽度，在用于半导体封装的衬底面板上获得额外的空间。

10. 发明申请

WO2008002836A2 STACKED, INTERCONNECTED SEMICONDUCTOR PACKAGES 审中-公开
标题翻译：堆叠互连半导体封装
公开(公告)号：WO2008002836A2
公开(公告)日：2008-01-03
申请号：PCT/US2007/071881
申请日：2007-06-22
申请人： SANDISK CORPORATION , YU, Cheeman , LIAO, Chih-chin , TAKIAR, Hem
发明人： YU, Cheeman , LIAO, Chih-chin , TAKIAR, Hem
IPC分类号： H01L25/11
CPC分类号： H01L25/105 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2225/0651 , H01L2225/06562 , H01L2225/1023 , H01L2225/1058 , H01L2225/1064 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： An electronic component is disclosed including a plurality of stacked semiconductor packages. A first such embodiment includes an internal connector for electrically coupling the stacked semiconductor packages. A second such embodiment includes an external connector for electrically coupling the stacked semiconductor packages.
摘要翻译：公开了一种电子部件，其包括多个堆叠的半导体封装。第一个这样的实施例包括用于电耦合堆叠的半导体封装的内部连接器。第二个这样的实施例包括用于电耦合堆叠的半导体封装的外部连接器。

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