专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2008154371A2 TWO-SIDED SUBSTRATE LEAD CONNECTION FOR MINIMIZING KERF WIDTH ON A SEMICONDUCTOR SUBSTRATE PANEL 审中-公开
标题翻译：用于在半导体衬底面板上最小化KERF宽度的两面衬底引线连接
公开(公告)号：WO2008154371A2
公开(公告)日：2008-12-18
申请号：PCT/US2008066100
申请日：2008-06-06
申请人： SANDISK CORP , LIAO CHIH-CHIN , YE NING , YU CHEEMAN , CHIEN JACK CHANG , TAKIAR HEM
发明人： LIAO CHIH-CHIN , YE NING , YU CHEEMAN , CHIEN JACK CHANG , TAKIAR HEM
IPC分类号： H01L21/60
CPC分类号： H01L23/49838 , H01L21/4846 , H01L21/561 , H01L23/3121 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01057 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/19105 , H05K3/0052 , H05K3/242 , H05K2201/09781 , H05K2203/175 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages.
摘要翻译：公开了半导体管芯衬底面板，其包括在面板上相邻的半导体封装轮廓之间的最小间隙宽度，同时确保电镀电端子的电隔离。通过减小相邻封装轮廓之间的边界的宽度，在用于半导体封装的衬底面板上获得额外的空间。

2. 发明申请

WO2008042657A2 METHODS OF FORMIMG A SINGLE LAYER SUBSTRATE FOR HIGH CAPACITY MEMORY CARDS 审中-公开
标题翻译：用于形成高容量存储卡的单层衬底的方法
公开(公告)号：WO2008042657A2
公开(公告)日：2008-04-10
申请号：PCT/US2007079450
申请日：2007-09-25
申请人： SANDISK CORP , YU CHEEMAN , TAKIAR HEM , LIAO CHIH-CHIN
发明人： YU CHEEMAN , TAKIAR HEM , LIAO CHIH-CHIN
IPC分类号： H01L23/498
CPC分类号： H01L21/4846 , H01L21/486 , H01L23/49827 , H01L2224/48091 , H01L2924/01078 , H01L2924/01079 , H01L2924/00014
摘要： Methods of forming a semiconductor package including a single-sided substrate are disclosed. In a first embodiment of the present invention, a substrate may include a conductive layer on a top surface of the substrate, i.e., on the same side of the substrate as where the die are mounted. In a second embodiment of the present invention, a substrate may include a conductive layer on a bottom of the substrate, i.e., on the opposite side of the substrate as where the die are mounted.
摘要翻译：公开了形成包括单面基板的半导体封装的方法。在本发明的第一实施例中，衬底可以包括位于衬底的顶表面上的导电层，即，与衬底安装在衬底的同一侧上的导电层。在本发明的第二实施例中，衬底可以包括位于衬底底部上的导电层，即，衬底与安装管芯的位置相反的一侧。

3. 发明申请

WO2008002836A3 STACKED, INTERCONNECTED SEMICONDUCTOR PACKAGES 审中-公开
标题翻译：堆叠式，互连式半导体封装
公开(公告)号：WO2008002836A3
公开(公告)日：2008-02-14
申请号：PCT/US2007071881
申请日：2007-06-22
申请人： SANDISK CORP , YU CHEEMAN , LIAO CHIH-CHIN , TAKIAR HEM
发明人： YU CHEEMAN , LIAO CHIH-CHIN , TAKIAR HEM
IPC分类号： H01L25/11
CPC分类号： H01L25/105 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2225/0651 , H01L2225/06562 , H01L2225/1023 , H01L2225/1058 , H01L2225/1064 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： An electronic component is disclosed including a plurality of stacked semiconductor packages. A first such embodiment includes an internal connector for electrically coupling the stacked semiconductor packages. A second such embodiment includes an external connector for electrically coupling the stacked semiconductor packages.
摘要翻译：公开了一种包括多个堆叠的半导体封装的电子部件。第一个这样的实施例包括用于电耦合堆叠的半导体封装的内部连接器。第二个这样的实施例包括用于电耦合堆叠的半导体封装的外部连接器。

4. 发明申请

WO2007136651A3 SEMICONDUCTOR DEVICE WITH A DISTRIBUTED PLATING PATTERN 审中-公开
标题翻译：具有分布式电镀图案的半导体器件
公开(公告)号：WO2007136651A3
公开(公告)日：2008-03-13
申请号：PCT/US2007011728
申请日：2007-05-16
申请人： SANDISK CORP , LIAO CHIH-CHIN , CHEN HAN-SHIAO , CHIU CHIN-TIEN , YU CHEEMEN , TAKIAR HEM
发明人： LIAO CHIH-CHIN , CHEN HAN-SHIAO , CHIU CHIN-TIEN , YU CHEEMEN , TAKIAR HEM
IPC分类号： H01L23/498
CPC分类号： H01L23/49838 , H01L23/3121 , H01L2924/0002 , H01L2924/1433 , H05K1/0271 , H05K3/108 , H05K3/28 , H05K2201/0373 , H05K2201/09736 , H01L2924/00
摘要： A substrate, and a semiconductor die package formed therefrom, are disclosed which include a distributed plating pattern for reducing mechanical stress on the semiconductor die. The substrate according to embodiments of the invention may include traces and contact pads plated in a double image plating process. Additionally, the substrate may include dummy plating areas including plating material. The plated vias and/or traces and the plating material within the dummy plating areas provide a plating pattern which is evenly distributed across the surface of the substrate. The even distribution of the plating pattern prevents peaks and valleys in the finished substrate.
摘要翻译：公开了一种基板和由其形成的半导体管芯封装，其包括用于减小半导体管芯上的机械应力的分布电镀图案。根据本发明的实施例的衬底可以包括以双映像电镀工艺电镀的迹线和接触焊盘。此外，基板可以包括包括电镀材料的虚拟电镀区域。电镀通孔和/或迹线以及虚拟电镀区域内的电镀材料提供均匀分布在基板表面上的电镀图案。电镀图案的均匀分布防止成品基板中的峰和谷。

5. 发明申请

WO2007070467A3 SUBSTRATE HAVING MINIMUM KERF WIDTH 审中-公开
标题翻译：具有最小KERF宽度的基板
公开(公告)号：WO2007070467A3
公开(公告)日：2007-12-21
申请号：PCT/US2006047206
申请日：2006-12-11
申请人： SANDISK CORP , TAKIAR HEM , WANG KEN JIAN MING , LIAO CHIH-CHIN , CHEN HAN-SHIAO
发明人： TAKIAR HEM , WANG KEN JIAN MING , LIAO CHIH-CHIN , CHEN HAN-SHIAO
IPC分类号： H01L21/48 , H01L23/498
CPC分类号： H05K3/242 , H01L21/4846 , H01L23/49838 , H01L24/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H05K3/0052 , H05K2201/09263 , H01L2924/00
摘要： A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages.
摘要翻译：公开了一种半导体裸片衬底面板，其包括在面板上邻接的半导体封装外形之间的最小切口宽度，同时确保电镀电端子的电隔离。通过减小相邻封装轮廓之间的边界的宽度，在用于半导体封装的衬底面板上获得额外的空间。

6. 发明申请

WO2007056013A3 HIGH DENSITY THREE DIMENSIONAL SEMICONDUCTOR DIE PACKAGE 审中-公开
标题翻译：高密度三维半导体封装
公开(公告)号：WO2007056013A3
公开(公告)日：2007-07-26
申请号：PCT/US2006042664
申请日：2006-11-01
申请人： SANDISK CORP , YU CHEEMEN , LIAO CHIH-CHIN , TAKIAR HEM
发明人： YU CHEEMEN , LIAO CHIH-CHIN , TAKIAR HEM
IPC分类号： H01L21/48 , H01L21/66 , H01L23/538 , H01L25/065 , H01L25/10
CPC分类号： H01L25/0657 , G11C5/02 , G11C5/04 , G11C5/143 , G11C8/12 , H01L21/485 , H01L23/5382 , H01L25/50 , H01L2225/06527 , H01L2225/06579 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor package is disclosed including a plurality semiconductor die mounted on stacked and bonded layers of substrate, for example polyimide tape used in tape automated bonding processes. The tape may have a plurality of repeating patterns of traces and contact pads formed thereon. The traces each include aligned interconnect pads on the respective top and bottom surfaces of the substrate for bonding the traces of one pattern to the traces of another pattern after the patterns have been singulated from the substrate, aligned and stacked. Semiconductor die such as flash memory and a controller die are mounted on the traces of the respective patterns on the substrate. In order for the controller die to uniquely address a specific flash memory die in the stack, a group of traces on each substrate supporting the memory die are used as address pins and punched in a unique layout relative to the layout of the traces other substrates. By providing each flash memory semiconductor die on a substrate with a unique layout of address traces, each memory die may be selectively addressed by the controller die.
摘要翻译：公开了一种半导体封装，其包括安装在基板的堆叠和接合层上的多个半导体管芯，例如在带自动焊接工艺中使用的聚酰亚胺带。带可以具有多个重复图案的迹线和形成在其上的接触垫。每个迹线包括在衬底的相应顶部和底部表面上的对准的互连焊盘，用于在将图案从基板切割成对准和堆叠之后将一个图案的迹线粘合到另一图案的迹线。诸如闪速存储器和控制器管芯的半导体管芯安装在衬底上各个图案的迹线上。为了使控制器裸片独特地寻址堆叠中的特定闪存芯片，支持存储芯片的每个衬底上的一组迹线被用作地址引脚，并相对于其它衬底的迹线的布局以独特的布局冲压。通过在基板上提供具有唯一的地址迹线布局的每个闪速存储器半导体管芯，每个存储管芯可以被控制器管芯选择性地寻址。

7. 发明申请

WO2007079122A3 STRIP FOR INTEGRATED CIRCUIT PACKAGES HAVING A MAXIMIZED USABLE AREA 审中-公开
标题翻译：具有最大可用面积的集成电路封装的条带
公开(公告)号：WO2007079122A3
公开(公告)日：2007-09-07
申请号：PCT/US2006049379
申请日：2006-12-27
申请人： SANDISK CORP , TAKIAR HEM , THAVARAJAH MANICKAM , WANG KEN JIAN MING , LIAO CHIH-CHIN , MCKENZIE ANDRE , BHAGATH SHRIKAR , CHEN HAN-SHIAO , CHIU CHIN-TIEN
发明人： TAKIAR HEM , THAVARAJAH MANICKAM , WANG KEN JIAN MING , LIAO CHIH-CHIN , MCKENZIE ANDRE , BHAGATH SHRIKAR , CHEN HAN-SHIAO , CHIU CHIN-TIEN
IPC分类号： H01L21/56 , H01L23/495 , H01L23/544
CPC分类号： H01L23/544 , H01L21/4857 , H01L21/50 , H01L21/561 , H01L23/49565 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/85 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2223/54486 , H01L2224/2929 , H01L2224/293 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/83801 , H01L2224/83851 , H01L2224/85 , H01L2224/97 , H01L2225/06568 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/0102 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/0781 , H01L2924/12041 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , Y10T29/49117 , H01L2924/00012 , H01L2924/3512 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A strip (40) on which a plurality of integrated circuit package outlines (42) may be fabricated 'within a plurality of process tools. The strip includes one or more fiducial, notches (44) and/or guide pin notches (46) formed in an outer edge of the strip. The one or more fiducial and/or guide pin notches allow a position of the strip to be identified within at least one process tool of the plurality of process tools. By forming the notches in the outer periphery of the strip, the usable area on the strip on which integrated circuit package outlines may be formed is increased. The strip may alternatively include conventional fiducial and/or guide pin holes (24, 26), with the molding compound applied at least partially around the holes on one or more sides of the strip. The strip may further alternatively include fiducial holes (92) filled with a translucent material that provides stability to the strip while allowing the strip to be used with an optical recognition sensor.
摘要翻译：在多个处理工具中可在其上制造多个集成电路封装轮廓（42）的条（40）。该条带包括形成在条的外边缘中的一个或多个基准，凹口（44）和/或引导销凹口（46）。一个或多个基准和/或引导销凹口允许在多个处理工具的至少一个处理工具内识别条带的位置。通过在带的外周形成切口，可以形成集成电路封装轮廓的带上的可用区域。替代地，带可以包括常规的基准和/或引导销孔（24,26），其中模制化合物至少部分地围绕带的一侧或多侧上的孔施加。带还可以包括填充有半透明材料的基准孔（92），其为条带提供稳定性，同时允许带与光学识别传感器一起使用。

8. 发明申请

WO2007011511A2 DIE PACKAGE WITH ASYMMETRIC LEADFRAME CONNECTION 审中-公开
标题翻译：具有不对称铅球连接的模具包装
公开(公告)号：WO2007011511A2
公开(公告)日：2007-01-25
申请号：PCT/US2006025302
申请日：2006-06-28
申请人： SANDISK CORP , LEE MING HSUN , LIAO CHIH-CHIN , YU CHEEMEN , TAKIAR HEM
发明人： LEE MING HSUN , LIAO CHIH-CHIN , YU CHEEMEN , TAKIAR HEM
IPC分类号： H01L23/495
CPC分类号： H01L23/4951 , H01L23/49551 , H01L23/49558 , H01L23/49575 , H01L24/48 , H01L24/73 , H01L2224/05553 , H01L2224/32145 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/49109 , H01L2224/73265 , H01L2225/06562 , H01L2924/00014 , H01L2924/01087 , H01L2924/10161 , H01L2924/14 , H01L2924/181 , H01L2924/18165 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A leadframe for a semiconductor package is disclosed including electrical leads which extend from one side of the leadframe to an opposite side of the leadframe, where electrical connection may be made with the semiconductor die at the second side of the leadframe. The semiconductor die may be supported on the leads extending across the leadframe. The package may further include a spacer layer affixed to the electrical leads to fortify the semiconductor package and to prevent exposure of the electrical leads during the molding of the package.
摘要翻译：公开了一种用于半导体封装的引线框架，其包括从引线框架的一侧延伸到引线框架的相反侧的电引线，其中可以在引线框架的第二侧与半导体管芯进行电连接。半导体管芯可以被支撑在延伸穿过引线框架的引线上。该封装可以进一步包括固定到电引线的间隔层，以加固半导体封装并防止在引线封装成型期间电引线的暴露。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式