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1. 发明申请

WO2012061167A1 ASYMMETRIC HETERO-STRUCTURE FET AND METHOD OF MANUFACTURE 审中-公开
标题翻译：不对称异质结构FET及其制造方法
公开(公告)号：WO2012061167A1
公开(公告)日：2012-05-10
申请号：PCT/US2011/057779
申请日：2011-10-26
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ANDERSON, Brent, A. , JOHNSON, Jeffrey, B. , NOWAK, Edward, J. , ROBINSON, Robert, R.
发明人： ANDERSON, Brent, A. , JOHNSON, Jeffrey, B. , NOWAK, Edward, J. , ROBINSON, Robert, R.
IPC分类号： H01L29/10 , H01L21/336 , H01L29/165 , H01L29/49 , H01L29/51
CPC分类号： H01L29/1054 , H01L29/165 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/66659
摘要： An asymmetric hetero-structure FET and method of manufacture is provided. The structure includes a semiconductor substrate (10) and an epitaxially grown semiconductor layer (15) on the semiconductor substrate (10). The epitaxially grown semiconductor layer (15) includes an alloy having a band structure and thickness that confines inversion carriers in a channel region, and a thicker portion extending deeper into the semiconductor structure at a doped edge to avoid confinement of the inversion carriers at the doped edge.
摘要翻译：提供了非对称异质结构FET及其制造方法。该结构包括在半导体衬底（10）上的半导体衬底（10）和外延生长的半导体层（15）。外延生长的半导体层（15）包括具有限制沟道区域中的反转载流子的带结构和厚度的合金，以及在掺杂边缘处更深地延伸到半导体结构中的较厚部分，以避免掺杂的反转载流子的约束边缘。

2. 发明申请

WO2009003012A1 JUNCTION FIELD EFFECT TRANSISTOR WITH A HYPERABRUPT JUNCTION 审中-公开
标题翻译：具有高压接点的结型场效应晶体管
公开(公告)号：WO2009003012A1
公开(公告)日：2008-12-31
申请号：PCT/US2008/068139
申请日：2008-06-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ESHUN, Ebenezer, E. , JOHNSON, Jeffrey, B. , PHELPS, Richard, A. , RASSEL, Robert, M. , ZIERAK, Michael, L.
发明人： ESHUN, Ebenezer, E. , JOHNSON, Jeffrey, B. , PHELPS, Richard, A. , RASSEL, Robert, M. , ZIERAK, Michael, L.
IPC分类号： H01L29/80 , H01L21/338 , H01L29/812
CPC分类号： H01L29/808 , H01L27/0617 , H01L27/098 , H01L29/36 , H01L29/66901
摘要： A junction field effect transistor (JFET) (Fig. 4) has a hyperabrupl junction laj cr (54) that functions as a channel of a JFFT. The hyperabrupt junction layer (54) is formed by two dopant profiles (50. 52) of opposite t}pes such that one dopant concentration profile has a peak concentration depth at a tail end of the other dopant profile. The voltage bias to the channel is provided by a body ( 16) that is doped with the same type of dopants as the gate. This is in contrast with conventional JI7KTs that have a body that is doped with the opposite conductivity type as the gate. The body ( 16) may be electrically decoupled from (Figure 4, 10 and 30) the substrate by another reverse bias junction formed either between the body and the substrate or between a buried conductor layer beneath the body and the substrate (Figure 8. 16 and 1 10). The capability to form a thin hyperabrupt junction layer (54) allows formation of a JFET in a semiconductor-on-insulator substrate (Figure 11. 210. 230).
摘要翻译：结型场效应晶体管（JFET）（图4）具有作为JFFT通道发挥功能的超级联结结点laj cr（54）。超破裂结层（54）由相对的t} pes的两个掺杂剂轮廓（50.52）形成，使得一个掺杂剂浓度分布在另一个掺杂剂分布的尾端处具有峰值浓度深度。通道的电压偏置由掺杂有与栅极相同类型的掺杂剂的体（16）提供。这与传统的JI7KT相反，传统的JI7KT具有以与栅极相反的导电类型掺杂的主体。主体（16）可以通过在主体和衬底之间形成的另一个反向偏置连接点或者在主体和衬底之间的掩埋导体层之间（图8,10和30）与衬底电气去耦合（图8,10和30）和110）。形成薄的超破坏结层（54）的能力允许在绝缘体上半导体衬底中形成JFET（图11,210,230）。

3. 发明申请

WO2007084879A3 LOW RESISTANCE AND INDUCTANCE BACKSIDE THROUGH VIAS AND METHODS OF FABRICATING SAME 审中-公开
标题翻译：通过VIAS的低电阻和电感及其制造方法
公开(公告)号：WO2007084879A3
公开(公告)日：2008-02-21
申请号：PCT/US2007060544
申请日：2007-01-15
申请人： IBM , ERTURK METE , GROVES ROBERT A , JOHNSON JEFFREY B , JOSEPH ALVIN J , LIU QIZHI , SPROGIS EDMUND J , STAMPER ANTHONY K
发明人： ERTURK METE , GROVES ROBERT A , JOHNSON JEFFREY B , JOSEPH ALVIN J , LIU QIZHI , SPROGIS EDMUND J , STAMPER ANTHONY K
IPC分类号： H01L21/00 , H01L21/302 , H01L21/306 , H01L21/44 , H01L21/77
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation (250) in a substrate (100), the substrate (100) having a frontside and an opposing backside; forming a first dielectric layer (105) on the frontside of the substrate (100); forming a trench (265C) in the first dielectric layer (105), the trench (265C) aligned over and within a perimeter of the dielectric isolation (250) and extending to the dielectric isolation (250); extending the trench (265C) formed in the first dielectric layer (1 05) through the dielectric isolation (250) and into the substrate (1 00)to a depth (Dl ) less than a thickness of the substrate (1 00); filling the trench (265C) and co-planarizing a top surface of the trench (265C) with a top surface of the first dielectric layer (1 05) to form an electrically conductive through via (270C); and thinning the substrate (100) from a backside of the substrate (100) to expose the through via (270C).
摘要翻译：背面接触结构及其制造方法。该方法包括：在衬底（100）中形成绝缘隔离（250），所述衬底（100）具有前侧和相对的背面; 在所述基板（100）的前侧形成第一介电层（105）; 在所述第一电介质层（105）中形成沟槽（265C），所述沟槽（265C）在所述电介质隔离（250）的周边内并且在所述绝缘隔离（250）的周边内并且延伸到所述电介质隔离（250）; 将形成在第一电介质层（105）中的沟槽（265C）延伸通过电介质隔离（250）并延伸到衬底（100）中至小于衬底厚度（001）的深度（D1）。填充沟槽（265C）并且将沟槽（265C）的顶表面与第一介电层（105）的顶表面共平面化以形成导电通孔（270C）; 以及从所述衬底（100）的背面使所述衬底（100）变薄以暴露所述通孔（270C）。

4. 发明申请

WO2006073943A2 METHOD FOR FORMING A ONE MASK HYPERABRUPT JUNCTION VARACTOR USING A COMPENSATED CATHODE CONTACT 审中-公开
标题翻译：使用补偿阴极接触形成一个掩模超高压连接器的方法
公开(公告)号：WO2006073943A2
公开(公告)日：2006-07-13
申请号：PCT/US2005047085
申请日：2005-12-22
申请人： IBM , COOLBAUGH DOUGLAS D , FURKAY STEPHEN S , JOHNSON JEFFREY B , RASSEL ROBERT M
发明人： COOLBAUGH DOUGLAS D , FURKAY STEPHEN S , JOHNSON JEFFREY B , RASSEL ROBERT M
IPC分类号： H01L29/93 , H01L21/20
CPC分类号： H01L29/93
摘要： A semiconductor structure comprising a hyperabrupt junction varactor with a compensated cathode contact as well as a method of fabricating the same are disclosed. The method includes a single implant mask which is used in forming the subcollector/cathode, collector/well and hyperabrupt junction.
摘要翻译：公开了一种半导体结构，其包括具有补偿的阴极接触的超级连接变容二极管及其制造方法。该方法包括用于形成子集电极/阴极，集电极/阱和超破裂结的单个注入掩模。

5. 发明申请

WO2012064912A3 BUTTED SOI JUNCTION ISOLATION STRUCTURES AND DEVICES AND METHOD OF FABRICATION 审中-公开
公开(公告)号：WO2012064912A3
公开(公告)日：2012-05-18
申请号：PCT/US2011/060084
申请日：2011-11-10
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , JOHNSON, Jeffrey, B. , NARASIMHA, Shreesh , NAYFEH, Hasan, M. , ONTALUS, Viorel, C. , ROBINSON, Robert, R.
发明人： JOHNSON, Jeffrey, B. , NARASIMHA, Shreesh , NAYFEH, Hasan, M. , ONTALUS, Viorel, C. , ROBINSON, Robert, R.
IPC分类号： H01L29/78 , H01L21/336
摘要： A structure, a FET, a method of making the structure and of making the FET. The structure including: a silicon layer (105; Fig. 5) on a buried oxide (BOX) layer (115) of a silicon-on-insulator substrate (100); a trench in the silicon layer extending from a top surface of the silicon layer into the silicon layer, the trench not extending to the BOX layer (160, 165, and 170), a doped region (155) in the silicon layer between and abutting the BOX layer and a bottom of the trench, the first doped region doped to a first dopant concentration; a first epitaxial layer (160), doped to a second dopant concentration, in a bottom of the trench; a second epitaxial layer (165), doped to a third dopant concentration, on the first epitaxial layer in the trench; and wherein the third dopant concentration is greater than the first and second dopant concentrations and the first dopant concentration is greater than the second dopant concentration.

6. 发明申请

WO2012064912A2 BUTTED SOI JUNCTION ISOLATION STRUCTURES AND DEVICES AND METHOD OF FABRICATION 审中-公开
标题翻译：所谓的SOI结隔离结构和装置以及制造方法
公开(公告)号：WO2012064912A2
公开(公告)日：2012-05-18
申请号：PCT/US2011060084
申请日：2011-11-10
申请人： IBM , JOHNSON JEFFREY B , NARASIMHA SHREESH , NAYFEH HASAN M , ONTALUS VIOREL C , ROBINSON ROBERT R
发明人： JOHNSON JEFFREY B , NARASIMHA SHREESH , NAYFEH HASAN M , ONTALUS VIOREL C , ROBINSON ROBERT R
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7824 , H01L21/76237 , H01L21/84 , H01L27/1203
摘要： A structure, a FET, a method of making the structure and of making the FET. The structure including: a silicon layer (105; Fig. 5) on a buried oxide (BOX) layer (115) of a silicon-on-insulator substrate (100); a trench in the silicon layer extending from a top surface of the silicon layer into the silicon layer, the trench not extending to the BOX layer (160, 165, and 170), a doped region (155) in the silicon layer between and abutting the BOX layer and a bottom of the trench, the first doped region doped to a first dopant concentration; a first epitaxial layer (160), doped to a second dopant concentration, in a bottom of the trench; a second epitaxial layer (165), doped to a third dopant concentration, on the first epitaxial layer in the trench; and wherein the third dopant concentration is greater than the first and second dopant concentrations and the first dopant concentration is greater than the second dopant concentration.
摘要翻译：一种结构，一种FET，一种制造该结构和制造该FET的方法。所述结构包括：在绝缘体上硅衬底（100）上的掩埋氧化物（BOX）层（115）上的硅层（105;图5）; 所述硅层中的沟槽从所述硅层的顶表面延伸到所述硅层中，所述沟槽不延伸到所述BOX层（160,165和170），所述硅层中的掺杂区域（155）和邻接 BOX层和沟槽的底部，掺杂到第一掺杂剂浓度的第一掺杂区; 在沟槽的底部掺杂到第二掺杂剂浓度的第一外延层（160）; 在沟槽中的第一外延层上掺杂到第三掺杂剂浓度的第二外延层（165）; 并且其中所述第三掺杂剂浓度大于所述第一和第二掺杂剂浓度，并且所述第一掺杂剂浓度大于所述第二掺杂剂浓度。

7. 发明申请

WO2011162977A3 DELTA MONOLAYER DOPANTS EPITAXY FOR EMBEDDED SOURCE/DRAIN SILICIDE 审中-公开
标题翻译： DELTA MONOLAYER DOPANTS嵌入式源/漏极硅胶外观
公开(公告)号：WO2011162977A3
公开(公告)日：2012-03-15
申请号：PCT/US2011039892
申请日：2011-06-10
申请人： IBM , CHAN KEVIN K , DUBE ABHISHEK , HOLT JUDSON R , JOHNSON JEFFREY B , LI JINGHONG , PARK DAE-GYU , ZHU ZHENGMAO
发明人： CHAN KEVIN K , DUBE ABHISHEK , HOLT JUDSON R , JOHNSON JEFFREY B , LI JINGHONG , PARK DAE-GYU , ZHU ZHENGMAO
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66636 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7834 , H01L29/7848
摘要： Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack (18) located on an upper surface of a semiconductor substrate (12). The at least one FET gate stack includes source and drain extension regions (28) located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel (40) is also present between the source and drain extension regions (28) and beneath the at least one gate stack (18). The structure further includes embedded stressor elements (33) located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes, from bottom to top, a first layer of a first epitaxy doped semiconductor material (35) having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, a second layer of a second epitaxy doped semiconductor material (36) located atop the first layer, and a delta monolayer of dopant located on an upper surface of the second layer. The structure further includes a metal semiconductor alloy contact (45) located directly on an upper surface of the delta monolayer (37).
摘要翻译：公开了在其中具有嵌入的应力元件的半导体结构。所公开的结构包括位于半导体衬底（12）的上表面上的至少一个FET栅叠层（18）。所述至少一个FET栅极堆叠包括位于所述至少一个FET栅极堆叠中的覆盖区内的所述半导体衬底内的源极和漏极延伸区域（28）。器件通道（40）也存在于源极和漏极延伸区域（28）之间并且在至少一个栅极堆叠（18）下方。该结构还包括位于至少一个FET栅极堆叠的相对侧上并且在半导体衬底内的嵌入式应力元件（33）。每个嵌入式应力元件包括从底部到顶部具有不同于半导体衬底的晶格常数的晶格常数的第一外延掺杂半导体材料（35）的第一层，并且在器件沟道中施加应变，位于第一层顶部的第二外延掺杂半导体材料（36）的第二层和位于第二层的上表面上的掺杂剂的Δ单层。该结构还包括直接位于三角单层（37）的上表面上的金属半导体合金接触（45）。

8. 发明申请

WO2011162977A2 DELTA MONOLAYER DOPANTS EPITAXY FOR EMBEDDED SOURCE/DRAIN SILICIDE 审中-公开
标题翻译： DELTA MONOLAYER DOPANTS嵌入式源/漏极硅胶外观
公开(公告)号：WO2011162977A2
公开(公告)日：2011-12-29
申请号：PCT/US2011/039892
申请日：2011-06-10
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CHAN, Kevin, K. , DUBE, Abhishek , HOLT, Judson, R. , JOHNSON, Jeffrey, B. , LI, Jinghong , PARK, Dae-Gyu , ZHU, Zhengmao
发明人： CHAN, Kevin, K. , DUBE, Abhishek , HOLT, Judson, R. , JOHNSON, Jeffrey, B. , LI, Jinghong , PARK, Dae-Gyu , ZHU, Zhengmao
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66636 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7834 , H01L29/7848
摘要： Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack (18) located on an upper surface of a semiconductor substrate (12). The at least one FET gate stack includes source and drain extension regions (28) located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel (40) is also present between the source and drain extension regions (28) and beneath the at least one gate stack (18). The structure further includes embedded stressor elements (33) located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes, from bottom to top, a first layer of a first epitaxy doped semiconductor material (35) having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, a second layer of a second epitaxy doped semiconductor material (36) located atop the first layer, and a delta monolayer of dopant located on an upper surface of the second layer. The structure further includes a metal semiconductor alloy contact (45) located directly on an upper surface of the delta monolayer (37).
摘要翻译：公开了在其中具有嵌入的应力元件的半导体结构。所公开的结构包括位于半导体衬底（12）的上表面上的至少一个FET栅叠层（18）。所述至少一个FET栅极堆叠包括位于所述至少一个FET栅极堆叠中的覆盖区内的所述半导体衬底内的源极和漏极延伸区域（28）。器件通道（40）也存在于源极和漏极延伸区域（28）之间并且在至少一个栅极堆叠（18）下方。该结构还包括位于至少一个FET栅极堆叠的相对侧上并且在半导体衬底内的嵌入式应力元件（33）。每个嵌入式应力元件包括从底部到顶部具有不同于半导体衬底的晶格常数的晶格常数的第一外延掺杂半导体材料（35）的第一层，并且在器件沟道中施加应变，位于第一层顶部的第二外延掺杂半导体材料（36）的第二层和位于第二层的上表面上的掺杂剂的Δ单层。该结构还包括直接位于三角单层（37）的上表面上的金属半导体合金接触（45）。

9. 发明申请

WO2007084879A2 LOW RESISTANCE AND INDUCTANCE BACKSIDE THROUGH VIAS AND METHODS OF FABRICATING SAME 审中-公开
标题翻译：通过VIAS的低电阻和电感及其制造方法
公开(公告)号：WO2007084879A2
公开(公告)日：2007-07-26
申请号：PCT/US2007/060544
申请日：2007-01-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ERTURK, Mete , GROVES, Robert, A. , JOHNSON, Jeffrey, B. , JOSEPH, Alvin, J. , LIU, Qizhi , SPROGIS, Edmund, J. , STAMPER, Anthony, K.
发明人： ERTURK, Mete , GROVES, Robert, A. , JOHNSON, Jeffrey, B. , JOSEPH, Alvin, J. , LIU, Qizhi , SPROGIS, Edmund, J. , STAMPER, Anthony, K.
IPC分类号： H01L21/50
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation (250) in a substrate (100), the substrate (100) having a frontside and an opposing backside; forming a first dielectric layer (105) on the frontside of the substrate (100); forming a trench (265C) in the first dielectric layer (105), the trench (265C) aligned over and within a perimeter of the dielectric isolation (250) and extending to the dielectric isolation (250); extending the trench (265C) formed in the first dielectric layer (1 05) through the dielectric isolation (250) and into the substrate (1 00)to a depth (Dl ) less than a thickness of the substrate (1 00); filling the trench (265C) and co-planarizing a top surface of the trench (265C) with a top surface of the first dielectric layer (1 05) to form an electrically conductive through via (270C); and thinning the substrate (100) from a backside of the substrate (100) to expose the through via (270C).
摘要翻译：背面接触结构及其制造方法。该方法包括：在衬底（100）中形成绝缘隔离（250），所述衬底（100）具有前侧和相对的背面; 在所述基板（100）的前侧形成第一电介质层（105）; 在所述第一电介质层（105）中形成沟槽（265C），所述沟槽（265C）在所述介电隔离（250）的周边内并且在所述介质隔离（250）的周边内对准并且延伸到所述电介质隔离（250）; 将形成在第一电介质层（105）中的沟槽（265C）延伸通过电介质隔离（250）并延伸到衬底（100）中至达到小于衬底厚度（001）的深度（D1）。填充沟槽（265C）并且将沟槽（265C）的顶表面与第一介电层（105）的顶表面共平化以形成导电通孔（270C）; 以及从所述衬底（100）的背面使所述衬底（100）变薄以暴露所述通孔（270C）。

10. 发明申请

WO2006073943A3 METHOD FOR FORMING A ONE MASK HYPERABRUPT JUNCTION VARACTOR USING A COMPENSATED CATHODE CONTACT 审中-公开
公开(公告)号：WO2006073943A3
公开(公告)日：2006-07-13
申请号：PCT/US2005/047085
申请日：2005-12-22
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , COOLBAUGH, Douglas, D. , FURKAY, Stephen, S. , JOHNSON, Jeffrey, B. , RASSEL, Robert, M.
发明人： COOLBAUGH, Douglas, D. , FURKAY, Stephen, S. , JOHNSON, Jeffrey, B. , RASSEL, Robert, M.
IPC分类号： H01L21/20 , H01L29/93
摘要： A semiconductor structure comprising a hyperabrupt junction varactor with a compensated cathode contact as well as a method of fabricating the same are disclosed. The method includes a single implant mask which is used in forming the subcollector/cathode, collector/well and hyperabrupt junction.

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