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1. 发明申请

WO2011162977A2 DELTA MONOLAYER DOPANTS EPITAXY FOR EMBEDDED SOURCE/DRAIN SILICIDE 审中-公开
标题翻译： DELTA MONOLAYER DOPANTS嵌入式源/漏极硅胶外观
公开(公告)号：WO2011162977A2
公开(公告)日：2011-12-29
申请号：PCT/US2011/039892
申请日：2011-06-10
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CHAN, Kevin, K. , DUBE, Abhishek , HOLT, Judson, R. , JOHNSON, Jeffrey, B. , LI, Jinghong , PARK, Dae-Gyu , ZHU, Zhengmao
发明人： CHAN, Kevin, K. , DUBE, Abhishek , HOLT, Judson, R. , JOHNSON, Jeffrey, B. , LI, Jinghong , PARK, Dae-Gyu , ZHU, Zhengmao
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66636 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7834 , H01L29/7848
摘要： Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack (18) located on an upper surface of a semiconductor substrate (12). The at least one FET gate stack includes source and drain extension regions (28) located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel (40) is also present between the source and drain extension regions (28) and beneath the at least one gate stack (18). The structure further includes embedded stressor elements (33) located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes, from bottom to top, a first layer of a first epitaxy doped semiconductor material (35) having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, a second layer of a second epitaxy doped semiconductor material (36) located atop the first layer, and a delta monolayer of dopant located on an upper surface of the second layer. The structure further includes a metal semiconductor alloy contact (45) located directly on an upper surface of the delta monolayer (37).
摘要翻译：公开了在其中具有嵌入的应力元件的半导体结构。所公开的结构包括位于半导体衬底（12）的上表面上的至少一个FET栅叠层（18）。所述至少一个FET栅极堆叠包括位于所述至少一个FET栅极堆叠中的覆盖区内的所述半导体衬底内的源极和漏极延伸区域（28）。器件通道（40）也存在于源极和漏极延伸区域（28）之间并且在至少一个栅极堆叠（18）下方。该结构还包括位于至少一个FET栅极堆叠的相对侧上并且在半导体衬底内的嵌入式应力元件（33）。每个嵌入式应力元件包括从底部到顶部具有不同于半导体衬底的晶格常数的晶格常数的第一外延掺杂半导体材料（35）的第一层，并且在器件沟道中施加应变，位于第一层顶部的第二外延掺杂半导体材料（36）的第二层和位于第二层的上表面上的掺杂剂的Δ单层。该结构还包括直接位于三角单层（37）的上表面上的金属半导体合金接触（45）。

2. 发明申请

WO2011133339A2 MONOLAYER DOPANT EMBEDDED STRESSOR FOR ADVANCED CMOS 审中-公开
标题翻译：用于高级CMOS的单层掺杂嵌入式压电器
公开(公告)号：WO2011133339A2
公开(公告)日：2011-10-27
申请号：PCT/US2011/031693
申请日：2011-04-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CHAN, Kevin, K. , DUBE, Abhishek , HOLT, Judson, R. , LI, Jinghong , NEWBURY, Joseph, S. , ONTALUS, Viorel , PARK, Dae-Gyu , ZHU, Zhengmao
发明人： CHAN, Kevin, K. , DUBE, Abhishek , HOLT, Judson, R. , LI, Jinghong , NEWBURY, Joseph, S. , ONTALUS, Viorel , PARK, Dae-Gyu , ZHU, Zhengmao
IPC分类号： H01L29/78 , H01L21/336 , H01L27/092 , H01L21/8228
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/6656 , H01L29/66636 , H01L29/7834
摘要： Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include an FET gate stack 18 located on an upper surface of a semiconductor substrate 12. The FET gate stack includes source and drain extension regions 28 located within the semiconductor substrate at a footprint of the FET gate stack. A device channel 40 is also present between the source and drain extension regions and beneath the gate stack. The structure further includes embedded stressor elements 34 located on opposite sides of the FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes a lower layer of a first epitaxy 36 doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy 38 doped semiconductor material located atop the lower layer. The lower layer of the first epitaxy doped semiconductor material has a lower content of dopant as compared to the upper layer of the second epitaxy doped semiconductor material. The structure further includes a monolayer of dopant located within the upper layer of each of the embedded stressor elements. The monolayer of dopant is in direct contact with an edge of either the source extension region or the drain extension region.
摘要翻译：公开了在其中具有嵌入的应力元件的半导体结构。所公开的结构包括位于半导体衬底12的上表面上的FET栅极堆叠18. FET栅极堆叠包括在FET栅极堆叠的覆盖区处位于半导体衬底内的源极和漏极延伸区域28。器件沟道40也存在于源极延伸区域和漏极延伸区域之间以及栅极堆叠层下方。该结构还包括位于FET栅极堆叠的相对侧并且位于半导体衬底内的嵌入式应力元件34。每个嵌入的应力元件包括第一外延36掺杂半导体材料的下层，其具有不同于半导体衬底的晶格常数的晶格常数并且在器件沟道中施加应变，并且第二外延的上层 38掺杂的半导体材料位于下层的顶部。与第二外延掺杂半导体材料的上层相比，第一外延掺杂半导体材料的下层具有较低的掺杂剂含量。该结构还包括位于每个嵌入的应力元件的上层内的掺杂剂单层。掺杂剂的单层与源极延伸区域或漏极延伸区域的边缘直接接触。

3. 发明申请

WO2011162977A3 DELTA MONOLAYER DOPANTS EPITAXY FOR EMBEDDED SOURCE/DRAIN SILICIDE 审中-公开
标题翻译： DELTA MONOLAYER DOPANTS嵌入式源/漏极硅胶外观
公开(公告)号：WO2011162977A3
公开(公告)日：2012-03-15
申请号：PCT/US2011039892
申请日：2011-06-10
申请人： IBM , CHAN KEVIN K , DUBE ABHISHEK , HOLT JUDSON R , JOHNSON JEFFREY B , LI JINGHONG , PARK DAE-GYU , ZHU ZHENGMAO
发明人： CHAN KEVIN K , DUBE ABHISHEK , HOLT JUDSON R , JOHNSON JEFFREY B , LI JINGHONG , PARK DAE-GYU , ZHU ZHENGMAO
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66636 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7834 , H01L29/7848
摘要： Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack (18) located on an upper surface of a semiconductor substrate (12). The at least one FET gate stack includes source and drain extension regions (28) located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel (40) is also present between the source and drain extension regions (28) and beneath the at least one gate stack (18). The structure further includes embedded stressor elements (33) located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes, from bottom to top, a first layer of a first epitaxy doped semiconductor material (35) having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, a second layer of a second epitaxy doped semiconductor material (36) located atop the first layer, and a delta monolayer of dopant located on an upper surface of the second layer. The structure further includes a metal semiconductor alloy contact (45) located directly on an upper surface of the delta monolayer (37).
摘要翻译：公开了在其中具有嵌入的应力元件的半导体结构。所公开的结构包括位于半导体衬底（12）的上表面上的至少一个FET栅叠层（18）。所述至少一个FET栅极堆叠包括位于所述至少一个FET栅极堆叠中的覆盖区内的所述半导体衬底内的源极和漏极延伸区域（28）。器件通道（40）也存在于源极和漏极延伸区域（28）之间并且在至少一个栅极堆叠（18）下方。该结构还包括位于至少一个FET栅极堆叠的相对侧上并且在半导体衬底内的嵌入式应力元件（33）。每个嵌入式应力元件包括从底部到顶部具有不同于半导体衬底的晶格常数的晶格常数的第一外延掺杂半导体材料（35）的第一层，并且在器件沟道中施加应变，位于第一层顶部的第二外延掺杂半导体材料（36）的第二层和位于第二层的上表面上的掺杂剂的Δ单层。该结构还包括直接位于三角单层（37）的上表面上的金属半导体合金接触（45）。

4. 发明申请

WO2011051109A1 BI-LAYER nFET EMBEDDED STRESSOR ELEMENT AND INTEGRATION TO ENHANCE DRIVE CURRENT 审中-公开
标题翻译：双层NFET嵌入式应力元件和集成以增强驱动电流
公开(公告)号：WO2011051109A1
公开(公告)日：2011-05-05
申请号：PCT/EP2010/065495
申请日：2010-10-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , ONTALUS, Viorel , CHAN, Kevin , DUBE, Abhishek , LI, Jinghong , ZHU, Zhengmao
发明人： ONTALUS, Viorel , CHAN, Kevin , DUBE, Abhishek , LI, Jinghong , ZHU, Zhengmao
IPC分类号： H01L21/336 , H01L29/165 , H01L29/78
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/66636 , H01L29/7834 , Y10S257/90 , Y10S257/902 , Y10S257/903
摘要： A semiconductor structure including a bi-layer nFET embedded stressor element is disclosed. The bi-layer nFET embedded stressor element can be integrated into any CMOS process flow. The bi-layer nFET embedded stressor element includes an implant damaged free first layer of a first epitaxy semiconductor material having a lattice constant that is different from a lattice constant of a semiconductor substrate and imparts a tensile strain in a device channel of an nFET gate stack. Typically, and when the semiconductor is composed of silicon, the first layer of the bi-layer nFET embedded stressor element is composed of Si:C. The bi-layer nFET embedded stressor element further includes a second layer of a second epitaxy semiconductor material that has a lower resistance to dopant diffusion than the first epitaxy semiconductor material. Typically, and when the semiconductor is composed of silicon, the second layer of the bi-layer nFET embedded stressor element is composed of silicon. Only the second layer of the bi-layer nFET embedded stressor element includes the implanted source/drain regions.
摘要翻译：公开了一种包括双层nFET嵌入式应力元件的半导体结构。双层nFET嵌入式应力元件可以集成到任何CMOS工艺流程中。双层nFET嵌入式应力元件包括具有不同于半导体衬底的晶格常数的晶格常数的第一外延半导体材料的自由第一层的植入物，并且在nFET栅极堆叠的器件沟道中施加拉伸应变。通常，当半导体由硅组成时，双层nFET嵌入的应力元件的第一层由Si：C组成。双层nFET嵌入式应力元件还包括具有比第一外延半导体材料更低的掺杂剂扩散阻力的第二外延半导体材料层。通常，当半导体由硅组成时，双层nFET嵌入的应力元件的第二层由硅组成。双层nFET嵌入式应力元件的第二层仅包括注入的源极/漏极区域。

5. 发明申请

WO2011133339A3 MONOLAYER DOPANT EMBEDDED STRESSOR FOR ADVANCED CMOS 审中-公开
标题翻译：用于高级CMOS的单层掺杂嵌入式压电器
公开(公告)号：WO2011133339A3
公开(公告)日：2012-03-08
申请号：PCT/US2011031693
申请日：2011-04-08
申请人： IBM , CHAN KEVIN K , DUBE ABHISHEK , HOLT JUDSON R , LI JINGHONG , NEWBURY JOSEPH S , ONTALUS VIOREL , PARK DAE-GYU , ZHU ZHENGMAO
发明人： CHAN KEVIN K , DUBE ABHISHEK , HOLT JUDSON R , LI JINGHONG , NEWBURY JOSEPH S , ONTALUS VIOREL , PARK DAE-GYU , ZHU ZHENGMAO
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8228 , H01L27/092
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/6656 , H01L29/66636 , H01L29/7834
摘要： Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include an FET gate stack 18 located on an upper surface of a semiconductor substrate 12. The FET gate stack includes source and drain extension regions 28 located within the semiconductor substrate at a footprint of the FET gate stack. A device channel 40 is also present between the source and drain extension regions and beneath the gate stack. The structure further includes embedded stressor elements 34 located on opposite sides of the FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes a lower layer of a first epitaxy 36 doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy 38 doped semiconductor material located atop the lower layer. The lower layer of the first epitaxy doped semiconductor material has a lower content of dopant as compared to the upper layer of the second epitaxy doped semiconductor material. The structure further includes a monolayer of dopant located within the upper layer of each of the embedded stressor elements. The monolayer of dopant is in direct contact with an edge of either the source extension region or the drain extension region.
摘要翻译：公开了在其中具有嵌入的应力元件的半导体结构。所公开的结构包括位于半导体衬底12的上表面上的FET栅极堆叠18. FET栅极堆叠包括在FET栅极堆叠的覆盖区处位于半导体衬底内的源极和漏极延伸区域28。器件沟道40也存在于源极延伸区域和漏极延伸区域之间以及栅极堆叠层下方。该结构还包括位于FET栅极堆叠的相对侧并且位于半导体衬底内的嵌入式应力元件34。每个嵌入的应力元件包括第一外延36掺杂半导体材料的下层，其具有不同于半导体衬底的晶格常数的晶格常数并且在器件沟道中施加应变，并且第二外延的上层 38掺杂的半导体材料位于下层的顶部。与第二外延掺杂半导体材料的上层相比，第一外延掺杂半导体材料的下层具有较低的掺杂剂含量。该结构还包括位于每个嵌入的应力元件的上层内的掺杂剂单层。掺杂剂的单层与源极延伸区域或漏极延伸区域的边缘直接接触。

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