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1. 发明申请

WO2006073943A2 METHOD FOR FORMING A ONE MASK HYPERABRUPT JUNCTION VARACTOR USING A COMPENSATED CATHODE CONTACT 审中-公开
标题翻译：使用补偿阴极接触形成一个掩模超高压连接器的方法
公开(公告)号：WO2006073943A2
公开(公告)日：2006-07-13
申请号：PCT/US2005047085
申请日：2005-12-22
申请人： IBM , COOLBAUGH DOUGLAS D , FURKAY STEPHEN S , JOHNSON JEFFREY B , RASSEL ROBERT M
发明人： COOLBAUGH DOUGLAS D , FURKAY STEPHEN S , JOHNSON JEFFREY B , RASSEL ROBERT M
IPC分类号： H01L29/93 , H01L21/20
CPC分类号： H01L29/93
摘要： A semiconductor structure comprising a hyperabrupt junction varactor with a compensated cathode contact as well as a method of fabricating the same are disclosed. The method includes a single implant mask which is used in forming the subcollector/cathode, collector/well and hyperabrupt junction.
摘要翻译：公开了一种半导体结构，其包括具有补偿的阴极接触的超级连接变容二极管及其制造方法。该方法包括用于形成子集电极/阴极，集电极/阱和超破裂结的单个注入掩模。

2. 发明申请

WO2006017600A3 FEOL/MEOL METAL RESISTOR FOR HIGH END CMOS 审中-公开
标题翻译：用于高端CMOS的FEOL / MEOL金属电阻器
公开(公告)号：WO2006017600A3
公开(公告)日：2006-06-22
申请号：PCT/US2005027618
申请日：2005-08-04
申请人： IBM , CHINTHAKINDI ANIL K , COOLBAUGH DOUGLAS D , RAMACHANDRAN VIDHYA , RASSEL ROBERT M
发明人： CHINTHAKINDI ANIL K , COOLBAUGH DOUGLAS D , RAMACHANDRAN VIDHYA , RASSEL ROBERT M
IPC分类号： H01L21/20
CPC分类号： H01L28/24 , H01L27/0629 , H01L29/7833
摘要： A FEOL/MEOL metal resistor (32) that has tight sheet resistance tolerance (on the order of about 5% or less), high current density (on the order of about 0.5 mA/micron or greater), lower parasitics than diffused resistors and lower TCR than standard BEOL metal resistors as well as various methods of integrating such a metal resistor structure (32) into a CMOS technology are provided.
摘要翻译： FEOL / MEOL金属电阻（32）具有紧密的薄层电阻公差（约5％或更小），高电流密度（约0.5mA /微米或更大），比扩散电阻器更低的寄生效应，提供比标准BEOL金属电阻器更低的TCR以及将这种金属电阻器结构（32）集成到CMOS技术中的各种方法。

3. 发明申请

WO2006026055A2 MOS VARACTOR USING ISOLATION WELL 审中-公开
标题翻译： MOS变压器采用隔离井
公开(公告)号：WO2006026055A2
公开(公告)日：2006-03-09
申请号：PCT/US2005027738
申请日：2005-08-05
申请人： IBM , COOLBAUGH DOUGLAS D , HERSHBERGER DOUGLAS B , RASSEL ROBERT M
发明人： COOLBAUGH DOUGLAS D , HERSHBERGER DOUGLAS B , RASSEL ROBERT M
IPC分类号： H01L29/94 , H01L21/20
CPC分类号： H01L29/93 , H01L29/94
摘要： The present invention provides a varactor (22) that has increased tunability and a high quality factor Q as well as a method of fabricating the varactor (22). The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes providing a structure that includes a semiconductor substrate (12) of a first conductivity type and optionally a subcollector (14) or isolation well (i.e., doped region) of a second conductivity type located below an upper region (11) of the substrate (12), the first conductivity type is different from said second conductivity type. Next, a plurality of isolation regions (16) are formed in the upper region (11) of the substrate (12) and then a well region is formed in the upper region (11) of the substrate (12). In some cases, the doped region (14) is formed at this point of the inventive process. The well region includes outer well regions (20A and 20C) of the second conductivity type and an inner well region (20B) of the first conductivity type. Each well of said well region is separated at an upper surface by an isolation region (16). A field effect transistor having at least a gate conductor (26) of the first conductivity type is then formed above the inner well region (20B).
摘要翻译：本发明提供了具有增加的可调谐性和高品质因数Q的变容二极管（22）以及制造变容二极管（22）的方法。本发明的方法可以集成到常规的CMOS处理方案中或者集成到传统的BiCMOS处理方案中。该方法包括提供包括第一导电类型的半导体衬底（12）和可选地位于第二导电类型的上部区域（11）下方的第二导电类型的子集电极（14）或隔离阱（即，掺杂区域）衬底（12），第一导电类型不同于所述第二导电类型。接下来，在衬底（12）的上部区域（11）中形成多个隔离区域（16），然后在衬底（12）的上部区域（11）中形成阱区域。在某些情况下，掺杂区（14）在本发明方法的这一点形成。阱区包括第二导电类型的外阱区（20A和20C）和第一导电类型的内阱区（20B）。所述阱区的每个阱在上表面处被隔离区（16）分隔开。然后在内阱区（20B）上方形成至少具有第一导电类型的栅极导体（26）的场效应晶体管。

4. 发明申请

WO2005034202A3 PRECISION POLYSILICON RESISTOR PROCESS 审中-公开
标题翻译：精密多晶硅电阻工艺
公开(公告)号：WO2005034202A3
公开(公告)日：2005-11-10
申请号：PCT/US2004032406
申请日：2004-09-30
申请人： IBM , COOLBAUGH DOUGLAS D , GREER HEIDI L , RASSEL ROBERT M
发明人： COOLBAUGH DOUGLAS D , GREER HEIDI L , RASSEL ROBERT M
IPC分类号： H01L20060101 , H01L21/02 , H01L21/302 , H01L21/461 , H01L27/08
CPC分类号： H01L27/0738 , H01L27/0802 , H01L28/20
摘要： A process is disclosed for fabricating precision polysilicon resistors which more precisely control the tolerance of the sheet resistivity of the produced polysilicon resistors. The process generally includes performing an emitter / FET activation rapid thermal anneal (RTA) on a wafer having partially formed polysilicon resistors, followed by steps of depositing a protective dielectric layer (62) on the polysilicon, (56) implanting a dopant (64) through the protective dielectric layer into the polysilicon (56) to define the resistance of the polysilicon resistors, and forming a silicide (66).
摘要翻译：公开了一种制造精密多晶硅电阻器的方法，其更精确地控制所产生的多晶硅电阻器的薄层电阻率的公差。该方法通常包括在具有部分形成的多晶硅电阻器的晶片上执行发射极/ FET激活快速热退火（RTA），随后在多晶硅上沉积保护性介电层（62）的步骤，（56）注入掺杂剂（64）通过保护介电层进入多晶硅（56）以限定多晶硅电阻器的电阻，并形成硅化物（66）。

5. 发明申请

WO2009140052A3 METAL GATE INTEGRATION STRUCTURE AND METHOD INCLUDING METAL FUSE, ANTI-FUSE AND/OR RESISTOR 审中-公开
标题翻译：金属栅组合结构和方法，包括金属保险丝，抗保险丝和/或电阻
公开(公告)号：WO2009140052A3
公开(公告)日：2010-01-21
申请号：PCT/US2009041861
申请日：2009-04-28
申请人： IBM , ESHUN EBENEZER E , HE ZHONG-XIANG , RASSEL ROBERT M , COOLBAUGH DOUGLAS , GEBRESELASIE EPHREM G , WANG PING-CHUAN , KIM DEOK-KEE , KOTHANDARAMAN CHANDRASEKHARAN , ROBSON NORMAN W , MOY DAN , SAFRAN JOHN M , STEIN KENNETH J , HO HERBERT L , YAN HONGWEN
发明人： ESHUN EBENEZER E , HE ZHONG-XIANG , RASSEL ROBERT M , COOLBAUGH DOUGLAS , GEBRESELASIE EPHREM G , WANG PING-CHUAN , KIM DEOK-KEE , KOTHANDARAMAN CHANDRASEKHARAN , ROBSON NORMAN W , MOY DAN , SAFRAN JOHN M , STEIN KENNETH J , HO HERBERT L , YAN HONGWEN
IPC分类号： H01L21/335
CPC分类号： H01L27/0629 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in part simultaneously upon an isolation region laterally separated from the active region within the semiconductor substrate. The field effect device includes a gate dielectric comprising a high dielectric constant dielectric material and a gate electrode comprising a metal material. The at least one of the fuse structure, anti-fuse structure and resistor structure includes a pad dielectric comprising the same material as the gate dielectric, and optionally, also a fuse, anti-fuse or resistor that may comprise the same metal material as the gate electrode.
摘要翻译：半导体结构和半导体结构的制造方法提供一种场效应器件，其位于和形成在半导体衬底的有源区上，并且至少一个熔丝结构，抗熔丝结构和电阻结构中的至少一个至少位于并形成部分地同时地在与半导体衬底内的有源区域横向分离的隔离区域上。场效应器件包括包括高介电常数介电材料的栅极电介质和包括金属材料的栅电极。熔丝结构，反熔丝结构和电阻器结构中的至少一个包括包括与栅极电介质相同的材料的焊盘电介质，以及可选地还包括熔断器，反熔丝或电阻器，其可以包括与所述栅极电介质相同的金属材料栅电极。

6. 发明申请

WO2012012157A3 SCHOTTKY BARRIER DIODE WITH PERIMETER CAPACITANCE WELL JUNCTION 审中-公开
标题翻译：肖特基势垒二极管，具有周波电容和结
公开(公告)号：WO2012012157A3
公开(公告)日：2012-04-26
申请号：PCT/US2011042296
申请日：2011-06-29
申请人： IBM , ANDERSON FREDERICK G , LARY JENIFER E , RASSEL ROBERT M , STIDHAM MARK E
发明人： ANDERSON FREDERICK G , LARY JENIFER E , RASSEL ROBERT M , STIDHAM MARK E
IPC分类号： H01L29/872 , H01L29/47
CPC分类号： H01L29/872 , H01L21/761 , H01L29/0619 , H01L29/0646 , H01L29/0692 , H01L29/66143
摘要： A Schottky barrier diode comprises a first-type substrate (100), a second-type well isolation region (102) on the first-type substrate, and a first-type well region (110) on the second-type well isolation region. With embodiments herein a feature referred to as a perimeter capacitance well junction ring (106) is on the second-type well isolation region. A second-type well region (104) is on the second-type well isolation region. The perimeter capacitance well junction ring is positioned between and separates the first-type well region and the second-type well region. A second-type contact region (108) is on the second-type well region, and a first-type contact region (112) contacts the inner portion of the first-type well region. The inner portion of the first-type well region is positioned within the center of the first-type contact region. Additionally, a first ohmic metallic layer (124) is on the first- type contact region and a second ohmic metallic layer (126) is on the first-type well region. The first ohmic metallic layer contacts the second ohmic metallic layer at a junction that makes up the Schottky barrier of the Schottky barrier diode.
摘要翻译：肖特基势垒二极管包括第一类型衬底（100），在第一类型衬底上的第二类型阱隔离区域（102）以及在第二类型阱隔离区域上的第一类型阱区域（110）。通过本文的实施例，被称为周边电容阱结环（106）的特征位于第二类型阱隔离区上。第二类型阱区（104）位于第二类型阱隔离区上。周边电容阱连接环位于第一类型阱区和第二类型阱区之间并将其隔开。第二类型接触区域（108）位于第二类型阱区域上，并且第一类型接触区域（112）接触第一类型阱区域的内部部分。第一类型阱区的内部位于第一类型接触区的中心内。此外，第一欧姆金属层（124）位于第一型接触区上，而第二欧姆金属层（126）位于第一型阱区上。第一欧姆金属层在构成肖特基势垒二极管的肖特基势垒的结处与第二欧姆金属层接触。

7. 发明申请

WO2012106101A3 A SCHOTTKY BARRIER DIODE, A METHOD OF FORMING THE DIODE AND A DESIGN STRUCTURE FOR THE DIODE 审中-公开
标题翻译：肖特基二极管二极管，形成二极管的方法和二极管的设计结构
公开(公告)号：WO2012106101A3
公开(公告)日：2012-10-26
申请号：PCT/US2012021483
申请日：2012-01-17
申请人： IBM , RASSEL ROBERT M , STIDHAM MARK E
发明人： RASSEL ROBERT M , STIDHAM MARK E
IPC分类号： H01L29/872 , H01L21/328
CPC分类号： H01L29/66143 , G06F17/5068 , H01L29/872
摘要： Disclosed are embodiments of a Schottky barrier diode (100). This Schottky barrier diode can be formed in a semiconductor substrate (101) having a doped region (110) with a first conductivity type. A trench isolation structure (120) can laterally surround a section (111) of the doped region at the top surface (102) of the substrate. A semiconductor layer (150) can be positioned on the top surface of the substrate. This semiconductor layer can have a Schottky barrier portion (151) over the defined section (111) of the doped region and a guardring portion (152) over the trench isolation structure laterally surrounding the Schottky barrier portion. The Schottky barrier portion can have the first conductivity type and the guarding portion can have a second conductivity type different from the first conductivity type. A metal silicide layer (140) can overlie the semiconductor layer. Also disclosed are embodiments of a method of forming this Schottky barrier diode and of a design structure for the Schottky barrier diode.
摘要翻译：公开了肖特基势垒二极管（100）的实施例。该肖特基势垒二极管可以形成在具有第一导电类型的掺杂区域（110）的半导体衬底（101）中。沟槽隔离结构（120）可横向地围绕衬底的顶表面（102）处的掺杂区域的部分（111）。半导体层（150）可以位于衬底的顶表面上。该半导体层可以在掺杂区域的限定部分（111）上方具有肖特基势垒部分（151），并且在沟槽隔离结构之上的护套部分（152）横向围绕肖特基势垒部分。肖特基势垒部分可以具有第一导电类型，并且保护部分可以具有不同于第一导电类型的第二导电类型。金属硅化物层（140）可以覆盖半导体层。还公开了形成该肖特基势垒二极管的方法和肖特基势垒二极管的设计结构的实施例。

8. 发明申请

WO2007082200A3 SEMICONDUCTOR STRUCTURE INCLUDING TRENCH CAPACITOR AND TRENCH RESISTOR 审中-公开
标题翻译：半导体结构，包括TRENCH电容和TRENCH电阻
公开(公告)号：WO2007082200A3
公开(公告)日：2008-07-03
申请号：PCT/US2007060266
申请日：2007-01-09
申请人： IBM , CHENG KANGGUO , RASSEL ROBERT M
发明人： CHENG KANGGUO , RASSEL ROBERT M
IPC分类号： H01L29/94
CPC分类号： H01L29/945 , H01L27/016 , H01L27/0682 , H01L28/20 , H01L29/66181
摘要： A structure and a method for fabrication of the structure use a capacitor trench (CT) for a trench capacitor and a resistor trench (RT) for a trench resistor. The structure is typically a semiconductor structure. In a first instance, the capacitor trench (CT) has a linewidth dimension (LWC) narrower than the resistor trench (RT). The trench linewidth difference provides an efficient method for fabricating the trench capacitor and the trench resistor. In a second instance, the trench resistor comprises a conductor material (18a, 18b) at a periphery of the resistor trench (RT) and a resistor material (20) at a central portion of the resistor trench (RT).
摘要翻译：用于制造结构的结构和方法使用用于沟槽电容器的电容器沟槽（CT）和用于沟槽电阻器的电阻器沟槽（RT）。该结构通常是半导体结构。在第一种情况下，电容器沟槽（CT）具有比电阻器沟槽（RT）窄的线宽尺寸（LWC）。沟槽线宽差提供了制造沟槽电容器和沟槽电阻器的有效方法。在第二种情况下，沟槽电阻器包括在电阻器沟槽（RT）的外围的导体材料（18a，18b）和电阻器沟槽（RT）的中心部分处的电阻材料（20）。

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