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71. 发明申请

WO2008088135A1 MULTIPLE VALUED DYNAMIC RANDOM ACCESS MEMORY CELL AND THEREOF ARRAY USING SINGLE ELECTRON TRANSISTOR 审中-公开
标题翻译：多值动态随机访问存储单元及其使用单电子晶体管的阵列
公开(公告)号：WO2008088135A1
公开(公告)日：2008-07-24
申请号：PCT/KR2007/006695
申请日：2007-12-20
申请人： EXCEL Semiconductor Inc, , SONG, Bok Nam , CHOI, Jung Bum , KYE, Hun Woo
发明人： SONG, Bok Nam , CHOI, Jung Bum , KYE, Hun Woo
IPC分类号： G11C11/405
CPC分类号： G11C11/4085 , G11C11/405 , G11C11/406 , G11C11/56 , G11C2211/4065 , G11C2216/08
摘要： Provided is a multi- valued dynamic random access memory (DRAM) cell using a single electron transistor (SET). The multi- valued DRAM cell using the SET applies different refresh signals to a load current transistor for controlling current supply to the SET and a voltage control transistor for controlling a terminal voltage of the SET and refreshes a data value stored in the SET by a predetermined period to reduce standby current and stably supply a voltage low enough to satisfy a coulomb-blockade condition to the terminal of the SET.
摘要翻译：提供了使用单电子晶体管（SET）的多值动态随机存取存储器（DRAM）单元。使用SET的多值DRAM单元对用于控制对SET的电流供给的负载电流晶体管施加不同的刷新信号，以及用于控制SET的端子电压的电压控制晶体管，并且将存储在SET中的数据值刷新预定的以减少待机电流并稳定地提供足够低的电压以满足库仑封锁状态到SET的端子。

72. 发明申请

WO2007084749A3 METHOD AND SYSTEM FOR ERROR CORRECTION IN FLASH MEMORY 审中-公开
标题翻译：闪存中错误校正的方法和系统
公开(公告)号：WO2007084749A3
公开(公告)日：2008-04-10
申请号：PCT/US2007001620
申请日：2007-01-19
申请人： MARVELL WORLD TRADE LTD , RAMAMOORTHY ADITYA , WU ZINING , SUTARDJA PANTAS
发明人： RAMAMOORTHY ADITYA , WU ZINING , SUTARDJA PANTAS
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G06F11/1068 , G06F11/1072 , G06F11/1666 , G06F2212/403 , G11C7/02 , G11C7/1006 , G11C7/16 , G11C11/56 , G11C11/5621 , G11C16/10 , G11C27/005 , G11C29/00 , G11C2029/0411 , G11C2207/16 , G11C2211/562 , G11C2211/563 , H03M13/1177 , H03M13/1515
摘要： A solid state non-volatile memory unit. The memory unit includes a multi-level solid state non-volatile memory array adapted to store data characterized by a first number of digital levels. The memory unit also includes an analog-to-digital converter having an input and an output. The input of the analog-to-digital converter is adapted to receive data from the multi-level solid state non-volatile memory array. The output of the analog-to-digital converter is adapted to output a digital signal characterized by a second number of digital levels greater than the first number of digital levels.
摘要翻译：固态非易失性存储器单元。存储单元包括适于存储以第一数量级数字表征的数据的多级固态非易失性存储器阵列。存储器单元还包括具有输入和输出的模拟 - 数字转换器。模拟 - 数字转换器的输入适于从多级固态非易失性存储器阵列接收数据。模拟 - 数字转换器的输出适于输出特征在于数字电平大于第一数字电平数量的第二数字电平的数字信号。

73. 发明申请

WO2008016420A3 MULTI-USE MEMORY CELL AND MEMORY ARRAY AND METHOD FOR USE THEREWITH 审中-公开
标题翻译：多用途存储器单元和存储器阵列及其使用方法
公开(公告)号：WO2008016420A3
公开(公告)日：2008-03-27
申请号：PCT/US2007013770
申请日：2007-06-12
申请人： SANDISK 3D LLC , SCHEUERLEIN ROY E , KUMAR TANMAY
发明人： SCHEUERLEIN ROY E , KUMAR TANMAY
IPC分类号： G11C17/14 , G11C11/56 , G11C13/00
CPC分类号： G11C11/56 , G11C13/00 , G11C17/06 , G11C17/16 , G11C17/165 , G11C17/18 , G11C29/027 , G11C29/028 , G11C2211/5641
摘要： A multi-use memory cell and memory array and a method for use therewith are disclosed. In one preferred embodiment, a memory cell is operable as a one-time programmable memory cell or a rewritable memory cell. The memory cell comprises a memory element comprising a semiconductor material configurable to one of at least three resistivity states, wherein a first resistivity state is used to represent a data state of the memory cell when the memory cell operates as a one-time programmable memory cell but not when the memory cell operates as a rewritable memory cell. A memory array with such memory cells is also disclosed. In another preferred embodiment, a memory cell is provided comprising a switchable resistance material, wherein the memory cell is operable in a first mode in which the memory cell is programmed with a forward bias and a second mode in which the memory cell is programmed with a reverse bias.
摘要翻译：公开了一种多用途存储单元和存储器阵列及其使用方法。在一个优选实施例中，存储器单元可操作为一次性可编程存储器单元或可重写存储单元。存储单元包括存储元件，其包括可配置为至少三种电阻率状态之一的半导体材料，其中当存储器单元作为一次可编程存储单元操作时，第一电阻率状态用于表示存储单元的数据状态但是当存储器单元作为可重写存储单元时不起作用。还公开了具有这种存储单元的存储器阵列。在另一个优选实施例中，提供了一种包括可切换电阻材料的存储单元，其中存储单元可在第一模式中操作，其中存储单元用正向偏置和第二模式编程，其中存储单元用反向偏差。

74. 发明申请

WO2008016421A2 MIXED-USE MEMORY ARRAY WITH DIFFERENT DATA STATES AND METHOD FOR USE THEREWITH 审中-公开
标题翻译：具有不同数据状态的混合使用存储器阵列及其使用方法
公开(公告)号：WO2008016421A2
公开(公告)日：2008-02-07
申请号：PCT/US2007/013772
申请日：2007-06-12
申请人： SANDISK 3D LLC , SCHEUERLEIN, Roy, E. , PETTI, Christopher, J.
发明人： SCHEUERLEIN, Roy, E. , PETTI, Christopher, J.
IPC分类号： G11C13/02
CPC分类号： G11C17/165 , G11C11/56 , G11C11/5692 , G11C13/0002 , G11C17/16 , G11C29/76 , G11C2211/5641 , G11C2211/5646 , G11C2213/72
摘要： A mixed-use memory array with different data states and a method for use therewith are disclosed. In one preferred embodiment, a memory array is provided comprising a plurality of memory cells, each memory cell comprising a memory element comprising a switchable resistance material configurable to one of at least three resistivity states. A first set of memory cells uses X resistivity states to represent X respective data states, and a second set of memory cells uses Y resistivity states to represent Y respective data states, wherein X≠Y.
摘要翻译：公开了具有不同数据状态的混合使用存储器阵列及其使用方法。在一个优选实施例中，提供包括多个存储单元的存储器阵列，每个存储单元包括存储元件，存储元件包括可配置为至少三个电阻率状态之一的可切换电阻材料。第一组存储器单元使用X电阻率状态来表示X个相应的数据状态，并且第二组存储器单元使用Y电阻率状态来表示Y个相应的数据状态，其中X≥Y。

75. 发明申请

WO2007134062A2 SENSING LIGHT AND SENSING THE STATE OF A MEMORY CELL 审中-公开
标题翻译：感知光和感知记忆细胞的状态
公开(公告)号：WO2007134062A2
公开(公告)日：2007-11-22
申请号：PCT/US2007/068484
申请日：2007-05-08
申请人： SLICEX, INC. , HALES, Rex K. , JOHANCSIK, Tracy , WOLF, Thomas L.
发明人： HALES, Rex K. , JOHANCSIK, Tracy , WOLF, Thomas L.
IPC分类号： G06F11/00
CPC分类号： H03K3/03 , G01J1/46 , G11C11/56 , G11C11/5642 , G11C2211/563 , G11C2211/5644
摘要： A light-to-frequency converter includes a switch (130) connected in series with a reverse-biased photodiode (120). A node (150) in the current path through the switch and the photodiode is connected to the input of a Schmidt trigger (160), whose output controls the switch. New techniques are provided for motion compensation, partial readouts, dark current elimination, non-destructive testing, and sensing the state of a memory cell.
摘要翻译：光频变换器包括与反向偏置光电二极管（120）串联连接的开关（130）。通过开关和光电二极管的电流路径中的节点（150）连接到施密特触发器（160）的输入端，其输出控制开关。提供了新的技术用于运动补偿，部分读数，暗电流消除，非破坏性测试以及感测存储单元的状态。

76. 发明申请

WO2007132456A2 MEMORY DEVICE WITH ADAPTIVE CAPACITY 审中-公开
标题翻译：具有适应能力的存储器件
公开(公告)号：WO2007132456A2
公开(公告)日：2007-11-22
申请号：PCT/IL2007/000579
申请日：2007-05-10
申请人： ANOBIT TECHNOLOGIES LTD. , SHALVI, Ofir , SOKOLOV, Dotan , MAISLOS, Ariel , COHEN, Zeev , GURGI, Eyal , SEMO, Gil
发明人： SHALVI, Ofir , SOKOLOV, Dotan , MAISLOS, Ariel , COHEN, Zeev , GURGI, Eyal , SEMO, Gil
IPC分类号： H04N7/14
CPC分类号： G11C16/349 , G06F2212/7205 , G06F2212/7206 , G11C11/56 , G11C11/5607 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C11/565 , G11C11/5657 , G11C11/5671 , G11C11/5678 , G11C27/005 , G11C2211/5621 , G11C2211/5641
摘要： A method for data storage in a memory (28) that includes a plurality of analog memory cells (32) includes estimating respective achievable storage capacities of the analog memory cells. The memory cells are assigned respective storage configurations defining quantities of data to be stored in the memory cells based on the estimated achievable capacities. The data is stored in the memory cells in accordance with the respective assigned storage configurations. The achievable storage capacities of the analog memory cells are re-estimated after the memory has been installed in a host system and used for storing the data in the host system. The storage configurations are modified responsively to the re-estimated achievable capacities.
摘要翻译：一种用于在包括多个模拟存储器单元（32）的存储器（28）中的数据存储的方法包括估计模拟存储器单元的各个可实现的存储容量。根据估计的可实现的容量，为存储器单元分配相应的存储配置，其定义要存储在存储器单元中的数据量。数据根据相应的分配的存储配置存储在存储器单元中。在存储器已经安装在主机系统中并用于在主机系统中存储数据之后，重新估计模拟存储器单元的可实现的存储容量。存储配置根据重新估计的可实现容量进行修改。

77. 发明申请

WO2007102141A2 MULTI-BIT-PER-CELL FLASH MEMORY DEVICE WITH NON-BIJECTIVE MAPPING 审中-公开
标题翻译：具有非定向映射的多位单元闪速存储器件
公开(公告)号：WO2007102141A2
公开(公告)日：2007-09-13
申请号：PCT/IL2006/001251
申请日：2006-10-30
申请人： RAMOT AT TEL-AVIV UNIVERSITY LTD. , LITSYN, Simon , SHARON, Eran , ALROD, Idan
发明人： LITSYN, Simon , SHARON, Eran , ALROD, Idan
IPC分类号： G06F12/00
CPC分类号： G11C16/10 , G06F11/1072 , G11C7/1006 , G11C11/56 , G11C11/5628 , G11C16/0483 , G11C16/34 , G11C29/42 , G11C2211/5641
摘要： To store a plurality of input bits, the bits are mapped to a corresponding programmed state of one or more memory cells and the cell(s) is/are programmed to that corresponding programmed state. The mapping may be many-to-one or may be an "into" generalized Gray mapping. The cell(s) is/are read to provide a read state value that is transformed into a plurality of output bits, for example by maximum likelihood decoding or by mapping the read state value into a plurality of soft bits and then decoding the soft bits.
摘要翻译：为了存储多个输入位，这些位被映射到一个或多个存储器单元的相应的编程状态，并且单元被编程为相应的编程状态。映射可以是多对一的或者可以是“到”广义灰色映射。读取单元以提供被转换成多个输出位的读取状态值，例如通过最大似然解码或通过将读取状态值映射到多个软比特中，然后解码软比特。

78. 发明申请

WO2007044034A2 NANOSCALE WIRE-BASED DATA STORAGE 审中-公开
标题翻译：纳米线基数据存储
公开(公告)号：WO2007044034A2
公开(公告)日：2007-04-19
申请号：PCT/US2005/044212
申请日：2005-12-06
申请人： PRESIDENT AND FELLOWS OF HARVARD COLLEGE , LIEBER, Charles, M. , WU, Yue , YAN, Hao
发明人： LIEBER, Charles, M. , WU, Yue , YAN, Hao
IPC分类号： H01R24/00
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y30/00 , G11C11/22 , G11C11/223 , G11C11/54 , G11C11/56 , G11C11/5657 , G11C13/003 , G11C13/025 , G11C2213/16 , G11C2213/17 , G11C2213/18 , G11C2213/75 , G11C2213/77 , H01L29/0673 , H01L29/068 , H01L29/78391
摘要： The present invention generally relates to nanotechnology and submicroelectronic devices that can be used in circuitry and, in some cases, to nanoscale wires and other nanostructures able to encode data. One aspect of the invention provides a nanoscale wire or other nanostructure having a region that is electrically-polarizable, for example, a nanoscale wire may comprise a core and an electrically-polarizable shell. In some cases, the electrically-polarizable region is able to retain its polarization state in the absence of an external electric field. All, or only a portion, of the electricallypolarizable region may be polarized, for example, to encode one or more bits of data. In one set of embodiments, the electrically-polarizable region comprises a functional oxide or a ferroelectric oxide material, for example, BaTiO 3 , lead zirconium titanate, or the like. In some embodiments, the nanoscale wire (or other nanostructure) may further comprise other materials, for example, a separation region separating the electricallypolarizable region from other regions of the nanoscale wire. For example, in a nanoscale wire, one or more intermediate shells may separate the core from the electricallypolarizable shell.
摘要翻译：本发明一般涉及可用于电路中并且在某些情况下可用于纳米级线和其他能够编码数据的纳米结构的纳米技术和次级微电子器件。本发明的一个方面提供了具有可电极化的区域的纳米线或其他纳米结构，例如纳米线可以包括核和电极化壳。在一些情况下，电极化区域能够在没有外部电场的情况下保持其极化状态。例如，所有或只有一部分电极和可怕极化区域可以被极化，以编码一个或多个数据位。在一组实施例中，可电极化区域包括功能氧化物或铁电氧化物材料，例如BaTiO 3，钛酸铅锆等。在一些实施例中，纳米线（或其他纳米结构）可以进一步包括其他材料，例如将纳米级线的其他区域与电和可;的可极化区域分开的分离区域。例如，在纳米线中，一个或多个中间壳可以将芯与电极和可怕的极化壳分开。

79. 发明申请

WO2006007197A3 TRI-STATE CIRCUIT USING A NANOTUBE SWITCHING ELEMENTS 审中-公开
标题翻译：使用NANOTUBE开关元件的三态电路
公开(公告)号：WO2006007197A3
公开(公告)日：2006-12-21
申请号：PCT/US2005018468
申请日：2005-05-26
申请人： NANTERO INC , BERTIN CLAUDE L
发明人： BERTIN CLAUDE L
IPC分类号： H03K19/00 , H03K19/20
CPC分类号： G11C11/56 , B82Y10/00 , G11C13/025 , G11C23/00 , H01H1/0094 , Y10S977/932 , Y10S977/936 , Y10S977/94
摘要： Nano-tube based logic circuitry is disclosed. Tri-stating elements (52, 56, 62, 66) add an enable/disable function to the circuitry. Tri- stating elements (52, 56, 62, 66) may be provided by nano-tube based switching devices (52, 56, 62, 66 ). In the disabled state, the outputs present a high impedance ie, are tristated, which state allows interconnection to a common bus or other shared communication lines. In embodiments wherein the components are non-volatile (52, 56, 62, 66), the inverter state and the control state are maintained in the absence of power. Such an inverter (20, 30) may be used in conjunction with and in the absence of diodes, resistors and transistors or as part of or as a replacement to CMOS, biCMOs, bipolar and other transistor level technologies.
摘要翻译：公开了基于纳管的逻辑电路。三态元件（52,56,62,66）向电路添加启用/禁用功能。三元件（52,56,62,66）可以由基于纳米管的开关装置（52,56,62,66）提供。在禁用状态下，输出呈现高阻抗，即三态化，哪种状态允许与公共总线或其他共享通信线路进行互连。在组件是非易失性的（52,56,66,66）的实施例中，在没有电力的情况下保持逆变器状态和控制状态。这种逆变器（20,30）可以与二极管，电阻器和晶体管结合使用，也可以在二极管，电阻器和晶体管的情况下使用，或者作为CMOS，biCM，双极和其他晶体管级技术的一部分或替代。

80. 发明申请

WO2006051455A1 MEMORY INTEGRATED CIRCUIT 审中-公开
标题翻译：内存集成电路
公开(公告)号：WO2006051455A1
公开(公告)日：2006-05-18
申请号：PCT/IB2005/053604
申请日：2005-11-04
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN ACHT, Victor, M., G. , MARSMAN, Albert, W. , CHONG, Boon, K. , LAMBERT, Nicolaas , WOERLEE, Pierre, H. , IKKINK, Teunis, J.
发明人： VAN ACHT, Victor, M., G. , MARSMAN, Albert, W. , CHONG, Boon, K. , LAMBERT, Nicolaas , WOERLEE, Pierre, H. , IKKINK, Teunis, J.
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/1036 , G11C7/1063 , G11C11/56
摘要： A memory integrated circuit contains a sensing circuit (12) that receives signals from addressed memory cells. The sensing circuit determines in which of a number of ranges the signals fall, the number of ranges being greater than the number values to which the cells can be programmed. An output circuit is provided that is arranged to supply either only data words that have been inferred from the detection, or also further information that provides more information about the ranges that have been detected than the data words only. Dependent on a control signal from external terminals of the memory integrated circuit the output circuit supplies the data words only to the external terminals or also the further information about the detected ranges in addition to the data words.
摘要翻译：存储器集成电路包含从寻址的存储器单元接收信号的感测电路（12）。感测电路确定信号下降的范围中的哪一个，范围的数量大于可以编程单元的数字值。提供了一种输出电路，其被布置为仅提供从检测中推断出的数据字，或者还提供了与仅数据字相比已经被检测的范围的更多信息的其他信息。取决于来自存储器集成电路的外部端子的控制信号，输出电路仅将数据字提供给外部端子，或者除了数据字之外还提供关于检测范围的进一步信息。

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