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1. 发明申请

WO2015066129A1 MULTI-BIT FERROELECTRIC MEMORY DEVICE AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：多位电磁存储器件及其形成方法
公开(公告)号：WO2015066129A1
公开(公告)日：2015-05-07
申请号：PCT/US2014/062820
申请日：2014-10-29
申请人： MICRON TECHNOLOGY, INC.
发明人： KARDA, Kamal M. , GEALY, F. Daniel , RAMASWAMY, D.V. Nirmal , MOULI, Chandra V.
IPC分类号： G11C11/22
CPC分类号： G11C11/5657 , G11C11/221 , G11C11/2273 , G11C11/2275 , H01L27/11507 , H01L28/40 , H01L43/02 , H01L43/12
摘要： Multi-bit ferroelectric memory devices and methods of forming the same are provided. One example method of forming a multi-bit ferroelectric memory device can include forming a first ferroelectric material on a first side of a via, removing a material to expose a second side of the via, and forming second ferroelectric material on the second side of the via at a different thickness compared to the first side of the via.
摘要翻译：提供了多位铁电存储器件及其形成方法。形成多位铁电存储器件的一个示例性方法可以包括在通孔的第一侧上形成第一铁电材料，去除材料以暴露通孔的第二面，并在第二侧上形成第二铁电材料与通孔的第一侧相比具有不同的厚度。

2. 发明申请

WO2012074776A2 ANALOG MEMORIES UTILIZING FERROELECTRIC CAPACITORS 审中-公开
标题翻译：使用电磁电容器的模拟记忆
公开(公告)号：WO2012074776A2
公开(公告)日：2012-06-07
申请号：PCT/US2011/061266
申请日：2011-11-17
申请人： RADIANT TECHNOLOGIES, INC. , EVANS, Joseph, T. , WARD, Calvin, B.
发明人： EVANS, Joseph, T. , WARD, Calvin, B.
IPC分类号： G11C11/22
CPC分类号： G11C11/221 , G11C11/2259 , G11C11/2273 , G11C11/2275 , G11C11/2293 , G11C11/5657 , G11C27/005
摘要： A ferroelectric memory having a plurality of ferroelectric memory cells, each ferroelectric memory cell including a ferroelectric capacitor is disclosed. The ferroelectric memory includes read and write lines and a plurality of ferroelectric memory cell select buses, one select bus corresponding to each of the ferroelectric memory cells. Each of the ferroelectric memory cells includes first and second gates for connecting the ferroelectric memory cell to the read line and the write line, respectively, in response to signals on the ferroelectric memory cell select bus corresponding to that ferroelectric memory cell. A write circuit causes a charge to be stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the write line, the charge having a value determined by a data value having at least three states. A read circuit measures the charge stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the read line to generate an output value, the output value corresponding to one of the states.
摘要翻译：公开了具有多个铁电存储单元的铁电存储器，每个强电介质存储单元包括铁电电容器。铁电存储器包括读写线和多个铁电存储器单元选择总线，每个铁电存储单元相应的一个选择总线。每个铁电存储单元包括用于响应于与该铁电存储单元相对应的强电介质存储单元选择总线上的信号而分别将铁电存储单元连接到读取线和写入线的第一和第二栅极。写入电路使得电荷存储在当前连接到写入线的铁电存储单元的铁电电容器中，电荷具有由具有至少三个状态的数据值确定的值。读取电路测量存储在当前连接到读取线的铁电存储器单元的铁电电容器中的电荷，以产生与其中一个状态对应的输出值。

3. 发明申请

WO2010036210A1 GRAPHENE MEMORY CELL AND FABRICATION METHODS THEREOF 审中-公开
标题翻译：石墨记忆体及其制造方法
公开(公告)号：WO2010036210A1
公开(公告)日：2010-04-01
申请号：PCT/SG2009000352
申请日：2009-09-23
申请人： UNIV SINGAPORE , OEZYILMAZ BARBAROS , ZHENG YI , NI GUANG XIN , TOH CHEE TAT
发明人： OEZYILMAZ BARBAROS , ZHENG YI , NI GUANG XIN , TOH CHEE TAT
IPC分类号： H01L21/8236 , G11C14/00 , G11C15/04
CPC分类号： G11C13/0014 , B82Y10/00 , G11C11/22 , G11C11/5657 , G11C11/5664 , G11C13/025 , G11C2213/35 , H01L29/1606 , H01L29/6684 , H01L29/7781 , H01L29/78391 , H01L29/78684
摘要： The disclosed memory cell (10) comprises a graphene layer (16) having controllable resistance states representing data values of the memory cell (10) In one exemplary embodiment a non- volatile memory is provided by having a ferroelectric layer (18) control the resistance states. In the exemplary embodiment, binary '0's and ' 1 's are respectively represented by low and high resistance states of the graphene layer (16), and these states are switched in a non-volatile manner by the polarization directions of the ferroelectric layer (18).
摘要翻译：所公开的存储器单元（10）包括具有表示存储器单元（10）的数据值的可控电阻状态的石墨烯层（16）。在一个示例性实施例中，通过使铁电层（18）控制电阻状态。在示例性实施例中，二进制“0”和“1”分别由石墨烯层（16）的低电阻状态和高电阻状态表示，并且这些状态以非易失性方式通过铁电层的极化方向（ 18）。

4. 发明申请

WO02054408A1 FERROELECTRIC MEMORY DEVICE AND ITS DRIVING METHOD 审中-公开
标题翻译：电磁存储器件及其驱动方法
公开(公告)号：WO02054408A1
公开(公告)日：2002-07-11
申请号：PCT/JP2001/011545
申请日：2001-12-27
IPC分类号： G11C11/22 , G11C11/56 , H01L21/8246 , H01L27/105 , H01L27/10
CPC分类号： G11C11/5657 , G11C11/22 , H01L27/11507
摘要： A ferroelectric memory device comprises a memory cell array where memory cells having at least a ferroelectric capacitors are arranged. By applying three or more different voltages (e.g., Vs, -Vc, -Vs) for bringing about three or more polarized states in the capacitors, each capacitor can selectively hold data of three or more values (e.g., Pr(0), P1(1), -Pr(2)).
摘要翻译：铁电存储器件包括其中布置有至少一个铁电电容器的存储单元的存储单元阵列。通过施加三个或更多个不同的电压（例如，Vs，-Vc，-Vs）以在电容器中产生三个或更多个极化状态，每个电容器可以选择性地保持三个或更多个值的数据（例如，Pr（0），P1 （1），-Pr（2））。

5. 发明申请

WO1997021223A1 NONVOLATILE CONTENT ADDRESSABLE MEMORY 审中-公开
标题翻译：非易失性内容可寻址存储器
公开(公告)号：WO1997021223A1
公开(公告)日：1997-06-12
申请号：PCT/CA1996000817
申请日：1996-12-06
申请人： SHEIKHOLESLAMI, Ali , GULAK, P., Glenn , HANYU, Takahiro
IPC分类号： G11C15/04
CPC分类号： G11C11/565 , G11C11/22 , G11C11/5657 , G11C15/046
摘要： Binary and multiple-valued nonvolatile content addressable memories (NVCAMs) use ferroelectric capacitors (634, 644, 714, 910, 918, 965, 976) as nonvolatile storage elements. The operation of the NVCAMs is accessed either in serial or in parallel. In a 2-bit NVCAM of a parallel access structure, search operation is performed by a simultaneous access to a 4-level polarization of the ferroelectric capacitor. The total number of search operations is reduced.
摘要翻译：二进制和多值非易失性内容可寻址存储器（NVCAM）使用铁电电容器（634,644,714,910,918,965,976）作为非易失性存储元件。 NVCAM的操作可以串行或并行访问。在并行访问结构的2位NVCAM中，通过同时访问铁电电容器的4电平极化来执行搜索操作。搜索操作的总数减少。

6. 发明申请

WO2017040053A1 METHODS OF OPERATING FERROELECTRIC MEMORY CELLS, AND RELATED FERROELECTRIC MEMORY CELLS 审中-公开
标题翻译：操作电磁记忆细胞的方法和相关的电磁记忆细胞
公开(公告)号：WO2017040053A1
公开(公告)日：2017-03-09
申请号：PCT/US2016/047584
申请日：2016-08-18
申请人： MICRON TECHNOLOGY, INC.
发明人： NICHOLES, Steven C. , CHAVAN, Ashonita A. , ROCKLEIN, Matthew N.
IPC分类号： G11C11/22 , H01L27/115
CPC分类号： G11C11/225 , G11C11/22 , G11C11/221 , G11C11/2273 , G11C11/2275 , G11C11/2297 , G11C11/5657 , G11C13/047 , G11C14/00 , H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/56 , H01L28/65 , H01L28/75
摘要： Methods of operating a ferroelectric memory cell. The method comprises applying one of a positive bias voltage and a negative bias voltage to a ferroelectric memory cell comprising a capacitor including a top electrode, a bottom electrode, a ferroelectric material between the top electrode and the bottom electrode, and an interfacial material between the ferroelectric material and one of the top electrode and the bottom electrode. The method further comprises applying another of the positive bias voltage and the negative bias voltage to the ferroelectric memory cell to switch a polarization of the ferroelectric memory cell, wherein an absolute value of the negative bias voltage is different from an absolute value of the positive bias voltage. Ferroelectric memory cells are also described.
摘要翻译：操作铁电存储单元的方法。该方法包括将正偏置电压和负偏置电压中的一个施加到包括上电极，底电极，顶电极和底电极之间的铁电材料的电容器和铁电存储单元之间的界面材料的铁电存储单元，铁电材料和顶电极和底电极之一。该方法还包括将另一个正偏置电压和负偏置电压施加到铁电存储单元以切换铁电存储单元的极化，其中负偏置电压的绝对值与正偏压的绝对值不同电压。还描述了铁电存储器单元。

7. 发明申请

WO2012074776A3 ANALOG MEMORIES UTILIZING FERROELECTRIC CAPACITORS 审中-公开
标题翻译：模拟记忆利用铁电电容
公开(公告)号：WO2012074776A3
公开(公告)日：2012-12-13
申请号：PCT/US2011061266
申请日：2011-11-17
申请人： RADIANT TECHNOLOGIES INC , EVANS JOSEPH T , WARD CALVIN B
发明人： EVANS JOSEPH T , WARD CALVIN B
IPC分类号： G11C11/22
CPC分类号： G11C11/221 , G11C11/2259 , G11C11/2273 , G11C11/2275 , G11C11/2293 , G11C11/5657 , G11C27/005
摘要： A ferroelectric memory having a plurality of ferroelectric memory cells, each ferroelectric memory cell including a ferroelectric capacitor is disclosed. The ferroelectric memory includes read and write lines and a plurality of ferroelectric memory cell select buses, one select bus corresponding to each of the ferroelectric memory cells. Each of the ferroelectric memory cells includes first and second gates for connecting the ferroelectric memory cell to the read line and the write line, respectively, in response to signals on the ferroelectric memory cell select bus corresponding to that ferroelectric memory cell. A write circuit causes a charge to be stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the write line, the charge having a value determined by a data value having at least three states. A read circuit measures the charge stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the read line to generate an output value, the output value corresponding to one of the states.
摘要翻译：公开了一种具有多个铁电存储器单元的铁电存储器，每个铁电存储器单元包括一个铁电电容器。铁电存储器包括读和写线以及多个铁电存储单元选择总线，一个选择总线对应于每个铁电存储单元。每个铁电存储单元包括第一和第二栅极，用于响应与该铁电存储单元对应的铁电存储单元选择总线上的信号，分别将铁电存储单元连接到读出线和写入线。写入电路使得电荷存储在当前连接到写入线的铁电存储器单元的铁电电容器中，该电荷具有由具有至少三个状态的数据值确定的值。读电路测量存储在当前连接到读线的铁电存储单元的铁电电容器中的电荷，以产生输出值，输出值对应于其中一个状态。

8. 发明申请

WO2007132456A2 MEMORY DEVICE WITH ADAPTIVE CAPACITY 审中-公开
标题翻译：具有适应能力的存储器件
公开(公告)号：WO2007132456A2
公开(公告)日：2007-11-22
申请号：PCT/IL2007/000579
申请日：2007-05-10
申请人： ANOBIT TECHNOLOGIES LTD. , SHALVI, Ofir , SOKOLOV, Dotan , MAISLOS, Ariel , COHEN, Zeev , GURGI, Eyal , SEMO, Gil
发明人： SHALVI, Ofir , SOKOLOV, Dotan , MAISLOS, Ariel , COHEN, Zeev , GURGI, Eyal , SEMO, Gil
IPC分类号： H04N7/14
CPC分类号： G11C16/349 , G06F2212/7205 , G06F2212/7206 , G11C11/56 , G11C11/5607 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C11/565 , G11C11/5657 , G11C11/5671 , G11C11/5678 , G11C27/005 , G11C2211/5621 , G11C2211/5641
摘要： A method for data storage in a memory (28) that includes a plurality of analog memory cells (32) includes estimating respective achievable storage capacities of the analog memory cells. The memory cells are assigned respective storage configurations defining quantities of data to be stored in the memory cells based on the estimated achievable capacities. The data is stored in the memory cells in accordance with the respective assigned storage configurations. The achievable storage capacities of the analog memory cells are re-estimated after the memory has been installed in a host system and used for storing the data in the host system. The storage configurations are modified responsively to the re-estimated achievable capacities.
摘要翻译：一种用于在包括多个模拟存储器单元（32）的存储器（28）中的数据存储的方法包括估计模拟存储器单元的各个可实现的存储容量。根据估计的可实现的容量，为存储器单元分配相应的存储配置，其定义要存储在存储器单元中的数据量。数据根据相应的分配的存储配置存储在存储器单元中。在存储器已经安装在主机系统中并用于在主机系统中存储数据之后，重新估计模拟存储器单元的可实现的存储容量。存储配置根据重新估计的可实现容量进行修改。

9. 发明申请

WO2007099277A1 MULTI-BIT MEMORY CELL STRUCTURES AND DEVICES 审中-公开
标题翻译：多位存储器单元结构和器件
公开(公告)号：WO2007099277A1
公开(公告)日：2007-09-07
申请号：PCT/GB2006/050045
申请日：2006-03-02
申请人： CAMBRIDGE ENTERPRISE LIMITED , BLAMIRE, Mark , KIM, Hyunho
发明人： BLAMIRE, Mark , KIM, Hyunho
IPC分类号： H01L27/22 , H01L27/115
CPC分类号： G11C11/22 , B82Y10/00 , G11C11/15 , G11C11/5607 , G11C11/5657 , H01L27/11502 , H01L27/11507 , H01L27/228
摘要： This invention is generally concerned with multi-bit memory cell structures, and memory devices incorporating such structures, as well as with related methods. More particularly the invention relates to the use of multiferroics in such structures and devices. A multi-bit memory cell structure is described. The cell structure comprises: a non-volatile magnetic memory storage structure having at least two switchable magnetic memory states; and a non-volatile electric memory storage structure having at least two switchable electric memory states; and wherein said magnetic and electric storage structures share a layer of multiferroic material.
摘要翻译：本发明通常涉及多位存储器单元结构，以及结合这种结构的存储器件以及相关方法。更具体地，本发明涉及在这种结构和装置中使用多铁性体。描述了多位存储单元结构。电池结构包括：具有至少两个可切换磁存储器状态的非易失性磁存储器结构; 以及具有至少两个可切换电存储器状态的非易失性电存储器结构; 并且其中所述磁性和电存储结构共享一层多铁性材料。

10. 发明申请

WO2007044034A2 NANOSCALE WIRE-BASED DATA STORAGE 审中-公开
标题翻译：纳米线基数据存储
公开(公告)号：WO2007044034A2
公开(公告)日：2007-04-19
申请号：PCT/US2005/044212
申请日：2005-12-06
申请人： PRESIDENT AND FELLOWS OF HARVARD COLLEGE , LIEBER, Charles, M. , WU, Yue , YAN, Hao
发明人： LIEBER, Charles, M. , WU, Yue , YAN, Hao
IPC分类号： H01R24/00
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y30/00 , G11C11/22 , G11C11/223 , G11C11/54 , G11C11/56 , G11C11/5657 , G11C13/003 , G11C13/025 , G11C2213/16 , G11C2213/17 , G11C2213/18 , G11C2213/75 , G11C2213/77 , H01L29/0673 , H01L29/068 , H01L29/78391
摘要： The present invention generally relates to nanotechnology and submicroelectronic devices that can be used in circuitry and, in some cases, to nanoscale wires and other nanostructures able to encode data. One aspect of the invention provides a nanoscale wire or other nanostructure having a region that is electrically-polarizable, for example, a nanoscale wire may comprise a core and an electrically-polarizable shell. In some cases, the electrically-polarizable region is able to retain its polarization state in the absence of an external electric field. All, or only a portion, of the electricallypolarizable region may be polarized, for example, to encode one or more bits of data. In one set of embodiments, the electrically-polarizable region comprises a functional oxide or a ferroelectric oxide material, for example, BaTiO 3 , lead zirconium titanate, or the like. In some embodiments, the nanoscale wire (or other nanostructure) may further comprise other materials, for example, a separation region separating the electricallypolarizable region from other regions of the nanoscale wire. For example, in a nanoscale wire, one or more intermediate shells may separate the core from the electricallypolarizable shell.
摘要翻译：本发明一般涉及可用于电路中并且在某些情况下可用于纳米级线和其他能够编码数据的纳米结构的纳米技术和次级微电子器件。本发明的一个方面提供了具有可电极化的区域的纳米线或其他纳米结构，例如纳米线可以包括核和电极化壳。在一些情况下，电极化区域能够在没有外部电场的情况下保持其极化状态。例如，所有或只有一部分电极和可怕极化区域可以被极化，以编码一个或多个数据位。在一组实施例中，可电极化区域包括功能氧化物或铁电氧化物材料，例如BaTiO 3，钛酸铅锆等。在一些实施例中，纳米线（或其他纳米结构）可以进一步包括其他材料，例如将纳米级线的其他区域与电和可;的可极化区域分开的分离区域。例如，在纳米线中，一个或多个中间壳可以将芯与电极和可怕的极化壳分开。

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