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61. 发明申请

WO2008130703A8 CLOCK SYNCHRONIZATION IN A MEMORY SYSTEM 审中-公开
标题翻译：记忆系统中的时钟同步
公开(公告)号：WO2008130703A8
公开(公告)日：2009-11-26
申请号：PCT/US2008005135
申请日：2008-04-18
申请人： RAMBUS INC , KIZER JADE M , WILSON JOHN M , EBLE JOHN III , WARE FREDERICK A
发明人： KIZER JADE M , WILSON JOHN M , EBLE JOHN III , WARE FREDERICK A
IPC分类号： G11C7/10 , G11C7/22
CPC分类号： G11C7/1066 , G11C7/1051 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C2207/2254
摘要： A system and method for synchronizing a strobed memory system 10. During memory read and/or memory write operations the corresponding data strobe is sampled at the data destination 50/55 according to a local clock signal 71/73. Based on ' the results of the sampling, the data strobe and local clock signal are synchronized. In this manner, the data is synchronized to the local clock signal so that sampling of data at the data destination can be performed according to the local clock signal rather than the data strobe.
摘要翻译：用于同步选通存储器系统10的系统和方法。在存储器读取和/或存储器写入操作期间，根据本地时钟信号71/73在数据目的地50/55处对相应的数据选通进行采样。基于“采样结果，数据选通和本地时钟信号同步。以这种方式，数据与本地时钟信号同步，使得可以根据本地时钟信号而不是数据选通来执行数据目的地的数据采样。

62. 发明申请

WO2009084796A1 READ ENABLE SIGNAL ADJUSTING FLASH MEMORY DEVICE AND READ CONTROL METHOD OF FLASH MEMORY DEVICE 审中-公开
标题翻译：读启动信号调整闪存存储器件和读存储器件的控制方法
公开(公告)号：WO2009084796A1
公开(公告)日：2009-07-09
申请号：PCT/KR2008/004964
申请日：2008-08-25
申请人： INDILINX CO., LTD. , CHUNG, Hyunmo , PARK, Hanmook
发明人： CHUNG, Hyunmo , PARK, Hanmook
IPC分类号： G11C16/26
CPC分类号： G11C16/32 , G11C16/04 , G11C29/02 , G11C29/023 , G11C29/028 , G11C29/50012 , G11C2207/2254
摘要： Disclosed is a flash memory device for adjusting a read signal timing and read control method of the flash memory device. The flash memory device include a plurality of flash memory units, a common input/output bus connected with each of the plurality of flash memory units, and a controller to propagate the read control signal to a flash memory unit selected from among the plurality of flash memories and to receive data read from the selected flash memory unit via the common input/output bus, the controller being connected with the common input/output bus, wherein the controller adjusts a propagation timing of the read control signal unit based on a propagation delay corresponding to the selected flash memory unit, and thereby controlling a timing optimized for each flash memory unit.
摘要翻译：公开了一种用于调整闪速存储器件的读取信号定时和读取控制方法的闪速存储器件。闪速存储装置包括多个闪存单元，与多个闪存单元中的每一个连接的公共输入/输出总线，以及控制器，用于将读取的控制信号传播到从多个闪存中选择的闪存单元存储器，并且经由公共输入/输出总线接收从所选择的闪存单元读取的数据，控制器与公共输入/输出总线连接，其中控制器基于传播延迟来调整读取控制信号单元的传播定时对应于所选择的闪存单元，从而控制针对每个闪存单元优化的定时。

63. 发明申请

WO2008148197A1 DYNAMIC IMPEDANCE CONTROL FOR INPUT/OUTPUT BUFFERS 审中-公开
标题翻译：输入/输出缓冲器的动态阻抗控制
公开(公告)号：WO2008148197A1
公开(公告)日：2008-12-11
申请号：PCT/CA2008/001069
申请日：2008-06-06
申请人： MOSAID Technologies Incorporated , MILLAR, Bruce
发明人： MILLAR, Bruce
IPC分类号： H03H7/38 , G11C11/407 , G11C7/10 , G11C7/12 , H03K19/0175
CPC分类号： H03K19/0005 , G11C5/063 , G11C7/02 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G11C11/4093 , G11C2207/2254 , H03H7/38 , H03H17/0045 , H04L25/0278 , H04L25/028
摘要： A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, the pull-up network is configured to produce a calibrated drive impedance when an "on" output is to be generated, and the pull-down network is configured to produce a calibrated drive impedance when an "off" output is to be generated. In termination mode, the pull- up network and the pull-down network are configured to produce a calibrated pull-up resistance and pull-down resistance, respectively, such that together they form a split termination.
摘要翻译：提供了执行片外驱动（OCD）和片上终止（ODT）的系统和方法。采用由晶体管组成的公共上拉网络和由晶体管组成的公共下拉网络来实现这两个功能。在驱动模式下，上拉网络被配置为当要产生“开”输出时产生校准的驱动阻抗，并且当“关”输出为“关”时，下拉网络被配置为产生校准的驱动阻抗生成。在终端模式中，上拉网络和下拉网络被配置为分别产生校准的上拉电阻和下拉电阻，使得它们一起形成分离终端。

64. 发明申请

WO2007105156A1 DOUBLE DATA RATE INTERFACE 审中-公开
标题翻译：双重数据速率接口
公开(公告)号：WO2007105156A1
公开(公告)日：2007-09-20
申请号：PCT/IB2007/050788
申请日：2007-03-09
申请人： NXP B.V. , REDMAN-WHITE, William
发明人： REDMAN-WHITE, William
IPC分类号： G11C7/10
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/222 , G11C11/4076 , G11C2207/2254
摘要： The present invention relates to a double data rate interface and method for use between a processor and random access memory, comprising a delay line including means for creating a delay in a data strobe signal from the random access memory, the delay line being arranged such that the delay in the data strobe signal is equal to the sum of set-up time and data bus rise time. The interface of includes the delay line comprising the delay locked loop which in turn comprises a ring oscillator. The ring oscillator includes a buffer and a Vernier delay.
摘要翻译：本发明涉及在处理器与随机存取存储器之间使用的双数据速率接口和方法，包括延迟线，包括用于从随机存取存储器产生数据选通信号的延迟的装置，所述延迟线被布置成使得数据选通信号的延迟等于设置时间和数据总线上升时间之和。该接口包括延迟线，该延迟线包括延迟锁定环，该延迟锁定环又包括环形振荡器。环形振荡器包括缓冲器和游标延迟。

65. 发明申请

WO2006121874A3 MEMORY DEVICE AND METHOD HAVING A DATA BYPASS PATH TO ALLOW RAPID TESTING AND CALIBRATION 审中-公开
标题翻译：具有数据旁路的存储器件和方法允许快速测试和校准
公开(公告)号：WO2006121874A3
公开(公告)日：2007-08-02
申请号：PCT/US2006017439
申请日：2006-05-04
申请人： MICRON TECHNOLOGY INC , JOHNSON JAMES B , MANNING TROY A
发明人： JOHNSON JAMES B , MANNING TROY A
IPC分类号： G01R31/26
CPC分类号： G11C7/1039 , G11C7/1048 , G11C11/401 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/028 , G11C29/50012 , G11C2207/105 , G11C2207/2254
摘要： A synchronous dynamic random access memory ("SDRAM") device (100) includes a pipelined write data path coupling data from a data bus to a DRAM array (122), and a pipelined read data path coupling read data from the array ((122) to the data bus. The SDRAM device also includes a bypass path allowing the write data in the write data path to be coupled directly to the read data path without firs being stored in the DRAM array. The write data are preferably coupled through the write data path by issuing a write command to the DRAM device, and the read data are preferably coupled through the read data path by issuing a read command to the DRAM device. The memory array is inhibited from responding to these commands so that the write data are not stored in the array, and read data from the array are not coupled to the read data path.
摘要翻译：同步动态随机存取存储器（“SDRAM”）装置（100）包括将从数据总线到DRAM阵列（122）的数据耦合的流水线写入数据路径，以及将读取数据从阵列（（122 ）SDRAM装置还包括旁路路径，允许写入数据路径中的写入数据直接耦合到读取数据路径，而没有保存在DRAM阵列中的数据，写入数据优选地通过写入通过向DRAM设备发出写入命令，读取数据优选地通过读取数据路径耦合到DRAM设备，读取命令被禁止响应于这些命令，使得写入数据是不存储在阵列中，并且从阵列读取数据不会耦合到读取的数据路径。

66. 发明申请

WO2007078994A2 CONFIGURABLE INPUTS AND OUTPUTS FOR MEMORY STACKING SYSTEM AND METHOD 审中-公开
标题翻译：用于存储堆栈系统和方法的可配置输入和输出
公开(公告)号：WO2007078994A2
公开(公告)日：2007-07-12
申请号：PCT/US2006/048812
申请日：2006-12-21
申请人： MICRON TECHNOLOGY, INC. , JANZEN, Jeffery
发明人： JANZEN, Jeffery
CPC分类号： G11C7/1078 , G11C5/02 , G11C5/04 , G11C7/109 , G11C7/22 , G11C7/225 , G11C11/4093 , G11C11/4096 , G11C2207/2254 , H01L25/0657 , H01L2224/16145 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/01055
摘要： Embodiments of the present invention relate to configurable inputs and/or outputs for memory and memory stacking applications. More specifically, embodiments of the present invention include memory devices that include a die having a circuit configured for enablement by a particular signal, an input pin configured to receive the particular signal, and a path selector configured to selectively designate a signal path to the circuit from the input pin.
摘要翻译：本发明的实施例涉及用于存储器和存储器堆叠应用的可配置输入和/或输出。更具体地，本发明的实施例包括存储器件，其包括具有配置为通过特定信号实现的电路的管芯，被配置为接收特定信号的输入引脚，以及路径选择器，其被配置为选择性地指定到电路的信号路径从输入引脚。

67. 发明申请

WO2005078734A1 ＤＬＬ回路审中-公开
标题翻译： DLL电路
公开(公告)号：WO2005078734A1
公开(公告)日：2005-08-25
申请号：PCT/JP2005/001894
申请日：2005-02-09
申请人：シャープ株式会社 , 凸版印刷株式会社 , 前田賢吾 , 谷川明 , 西山増治 , 大堀庄一 , 平野誠 , 高島洋 , 的場伸次 , 浅野正通
发明人：前田賢吾 , 谷川明 , 西山増治 , 大堀庄一 , 平野誠 , 高島洋 , 的場伸次 , 浅野正通
IPC分类号： G11C16/32
CPC分类号： H03L7/0814 , G11C7/1072 , G11C7/222 , G11C16/32 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2207/2254 , H03K5/133 , H03K2005/00019 , H03L7/0818
摘要：　本発明のＤＬＬ回路は、基準クロックと遅延クロックとの位相を比較する位相比較回路と、位相比較回路からの信号により遅延量を調節する可変遅延付加回路とを有するＤＬＬ回路であって、バースト開始時に、内部クロックの１クロック周期の開始により論理“１”にラッチされる第１の信号を、ダミー遅延を通して可変遅延付加回路に入力する手段と、可変遅延付加回路によりダミー遅延を通して入力された第１の信号の論理“１”の継続時間を内部クロックの１クロック周期の終了まで検出し、継続時間を基に可変遅延付加回路の遅延量の初期値を設定する手段と、を備える。
摘要翻译： DLL电路具有比较参考时钟的相位和延迟时钟的相位的相位比较电路; 以及可变延迟加法电路，其基于来自相位比较电路的信号来调整延迟量。 DLL电路包括用于通过虚拟延迟输入在突发开始时通过内部时钟的周期的开始被锁存到逻辑“1”的第一信号的装置; 以及用于确定经由虚拟延迟从可变延迟加法电路接收到的第一信号的逻辑“1”的持续时间的装置，直到内部时钟的周期结束，基于持续时间来建立可变延迟加法电路的延迟量的初始值。

68. 发明申请

WO2004077439A2 AN APPARATUS AN METHOD FOR A CONFIGURABLE MIRROR FAST SENSE AMPLIFIER 审中-公开
标题翻译：一种用于可配置反射镜快速感测放大器的装置
公开(公告)号：WO2004077439A2
公开(公告)日：2004-09-10
申请号：PCT/US2004/004729
申请日：2004-02-17
申请人： ATMEL CORPORATION , BEDARIDA, Lorenzo , SACCO, Andrea , MARZIANI, Monica
发明人： BEDARIDA, Lorenzo , SACCO, Andrea , MARZIANI, Monica
IPC分类号： G11C
CPC分类号： G11C16/28 , G11C7/062 , G11C7/14 , G11C2207/063 , G11C2207/2254
摘要： A configurable mirror sense amplifier system for flash memory having the following features. A power source generates a reference voltage. A plurality of transistors is biased at the reference voltage. The plurality of transistors is each coupled to a second transistor. Each of the plurality of transistors is also configured to provide a current for comparison with the flash memory. The reference voltage is internal, stable and independent from variations of a power supply or temperature. The plurality of transistors is in parallel with one another. A mirror transistor is coupled to the plurality of transistors. The plurality of transistors is configured so that at least one of at least one transistor is activated with a signal in order to provide the current for comparison to the flash memory. Also, the reference voltage may be modified in order to modify the current for comparison to the flash memory.
摘要翻译：用于闪存的可配置镜像读出放大器系统具有以下特征。电源产生参考电压。多个晶体管偏置在参考电压。多个晶体管各自耦合到第二晶体管。多个晶体管中的每一个还被配置为提供用于与闪存进行比较的电流。参考电压是内部的，稳定的并且与电源或温度的变化无关。多个晶体管彼此并联。镜像晶体管被耦合到多个晶体管。多个晶体管被配置为使得至少一个晶体管中的至少一个晶体管被信号激活以提供用于与闪存进行比较的电流。此外，参考电压可能会修改，以修改电流以与闪存进行比较。

69. 发明申请

WO2004008326A3 SYSTEM AND METHOD FOR IMPROVED SYNCHRONOUS DATA ACCESS 审中-公开
标题翻译：改进的同步数据访问的系统和方法
公开(公告)号：WO2004008326A3
公开(公告)日：2004-04-08
申请号：PCT/US0321791
申请日：2003-07-14
申请人： GLOBESPAN VIRATA INC
发明人： HELZER AMIR
IPC分类号： G11C7/10 , G11C7/22 , G06F13/42 , G06F13/16
CPC分类号： G11C7/1066 , G11C7/1051 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C2207/2254
摘要： A system and method for improved synchronous access of stored data are provided herein. A data requestor transmits a clock signal and a read request signal for reception by a data source, whereupon skewed versions of the clock signal and the read request signal are received due to the delays in the signal paths between the data requestor and the data source. Accordingly, the data requestor provides skewed clock and read request signals to its input sampling module to simulate the delays of the signal paths. Additionally, the data requestor provides process information associated with the requested data to a dual clock first in-first out (FIFO) buffer. When the input sampling module detects a read request using the skewed read request signal, the input sampling module can use this signal and the skewed clock signal to sample a data signal from the data source to obtain the requested data. Concurrently, the input sampling module can access the process information from the dual clock FIFO buffer using the skewed clock signal. Based at least in part on this process information, one or more process operations can be performed on the requested data. In other implementations, the storage and subsequent access of process information from a dual-clock FIFO is omitted. The present invention finds particular benefit in accessing data stored in synchronous memory, such as synchronous dynamic random access memory (SDRAM) and synchronous static random access memory (SSRAM).
摘要翻译：本文提供了用于改进存储数据的同步访问的系统和方法。数据请求者发送用于由数据源接收的时钟信号和读取请求信号，由于数据请求者和数据源之间的信号路径的延迟，接收到时钟信号和读取请求信号的偏移版本。因此，数据请求者向其输入采样模块提供偏斜时钟和读取请求信号，以模拟信号路径的延迟。此外，数据请求器将与请求的数据相关联的处理信息提供给双时钟先进先出（FIFO）缓冲器。当输入采样模块使用偏斜的读取请求信号检测到读取请求时，输入采样模块可以使用该信号和偏斜时钟信号从数据源采样数据信号以获得所请求的数据。同时，输入采样模块可以使用偏斜时钟信号从双时钟FIFO缓冲器访问过程信息。至少部分地基于该处理信息，可以对所请求的数据执行一个或多个处理操作。在其他实现中，省略了来自双时钟FIFO的处理信息的存储和后续访问。本发明特别有利于存取存储在同步存储器中的数据，如同步动态随机存取存储器（SDRAM）和同步静态随机存取存储器（SSRAM）。

70. 发明申请

WO03012795A3 FUSE PROGRAMMABLE I/O ORGANIZATION 审中-公开
标题翻译：熔丝可编程I / O组织
公开(公告)号：WO03012795A3
公开(公告)日：2003-07-17
申请号：PCT/EP0208560
申请日：2002-07-31
申请人： INFINEON TECHNOLOGIES AG
发明人： FRANKOWSKY GERD , VASQUEZ BARBARA
IPC分类号： G11C7/10 , G11C29/00
CPC分类号： G11C7/1045 , G11C2207/105 , G11C2207/2254
摘要： Circuitry using fuse and anti-fuse latches (62) for selecting the number of input/output channels (98, 109) after encapsulation is disclosed. The various embodiments allow conventional bond pads (14, 16, 18) to be used for initial selection of the number of input/output channels prior to encapsulation. However, by providing different selection signals (52, 54), the number of input/output channels may be changed by the user at any time after encapsulation. Other embodiments employ "enable" latch circuits (133,135) allow the initial selection by the users at any time after encapsulation, and then at least one more subsequent selection.
摘要翻译：公开了使用熔断器和反熔断器锁存器（62）用于在封装之后选择输入/输出通道（98,109）的数量的电路。各种实施例允许常规键合焊盘（14,16,18）用于在封装之前初始选择多个输入/输出通道。然而，通过提供不同的选择信号（52,54），用户可以在封装后的任何时间改变输入/输出通道的数量。其他实施例采用“启用”锁存电路（133,135）允许用户在封装之后的任何时间进行初始选择，然后进行至少一次后续选择。

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