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1. 发明申请

WO2019084519A1 FRACTIONAL TIME DELAY STRUCTURES IN DIGITALLY OVERSAMPLED MICROPHONE SYSTEMS, CIRCUITS, AND METHODS 审中-公开
公开(公告)号：WO2019084519A1
公开(公告)日：2019-05-02
申请号：PCT/US2018/057879
申请日：2018-10-27
申请人： KOPIN CORPORATION
发明人： FAN, Dashen , KWON, Joseph, Yong
IPC分类号： H04R3/00 , H04R5/027
CPC分类号： H03K5/135 , H03K5/133 , H03K2005/00019 , H03K2005/00234 , H03K2005/0026 , H04R1/005 , H04R3/00 , H04R3/005 , H04R19/04 , H04R2201/003 , H04R2499/11 , H04R2499/13
摘要： An apparatus to time delay a digital signal output from an oversampled sensor includes a first time delay element and a second time delay element. The first time delay element has a first input and a first output. The first time delay element is configured to output a time delayed signal that is time delayed by an integer number of sampling clock cycles. An output of the oversampled sensor is connected to the first input of the first time delay element. The second time delay element has a second input and a second output and is configured to output a time delayed signal that is time delayed by an integer number of sampling clock cycles. The first output of the first time delay element is connected to the second input of the second time delay element, A multiplexer has a control input and a multiplexer output. The first output of the first time delay element is connected to a first multiplexer input. The second output of the second time delay element is connected to a second multiplexer input, in operation, time delay information is used to provide a signal to the control input to select a particular multiplexer input for output on the multiplexer output. The output of the oversampled sensor is time delayed by an amount provided by the particular multiplexer input.

2. 发明申请

WO2015143993A1 时间域集成温度传感器审中-公开
公开(公告)号：WO2015143993A1
公开(公告)日：2015-10-01
申请号：PCT/CN2015/074096
申请日：2015-03-12
申请人：卓捷创芯科技(深圳)有限公司 , 无锡智速科技有限公司
发明人：马彪 , 吴边 , 韩富强 , 漆射虎 , 罗远明
IPC分类号： G01K1/00
CPC分类号： G01K3/04 , G01K7/01 , G05F1/463 , H03K5/153 , H03K17/687 , H03K19/21 , H03K21/026 , H03K2005/00019
摘要：时间域集成温度传感器采用经过整形后的时钟信号对电容充电时间进行控制，使得电容产生与输入时钟周期相关的充电延时信号，一路PTAT电流按照以上的控制方式为电容充电产生的延时信号和一路CTAT电流按照同样方式为电容充电产生的延迟信号经过逻辑异或运算，产生其宽度与温度和输入时钟周期均相关的脉冲信号；于是采用同一输入时钟信号对该脉冲信号的脉冲宽度进行量化，得到的量化结果与输入时钟的周期的相关性完全抵消，即温度传感器的输出值与输入时钟信号的周期无关，解决了现有时间域集成温度传感器随其时钟信号周期变化而读数不一致的问题，一定程度提高了时间域集成温度传感器的精度。

3. 发明申请

WO2014155635A1 遅延回路、それを用いた電子回路および超音波撮像装置审中-公开
标题翻译：延迟电路，使用延迟电路和超声波成像装置的电子电路
公开(公告)号：WO2014155635A1
公开(公告)日：2014-10-02
申请号：PCT/JP2013/059412
申请日：2013-03-28
申请人：株式会社日立製作所
发明人：中川　樹生
IPC分类号： G11C27/00 , A61B8/00 , H03H11/26 , H03H19/00
CPC分类号： H03K5/133 , A61B8/4494 , A61B8/54 , G01S7/52025 , G01S7/5208 , G01S15/8927 , G10K11/346 , G11C27/00 , G11C27/024 , H03H11/265 , H03H19/00 , H03K2005/00019
摘要：　遅延時間の精度が高く、最大遅延時間が長く、かつ低消費電力な遅延回路および超音波撮像装置を提供する。アナログ入力信号が入力される入力線と、複数のアナログ信号メモリ素子と、出力線と、前記入力線と前記複数のアナログ信号メモリ素子との接続／非接続を制御する複数のサンプリングスイッチと、前記複数のアナログ信号メモリ素子と前記出力線との接続／非接続を制御する複数の出力スイッチと、前記サンプリングスイッチを制御するサンプリングスイッチ制御信号と、前記出力スイッチを制御する出力スイッチ制御信号を生成するクロック生成部と、を備え、前記サンプリングスイッチ制御信号の位相を、前記出力スイッチ制御信号の位相に対してずらすことができるように構成した。
摘要翻译：提供具有高度精确的延迟时间，长的最大延迟时间和低功耗的延迟电路和超声波成像装置。延迟电路包括：输入线，输入模拟输入信号; 多个模拟信号存储元件; 输出线多个采样开关，用于控制输入线和多个模拟信号存储元件之间的连接和断开; 多个输出开关，用于控制多个模拟信号存储元件与输出线之间的连接和断开; 以及用于产生用于控制采样开关的采样开关控制信号的时钟产生单元和用于控制输出开关的输出开关控制信号。采样开关控制信号的相位可以相对于输出开关控制信号的相位移动。

4. 发明申请

WO2010010482A9 INTEGRATED CIRCUIT 审中-公开
标题翻译：集成电路
公开(公告)号：WO2010010482A9
公开(公告)日：2014-09-04
申请号：PCT/IB2009053050
申请日：2009-07-14
申请人： NXP BV , VAN NOORT WIBO D , LETAVIC THEODORE J , ZAATO FRANCIS
发明人： VAN NOORT WIBO D , LETAVIC THEODORE J , ZAATO FRANCIS
IPC分类号： H01L21/8247 , G11C16/04 , G11C27/00 , G11C27/02 , H01L27/102 , H01L27/105 , H01L27/115 , H01L29/792 , H03M1/06 , H03M1/10
CPC分类号： H01L27/115 , G11C16/0416 , G11C27/005 , G11C2216/10 , H01L21/8249 , H01L27/1026 , H01L27/105 , H01L27/11517 , H01L29/792 , H03K5/133 , H03K2005/00019 , H03M1/802
摘要： An integrated circuit is provided, which comprises at least one first group each having at least one analog unit; and at least one second group each having at least one electronically settable semi-permanent switching unit coupled to the at least analog unit of the first group for trimming the first group and having at least one many-times-programmable and non-volatile cell (MTP). Each many-times-programmable cell (MTP) comprises at least one MOS transistor having a floating gate (FG) with a tunnel oxide (TO) and a first capacitor coupled to the floating gate (FG). The capacitance of the first capacitor is substantially larger than a gate-channel capacitance of the MOS transistor.

5. 发明申请

WO2005072298A3 CONFIGURABLE DELAY LINE CIRCUIT 审中-公开
标题翻译：可配置延时线路电路
公开(公告)号：WO2005072298A3
公开(公告)日：2006-08-24
申请号：PCT/US2005002138
申请日：2005-01-25
申请人： MOTOROLA INC , TOMERLIN ANDREW T , STENGEL ROBERT E
发明人： TOMERLIN ANDREW T , STENGEL ROBERT E
IPC分类号： H03H11/26 , H03K5/00 , H03K5/13 , H03L7/08 , H03L7/081 , H03L7/16
CPC分类号： H03L7/0802 , H03K5/133 , H03K2005/00019 , H03L7/0812 , H03L7/0814 , H03L7/16
摘要： A configurable circuit consistent with certain embodiments has a variable length delay line (10), the delay line (10) having an input (24) and having N delay elements (12, 14, 16, 18, , 20) to provide a plurality of N delayed outputs (T(0) through T(N)). The variable length delay line (10) also has a number of active delay elements determined by a program command. A configurable processing array (32) receives the delayed outputs from the active delay elements and secondary data (38). The configurable processing array has an array of configurable circuit elements (104, 130, 150). The configurable processing array is configured to process the delayed outputs and the secondary data (38) in a manner for which the invention is to be used. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.
摘要翻译：与某些实施例一致的可配置电路具有可变长度延迟线（10），延迟线（10）具有输入（24）并具有N个延迟元件（12,14,16,18，，20）以提供多个的N个延迟输出（T（0）到T（N））。可变长度延迟线（10）还具有由程序命令确定的多个有效延迟元件。可配置处理阵列（32）从主动延迟元件和辅助数据（38）接收延迟的输出。可配置处理阵列具有可配置电路元件（104,130,150）的阵列。可配置处理阵列被配置为以将要使用本发明的方式处理延迟的输出和辅助数据（38）。该摘要不被认为是限制性的，因为其它实施例可能偏离本摘要中描述的特征。

6. 发明申请

WO2016043844A1 DELAY CIRCUIT WITH PARALLEL DELAY LINES AND INTERNAL SWITCHES BETWEEN THE DELAY LINES 审中-公开
标题翻译：延时电路与延时线之间的延时电路和内部开关
公开(公告)号：WO2016043844A1
公开(公告)日：2016-03-24
申请号：PCT/US2015/041587
申请日：2015-07-22
申请人： QUALCOMM INCORPORATED
发明人： SINGH, Guneet , CHENG, Yuehchun Claire , DIFFENDERFER, Jan Christian , SRINIVAS, Vaishnav , KIM, Robert Won Chol
IPC分类号： G11C7/10 , G11C11/4076 , G11C29/02 , G11C7/22
CPC分类号： H03K5/13 , G11C7/1066 , G11C7/1093 , G11C7/222 , G11C11/4076 , G11C29/023 , G11C29/028 , H03K2005/00019
摘要： Systems and methods for delay control are described herein. In one embodiment, a delay circuit comprises a first delay path and a second delay path. The delay circuit also comprises a plurality of switches, wherein each switch is coupled between different points on the first and second delay paths, and each switch is configured to turn on or off in response to a respective one of a plurality of select signals. The delay circuit further comprises a multiplexer having a first input coupled to an output of the first delay path, a second input coupled to an output of the second delay path, and an output coupled to an output of the delay circuit, wherein the multiplexer is configured to selectively couple one of the outputs of the first and second delay paths to the output of the delay circuit in response to a second select signal.
摘要翻译：本文描述了用于延迟控制的系统和方法。在一个实施例中，延迟电路包括第一延迟路径和第二延迟路径。延迟电路还包括多个开关，其中每个开关耦合在第一和第二延迟路径上的不同点之间，并且每个开关被配置为响应于多个选择信号中的相应一个而导通或关断。延迟电路还包括多路复用器，其具有耦合到第一延迟路径的输出的第一输入，耦合到第二延迟路径的输出的第二输入和耦合到延迟电路的输出的输出，其中多路复用器是被配置为响应于第二选择信号选择性地将第一和第二延迟路径的输出之一耦合到延迟电路的输出。

7. 发明申请

WO2014196737A1 트랜지스터 턴 오프 제어 방식이 개선된 능동 다이오드 审中-公开
标题翻译：具有改进的晶体管关断控制方法的活性二极管
公开(公告)号：WO2014196737A1
公开(公告)日：2014-12-11
申请号：PCT/KR2014/003690
申请日：2014-04-25
申请人： 주식회사 맵스
发明人： 황종태 , 신현익 , 전상오 , 이준
IPC分类号： H01L29/86
CPC分类号： H03K17/687 , H03K5/13 , H03K5/2463 , H03K17/302 , H03K2005/00019 , H03K2017/307
摘要： 트랜지스터 턴 오프 제어 방식이 개선된 능동 다이오드가 개시된다. 이 능동 다이오드는 트랜지스터의 기생 다이오드 양단 전압을 비교하는 비교기, 및 상기 비교기의 비교 결과에 따라 상기 트랜지스터의 게이트 단자를 제어하는 게이트 드라이버를 포함하며, 나아가 상기 기생 다이오드의 양단 전압이 양이 되는 시점에 상기 트랜지스터가 턴 오프 되도록 제어하는 오프 시점 제어부를 더 포함한다. 이에 의해 능동 다이오드가 오프 되어야 할 시점에 오프 될 수 있게 된다.
摘要翻译：公开了一种具有改进的晶体管截止控制方法的有源二极管。有源二极管包括用于比较晶体管的寄生二极管的两端的电压和用于根据比较器的比较结果来控制晶体管的栅极端的栅极驱动器的电压的比较器，还包括关断时间控制器在寄生二极管两端的电压变为正时，控制晶体管截止。因此，有源二极管可以在有源二极管应该关断时关断。

8. 发明申请

WO2013026040A8 SYSTEM FOR CLOCKING AN INTEGRATED CIRCUIT 审中-公开
标题翻译：闭合集成电路的系统
公开(公告)号：WO2013026040A8
公开(公告)日：2013-08-08
申请号：PCT/US2012051479
申请日：2012-08-17
申请人： BROADCOM CORP , SIPPEL TIM
发明人： SIPPEL TIM
IPC分类号： H03K3/03 , G06F1/04 , H03K3/037 , H03K5/13
CPC分类号： H03L7/0802 , G06F1/26 , G06F1/32 , G06F1/3203 , G06F1/3228 , G06F12/14 , G06F21/44 , H01L2924/0002 , H03K3/0315 , H03K3/037 , H03K3/0375 , H03K5/133 , H03K19/01 , H03K2005/00019 , H03K2005/00026 , H03K2005/00058 , H03L7/097 , H03L7/0997 , H01L2924/00
摘要： Embodiments provide systems and methods for dynamically regulating the clock frequency of an integrated circuit (IC) based on the IC supply voltage. By doing so, the clock frequency is no longer constrained by a worst-case voltage level, and a higher effective clock frequency can be supported, increasing the IC performance. Embodiments include a wave clocking system which uses a plurality of delay chains configured to match substantially the delays of respective logic paths of the IC. As the delays of the logic paths vary with supply voltage and temperature changes, the delay chains matched to the logic paths experience substantially similar changes and are used to regulate the clock frequency of the IC.
摘要翻译：实施例提供了用于基于IC电源电压来动态地调节集成电路（IC）的时钟频率的系统和方法。通过这样做，时钟频率不再受最坏情况电压电平的约束，并且可以支持更高的有效时钟频率，从而提高了IC性能。实施例包括波时钟系统，其使用被配置为基本上匹配IC的相应逻辑路径的延迟的多个延迟链。随着逻辑路径的延迟随着电源电压和温度的变化而变化，与逻辑路径匹配的延迟链经历基本类似的改变，并用于调节IC的时钟频率。

9. 发明申请

WO2013026032A1 ADAPTIVE CLOCKING SCHEME TO ACCOMMODATE SUPPLY VOLTAGE TRANSIENTS 审中-公开
标题翻译：自适应时钟方案来调节供电电压瞬变
公开(公告)号：WO2013026032A1
公开(公告)日：2013-02-21
申请号：PCT/US2012/051451
申请日：2012-08-17
申请人： BROADCOM CORPORATION , PENZES, Paul , FULLERTON, Mark
发明人： PENZES, Paul , FULLERTON, Mark
IPC分类号： H03K3/03
CPC分类号： H03L7/0802 , G06F1/26 , G06F1/32 , G06F1/3203 , G06F1/3228 , G06F12/14 , G06F21/44 , H01L2924/0002 , H03K3/0315 , H03K3/037 , H03K3/0375 , H03K5/133 , H03K19/01 , H03K2005/00019 , H03K2005/00026 , H03K2005/00058 , H03L7/097 , H03L7/0997 , H01L2924/00
摘要： Adaptive clocking schemes for synchronized on-chip functional blocks are provided. The clocking schemes enable synchronous clocking which can be adapted according to changes in signal path propagation delay due temperature, process, and voltage variations, for example. In embodiments, the clocking schemes allow for the capacity utilization of a logic path to be increased.
摘要翻译：提供了同步片上功能块的自适应时钟方案。时钟方案实现了可以根据信号路径传播延迟因温度，过程和电压变化而改变的同步时钟。在实施例中，时钟方案允许增加逻辑路径的容量利用。

10. 发明申请

WO2011091073A3 DUTY CYCLE CORRECTION CIRCUIT FOR MEMORY INTERFACES IN INTEGRATED CIRCUITS 审中-公开
标题翻译：集成电路存储器接口的占空比校正电路
公开(公告)号：WO2011091073A3
公开(公告)日：2011-11-17
申请号：PCT/US2011021762
申请日：2011-01-19
申请人： ALTERA CORP , CHONG YAN , HUANG JOSEPH , NAGARAJAN PRADEEP , SUNG CHIAKANG
发明人： CHONG YAN , HUANG JOSEPH , NAGARAJAN PRADEEP , SUNG CHIAKANG
IPC分类号： G11C7/22 , G11C7/10
CPC分类号： H03K5/1565 , H03K5/151 , H03K5/1534 , H03K2005/00019
摘要： Circuits and a method for correcting duty cycle distortions in an integrated circuit (IC) are disclosed. The IC includes a splitter circuit that is coupled to receive a clock signal. The clock signal is split into two different clock signals. One of the clock signals is an inverted version of the other. A delay circuit is coupled to each of the clock signals. Each of the delay circuits generates a delayed version of the corresponding clock signal. A corrector circuit is coupled to receive both the delayed versions of the clock signals. The corrector circuit generates a clock output signal with a corrected duty cycle.
摘要翻译：公开了用于校正集成电路（IC）中的占空比失真的电路和方法。该IC包括分离器电路，其被耦合以接收时钟信号。时钟信号被分成两个不同的时钟信号。其中一个时钟信号是另一个的反转版本。延迟电路被耦合到每个时钟信号。每个延迟电路产生对应的时钟信号的延迟版本。校正器电路被耦合以接收时钟信号的延迟版本。校正器电路产生具有校正占空比的时钟输出信号。

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