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61. 发明申请

WO2006078506A2 STRUCTURE AND METHOD FOR BIASING PHASE CHANGE MEMORY ARRAY FOR RELIABLE WRITING 审中-公开
标题翻译：用于偏移相位变化记忆阵列的可靠写入的结构和方法
公开(公告)号：WO2006078506A2
公开(公告)日：2006-07-27
申请号：PCT/US2006/000776
申请日：2006-01-11
申请人： MATRIX SEMICONDUCTOR, INC. , SCHEUERLEIN, Roy, E.
发明人： SCHEUERLEIN, Roy, E.
IPC分类号： H01L29/02
CPC分类号： G11C11/21 , G11C13/0004 , G11C13/0023 , G11C13/0038 , G11C13/0069 , G11C2013/009 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L27/2481
摘要： A memory array having memory cells comprising a diode and a phase change material is reliably programmed by maintaining all unselected memory cells in a reverse biased state. Thus leakage is low and assurance is high that no unselected memory cells are disturbed. In order to avoid disturbing unselected memory cells during sequential writing, previously selected word and bit lines are brought to their unselected voltages before new bit lines and word lines are selected. A modified current mirror structure controls state switching of the phase change material.
摘要翻译：具有包括二极管和相变材料的存储单元的存储器阵列通过将所有未选择的存储单元维持在反向偏置状态来可靠地编程。因此，泄漏低，并且确保没有未选择的存储器单元受到干扰。为了在顺序写入期间避免干扰未选择的存储单元，在选择新的位线和字线之前，先前选择的字线和位线被带到其未选择的电压。改进的电流镜结构控制相变材料的状态切换。

62. 发明申请

WO2006078505A2 A NON-VOLATILE MEMORY CELL COMPRISING A DIELECTRIC LAYER AND A PHASE CHANGE MATERIAL IN SERIES 审中-公开
标题翻译：包含电介质层和相变材料的非易失性存储元件系列
公开(公告)号：WO2006078505A2
公开(公告)日：2006-07-27
申请号：PCT/US2006/000774
申请日：2006-01-11
申请人： MATRIX SEMICONDUCTOR, INC. , SCHEUERLEIN, Roy E. , HERNER, S. Brad
发明人： HERNER, S. Brad
IPC分类号： H01L21/336
CPC分类号： G11C5/02 , G11C11/39 , G11C13/00 , G11C13/0004 , G11C13/0069 , G11C17/16 , G11C2013/008 , G11C2213/71 , G11C2213/72 , G11C2213/77 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/126 , H01L45/144
摘要： The invention provides for a nonvolatile memory cell comprising a dielectric material in series with a phase change material, such as a chalcogenide. Phase change is achieved in chalcogenide memories by thermal means. Concentrating thermal energy in a relatively small volume assists this phase change. By applying high voltage across a dielectric layer, dielectric breakdown occurs, forming a low-resistance rupture region traversing the dielectric layer. This rupture region can serve to concentrate thermal energy in a phase-change memory cell. In a preferred embodiment, such a cell can be used in a monolithic three dimensional memory array.
摘要翻译：本发明提供了一种非易失性存储单元，其包括与相变材料（例如硫族化物）串联的电介质材料。通过热法在硫族化物记忆中实现相变。将热能集中在相对较小的体积中有助于此相变。通过在介电层上施加高电压，发生电介质击穿，形成穿过介电层的低电阻断裂区域。该破裂区域可用于将热能集中在相变存储器单元中。在优选实施例中，这样的单元可以用在单片三维存储器阵列中。

63. 发明申请

WO2013173140A3 THREE DIMENSIONAL NON-VOLATILE STORAGE WITH INTERLEAVED VERTICAL SELECT DEVICES ABOVE AND BELOW VERTICAL BIT LINES 审中-公开
标题翻译：三维非易失性存储器，具有上述垂直选择器件和垂直位线
公开(公告)号：WO2013173140A3
公开(公告)日：2014-02-27
申请号：PCT/US2013040147
申请日：2013-05-08
申请人： SANDISK TECHNOLOGIES INC , SCHEUERLEIN ROY E , SIAU CHANG
发明人： SCHEUERLEIN ROY E , SIAU CHANG
IPC分类号： H01L27/24 , G11C5/06 , G11C13/00 , H01L45/00
CPC分类号： G11C5/06 , G11C5/063 , G11C7/18 , G11C13/0023 , G11C13/003 , G11C2213/71 , H01L27/2454 , H01L27/249 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/142 , H01L45/143 , H01L45/146
摘要： A three-dimensional array of memory elements reversibly change a level of electrical conductance/resistance in response to one or more voltage differences being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Local bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. Vertically oriented select devices are used to connect the local bit lines to global bit lines. A first subset of the vertically oriented select devices are positioned above the vertically oriented bit lines and a second subset of the vertically oriented select devices (interleaved with the first subset of the vertically oriented select devices) are positioned below the vertically oriented bit lines.
摘要翻译：存储元件的三维阵列响应于在其上施加的一个或多个电压差而可逆地改变电导/电阻的水平。存储元件跨越位于半导体衬底上方不同距离的多个平面形成。所有平面的存储元件连接到的局部位线从衬底垂直定向并穿过多个平面。垂直取向的选择器件用于将本地位线连接到全局位线。垂直取向的选择装置的第一子集位于垂直取向的位线上方，并且垂直取向的选择装置的第二子集（与垂直取向的选择装置的第一子集交错）位于垂直取向的位线下方。

64. 发明申请

WO2013101499A3 LOW FORMING VOLTAGE NON-VOLATILE STORAGE DEVICE 审中-公开
标题翻译：低成型电压非挥发性存储装置
公开(公告)号：WO2013101499A3
公开(公告)日：2013-09-12
申请号：PCT/US2012069676
申请日：2012-12-14
申请人： SANDISK TECHNOLOGIES INC , LAN ZHIDA , SCHEUERLEIN ROY E , ZHANG TONG , HOU KUN , RATNAM PERUMAL
发明人： LAN ZHIDA , SCHEUERLEIN ROY E , ZHANG TONG , HOU KUN , RATNAM PERUMAL
IPC分类号： G11C13/00 , H01L27/24 , H01L45/00
CPC分类号： G11C13/0097 , G11C13/0002 , G11C13/0007 , G11C13/003 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0083 , G11C2213/32 , G11C2213/52 , G11C2213/71 , G11C2213/77 , H01L27/2454 , H01L27/249 , H01L45/08 , H01L45/1226 , H01L45/1253 , H01L45/145 , H01L45/146
摘要： A three-dimensional array of memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are provided across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. The memory elements can be set to a low resistance state and reset to a high resistance state during standard operation by biasing appropriate voltages on the word lines and bit lines. Prior to standard operation, the memory elements undergo a forming operation, during which current through the bit lines is limited. A forming voltage is applied to the memory elements during forming with a polarity such that the bit line acts as a cathode and the word line acts as an anode, with the cathode having a lower electron injection energy barrier to the switching material than the anode.
摘要翻译：存储器元件的三维阵列响应于施加在其上的电压差而可逆地改变电导水平。跨在半导体衬底上方不同距离定位的多个平面提供存储器元件。所有平面的存储器元件连接到的位线从衬底垂直取向并穿过多个平面。通过偏置字线和位线上的适当电压，存储器元件可以被设置为低电阻状态并且在标准操作期间被重置为高电阻状态。在标准操作之前，存储器元件经历成形操作，在成形操作期间，通过位线的电流受到限制。形成电压在形成期间被施加至存储元件，其极性使得位线用作阴极并且字线用作阳极，其中阴极对开关材料具有比阳极更低的电子注入能量势垒。

65. 发明申请

WO2012067738A1 MEMORY SYSTEM WITH REVERSIBLE RESISTIVITY-SWITCHING USING PULSES OF ALTERNATE POLARITY 审中-公开
标题翻译：具有可逆电阻切换的存储器系统使用备用极性脉冲
公开(公告)号：WO2012067738A1
公开(公告)日：2012-05-24
申请号：PCT/US2011/056130
申请日：2011-10-13
申请人： SANDISK 3D LLC , RABKIN, Peter , SAMACHISA, George , SCHEUERLEIN, Roy, E.
发明人： RABKIN, Peter , SAMACHISA, George , SCHEUERLEIN, Roy, E.
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C2013/0073 , G11C2013/0078 , G11C2013/009 , G11C2013/0092
摘要： A memory system includes a plurality of non-volatile storage elements that each comprise a diode (or other steering device) in series with reversible resistance-switching material. One or more circuits in the memory system program the non-volatile storage elements by changing the reversible resistance-switching material of one or more non-volatile storage elements to a first resistance state. The memory system can also change the reversible resistance-switching material of one or more of the non-volatile storage elements from the first resistance state to a second resistance state by applying one or more pairs of opposite polarity voltage conditions (e.g., pulses) to the respective diodes (or other steering devices) such that current flows in the diodes (or other steering devices) without operating the diodes (or other steering devices) in breakdown condition.
摘要翻译：存储器系统包括多个非易失性存储元件，每个非易失性存储元件包括与可逆电阻切换材料串联的二极管（或其他转向装置）。存储器系统中的一个或多个电路通过将一个或多个非易失性存储元件的可逆电阻切换材料改变为第一电阻状态而对非易失性存储元件进行编程。存储系统还可以将一个或多个非易失性存储元件的可逆电阻切换材料从第一电阻状态改变到第二电阻状态，通过将一对或多对相反极性的电压条件（例如，脉冲）施加到相应的二极管（或其他转向装置）使得电流在二极管（或其他转向装置）中流动，而不会在击穿情况下操作二极管（或其他转向装置）。

66. 发明申请

WO2011056534A2 METHODS OF FORMING PILLARS FOR MEMORY CELLS USING SEQUENTIAL SIDEWALL PATTERNING 审中-公开
标题翻译：使用顺序侧壁图案形成记忆细胞的柱子的方法
公开(公告)号：WO2011056534A2
公开(公告)日：2011-05-12
申请号：PCT/US2010054027
申请日：2010-10-26
申请人： SANDISK 3D LLC , SCHEUERLEIN ROY E , PETTI CHRISTOPHER J , TANAKA YOICHIRO
发明人： SCHEUERLEIN ROY E , PETTI CHRISTOPHER J , TANAKA YOICHIRO
IPC分类号： H01L21/033
CPC分类号： G11C5/06 , H01L21/0337 , H01L27/0207 , H01L27/0688 , H01L27/101 , H01L27/2481 , H01L2924/0002 , Y10S257/909 , H01L2924/00
摘要： The present invention provides apparatus, methods, and systems for fabricating memory structures methods of forming pillars for memory cells using sequential sidewall patterning. The invention includes forming first features from a first template layer disposed above a memory layer stack; forming first sidewall spacers adjacent the first features; forming second features that extend in a first direction in a mask layer by using the first sidewall spacers as a hardmask; depositing a second template layer on the mask layer; forming third features from the second template layer; forming second sidewall spacers adjacent the third features; and forming fourth features that extend in a second direction in the mask layer by using the second sidewall spacers as a hardmask. Numerous additional aspects are disclosed.
摘要翻译：本发明提供了用于制造存储器结构的设备，方法和系统，其使用顺序侧壁图案化来形成存储器单元的柱。本发明包括从布置在存储层堆叠之上的第一模板层形成第一特征; 形成邻近所述第一部件的第一侧壁间隔物; 通过使用所述第一侧壁间隔物作为硬掩模形成在掩模层中沿第一方向延伸的第二特征; 在掩模层上沉积第二模板层; 从第二模板层形成第三特征; 形成与第三特征相邻的第二侧壁间隔物; 以及通过使用第二侧壁间隔物作为硬掩模，形成在掩模层中沿第二方向延伸的第四特征。披露了许多其他方面。

67. 发明申请

WO2010123657A1 WRITE METHOD OF A CROSS POINT NON-VOLATILE MEMORY CELL WITH DIODE 审中-公开
标题翻译：具有二极管的交叉点非易失性存储单元的写入方法
公开(公告)号：WO2010123657A1
公开(公告)日：2010-10-28
申请号：PCT/US2010/029186
申请日：2010-03-30
申请人： SANDISK 3D LLC , SCHEUERLEIN, Roy, E.
发明人： SCHEUERLEIN, Roy, E.
IPC分类号： G11C13/00
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/0078 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72
摘要： A memory system includes an X line, a first Y line, a second Y line, a semiconductor region of a first type running along the X line, first switching material and a first semiconductor region of a second type between the first Y line and the semiconductor region of the first type, second switching material and a second semiconductor region of the second type between the second Y line and the semiconductor region of the first type, and control circuitry. The control circuitry is in communication with the X line, the first Y line and the second Y line. The control circuitry changes the programming state of the first switching material to a first state by causing a first current to flow from the second Y line to the first Y line through the first switching material, the second switching material, the semiconductor region of the first type, the first semiconductor region of the second type and the second semiconductor region of the second type.
摘要翻译：存储系统包括X线，第一Y线，第二Y线，沿着X线延伸的第一类型的半导体区域，第一开关材料和第一Y线与第一Y线之间的第二类型的第一半导体区域第一类型的半导体区域，第二开关材料和第二类型的第二类型的第二半导体区域在第二Y线和第一类型的半导体区域之间，以及控制电路。控制电路与X线，第一Y线和第二Y线通信。控制电路通过使第一电流从第二Y线流过第一Y线，通过第一开关材料，第二开关材料，第一开关材料的半导体区域，将第一开关材料的编程状态改变到第一状态第二类型的第一半导体区域和第二类型的第二半导体区域。

68. 发明申请

WO2009126874A3 NON-VOLATILE MULTI-LEVEL RE-WRITABLE MEMORY CELL INCORPORATING A DIODE IN SERIES WITH MULTIPLE RESISTORS AND METHOD FOR WRITING SAME 审中-公开
标题翻译：具有多个电阻器的系列中的二极管非易失性多层可重写存储单元及其写入方法
公开(公告)号：WO2009126874A3
公开(公告)日：2010-01-21
申请号：PCT/US2009040187
申请日：2009-04-10
申请人： SANDISK 3D LLC , SCHEUERLEIN ROY E
发明人： SCHEUERLEIN ROY E
IPC分类号： G11C16/04 , G11C11/36 , G11C16/00
CPC分类号： G11C11/5685 , G11C11/5678 , G11C13/0004 , G11C13/0007 , G11C13/0069 , G11C17/16 , G11C2013/009 , G11C2213/15 , G11C2213/19 , G11C2213/31 , G11C2213/32 , G11C2213/33 , G11C2213/34 , G11C2213/72 , Y10T29/49002
摘要： A very dense cross-point memory array of multi-level read/write two-terminal memory cells, and methods for its programming, are described. Multiple states are achieved using two or more films that each have bi-stable resistivity states, rather than "tuning" the resistance of a single resistive element. An exemplary memory cell includes a vertical pillar diode in series with two different bi-stable resistance films. Each bi-stable resistance film has both a high resistance and low resistance state that can be switched with appropriate application of a suitable bias voltage and current. Such a cross-point array is adaptable for two-dimensional rewritable memory arrays, and also particularly well-suited for three-dimensional rewritable (3D R/W) memory arrays.
摘要翻译：描述了多级读/写两端存储单元的非常密集的交叉点存储器阵列及其编程方法。使用两个或更多个具有双稳态电阻率状态的膜而不是“调谐”单个电阻元件的电阻来实现多个状态。示例性存储单元包括与两个不同的双稳电阻膜串联的立柱二极管。每个双稳态电阻膜具有高电阻和低电阻状态，可以适当地施加适当的偏置电压和电流来切换。这种交叉点阵列适用于二维可重写存储器阵列，并且还特别适用于三维可重写（3D R / W）存储器阵列。

69. 发明申请

WO2010005864A1 MEMORY CELL WITH MULTIPLE SERIES PASSIVE ELEMENT FOR THREE-DIMENSIONAL ARRAYS 审中-公开
标题翻译：具有多个系列的存储器单元，用于三维阵列的被动元件
公开(公告)号：WO2010005864A1
公开(公告)日：2010-01-14
申请号：PCT/US2009/049513
申请日：2009-07-02
申请人： SANDISK 3D LLC , SCHEUERLEIN, Roy, E.
发明人： SCHEUERLEIN, Roy, E.
IPC分类号： G11C13/00 , H01L27/24
CPC分类号： G11C13/003 , B82Y10/00 , G11C13/025 , G11C2213/16 , G11C2213/35 , G11C2213/72 , G11C2213/74 , H01L27/2409 , H01L27/2418 , H01L45/04 , H01L45/1233 , H01L45/149
摘要： A nonvolatile memory cell including at least two two-terminal non-linear steering elements arranged in series, and a resistivity switching storage element arranged in series with the at least two two-terminal non-linear steering elements. A memory array, comprising a plurality of the nonvolatile memory cells is also described. A method of forming a nonvolatile memory cell is also described.
摘要翻译：包括串联布置的至少两个两端非线性转向元件的非易失性存储单元和与所述至少两个两端非线性转向元件串联设置的电阻率切换存储元件。还描述了包括多个非易失性存储器单元的存储器阵列。还描述了形成非易失性存储单元的方法。

70. 发明申请

WO2010002683A2 METHOD FOR FABRICATING HIGH DENSITY PILLAR STRUCTURES BY DOUBLE PATTERNING USING POSITIVE PHOTORESIST 审中-公开
标题翻译：利用正光子法双重构图高密度立柱结构的方法
公开(公告)号：WO2010002683A2
公开(公告)日：2010-01-07
申请号：PCT/US2009048584
申请日：2009-06-25
申请人： SANDISK 3D LLC , SCHEUERLEIN ROY E , RADIGAN STEVEN
发明人： SCHEUERLEIN ROY E , RADIGAN STEVEN
IPC分类号： H01L27/10 , H01L21/033 , H01L27/102 , H01L27/24
CPC分类号： H01L27/1021 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/14 , H01L45/146 , H01L45/147 , H01L45/149 , H01L45/16
摘要： A method of making a semiconductor device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer into a first photoresist pattern, wherein the first photoresist pattern comprises a plurality of spaced apart first photoresist features located over the underlying layer, and etching the underlying layer using the first photoresist pattern as a mask to form a plurality of first spaced apart features. The method further includes removing the first photoresist pattern, forming a second photoresist layer over the plurality of first spaced apart features, and patterning the second photoresist layer into a second photoresist pattern, wherein the second photoresist pattern comprises a plurality of second photoresist features covering edge portions of the plurality of first spaced apart features. The method also includes etching exposed portions of the plurality of first spaced apart features using the second photoresist pattern as a mask, such that a plurality of spaced apart edge portions of the plurality of first spaced apart features remain, and removing the second photoresist pattern.
摘要翻译：制造半导体器件的方法包括在下层上形成第一光刻胶层，将第一光刻胶层图案化成第一光刻胶图案，其中第一光刻胶图案包括位于下层之上的多个间隔开的第一光刻胶部件，以及使用所述第一光致抗蚀剂图案作为掩模来蚀刻所述下层，以形成多个第一间隔开的特征。该方法还包括去除第一光致抗蚀剂图案，在多个第一间隔开的特征上形成第二光致抗蚀剂层，并将第二光致抗蚀剂层图案化成第二光致抗蚀剂图案，其中第二光致抗蚀剂图案包括多个第二光致抗蚀剂特征，多个第一间隔开的特征的部分。该方法还包括使用第二光致抗蚀剂图案作为掩模来蚀刻多个第一间隔开的特征的暴露部分，使得多个第一间隔开的特征的多个间隔开的边缘部分保留，并且去除第二光致抗蚀剂图案。

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