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51. 发明申请

WO2017172214A1 TECHNOLOGIES FOR REGION-BIASED CACHE MANAGEMENT 审中-公开
标题翻译：区域偏置缓存管理技术
公开(公告)号：WO2017172214A1
公开(公告)日：2017-10-05
申请号：PCT/US2017/020225
申请日：2017-03-01
申请人： INTEL CORPORATION
发明人： SUKHOMLINOV, Vadim , DOSHI, Kshitij A. , VENKATESAN, Namakkal N.
IPC分类号： G06F12/0802
CPC分类号： G06F12/0891 , G06F12/0811 , G06F12/0893 , G06F2212/604 , G06F2212/70
摘要： Technologies for region-based cache management includes network computing device. The network computing device is configured to divide an allocated portion main memory of the network computing device into a plurality of memory regions, each memory region having a cache block that includes a plurality of cache lines of a cache memory of the processor. The network computing device is further configured to determine whether a cache line selected for eviction from the cache memory corresponds to one of the plurality of memory regions and, if so, retrieve a dynamically adjustable bias value (i.e., a fractional probability) associated with the corresponding memory region. Additionally, the network computing device is configured to generate a bias comparator value for the corresponding memory region, compare the bias value of the corresponding memory region and the bias comparator value generated for the corresponding memory region, and determine whether to evict the cache line based on the comparison. Other embodiments are described herein.
摘要翻译：用于基于区域的高速缓存管理的技术包括网络计算设备。网络计算设备被配置为将网络计算设备的分配的部分主存储器划分为多个存储区域，每个存储区域具有包括处理器的高速缓存存储器的多个高速缓存行的高速缓存块。所述网络计算设备还被配置为确定从所述高速缓冲存储器中选择用于驱逐的高速缓存行是否对应于所述多个存储区域中的一个存储区域，并且如果是，则检索与所述多个存储区域相关联的动态可调整偏差值（即，分数概率）相应的存储区域。另外，网络计算设备被配置成为对应的存储器区域生成偏置比较器值，比较对应的存储器区域的偏置值和针对对应的存储器区域生成的偏置比较器值，并且确定是否驱逐高速缓存线在比较。这里描述了其他实施例。

52. 发明申请

WO2017151280A1 WRITE-ALLOCATION FOR A CACHE BASED ON EXECUTE PERMISSIONS 审中-公开
标题翻译：基于执行权限的高速缓存写分配
公开(公告)号：WO2017151280A1
公开(公告)日：2017-09-08
申请号：PCT/US2017/016971
申请日：2017-02-08
申请人： QUALCOMM INCORPORATED
发明人： SARTORIUS, Thomas Andrew , DIEFFENDERFER, James Norris , MORROW, Michael William , BRIDGES, Jeffrey Todd , MCILVAINE, Michael Scott , SMITH, Rodney Wayne , DOCKSER, Kenneth Alan , SPEIER, Thomas Philip
IPC分类号： G06F12/0811 , G06F12/0888 , G06F12/1027 , G06F12/126 , G06F12/0831 , G06F12/0871
CPC分类号： G06F12/123 , G06F12/0811 , G06F12/0831 , G06F12/0871 , G06F12/0888 , G06F12/0891 , G06F12/0895 , G06F12/0897 , G06F12/1009 , G06F12/1027 , G06F12/12 , G06F12/126 , G06F2212/604 , G06F2212/6046 , G06F2212/621 , G06F2212/684
摘要： Systems and methods for managing access to a cache relate to determining one or more execute permissions associated with a write-address of a write-request to the cache. The cache may be a unified cache for storing data as well as instructions. If there is a write-miss in the cache for the write-request, a cache controller may determine whether to implement a write-allocate policy or a write-no-allocate policy for servicing the write-miss, based on the one or more execute permissions. The one or more execute permissions can relate to a privilege level associated with the write-address. Execute permissions of a producing agent which generated the write-request and an execute permission of a consuming agent which can execute from the write-address may be based on the privilege levels of the producing agent and the consuming agent, respectively.
摘要翻译：用于管理对高速缓存的访问的系统和方法涉及确定与对高速缓存的写请求的写地址相关联的一个或多个执行许可。缓存可以是用于存储数据以及指令的统一缓存。如果在写入请求的高速缓存中存在写入未命中，则高速缓存控制器可以基于一个或多个写入请求来确定是否实现用于写入未命中的写入分配策略或写入不分配策略执行权限。该一个或多个执行权限可以涉及与写地址相关联的特权级别。生成写入请求的生产代理的执行许可和可以从写入地址执行的消费代理的执行许可可以分别基于生产代理和消费代理的特权等级。

53. 发明申请

WO2017048657A1 PREFETCHING ASSOCIATED WITH PREDICATED LOAD INSTRUCTIONS 审中-公开
标题翻译：与预测负荷指令相关的预备
公开(公告)号：WO2017048657A1
公开(公告)日：2017-03-23
申请号：PCT/US2016/051418
申请日：2016-09-13
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： BURGER, Douglas C. , SMITH, Aaron L.
IPC分类号： G06F9/38 , G06F12/0862 , G06F9/30
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Technology related to prefetching data associated with predicated loads of programs in block-based processor architectures is disclosed. In one example of the disclosed technology, a processor includes a block-based processor core for executing an instruction block comprising a plurality of instructions. The block-based processor core includes decode logic and prefetch logic. The decode logic is configured to detect a predicated load instruction of the instruction block. The prefetch logic is configured to calculate a target address of the predicated load instruction and issue a prefetch request to a memory hierarchy of the processor for data at the calculated target address.
摘要翻译：公开了与在基于块的处理器架构中预测与程序负载相关联的数据相关的技术。在所公开的技术的一个示例中，处理器包括用于执行包括多个指令的指令块的基于块的处理器核心。基于块的处理器核心包括解码逻辑和预取逻辑。解码逻辑被配置为检测指令块的预测加载指令。预取逻辑被配置为计算预测加载指令的目标地址，并且在计算出的目标地址的数据上向处理器的存储器层次结构发出预取请求。

54. 发明申请

WO2017048655A1 DENSE READ ENCODING FOR DATAFLOW ISA 审中-公开
标题翻译： DENSE读取编码数据流ISA
公开(公告)号：WO2017048655A1
公开(公告)日：2017-03-23
申请号：PCT/US2016/051416
申请日：2016-09-13
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： BURGER, Douglas C. , SMITH, Aaron L.
IPC分类号： G06F12/0806 , G06F9/38
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Apparatus and methods are disclosed for controlling execution of memory access instructions in a block-based processor architecture using an instruction decoder that decodes instructions having variable numbers of target operands. In one example of the disclosed technology, a block-based processor core includes an instruction decoder configured to decode target operands for an instruction in an instruction block, the instruction being encoded to allow for a variable number of target operands and a control unit configured to send data for at least one of the decoded target operands for an operation performed by the at least one of the cores. In some examples, the instruction indicates target instructions with a vector encoding. In other examples, a variable length format allows for the indication of one or more targets.
摘要翻译：公开了用于在基于块的处理器架构中使用解码具有可变数目的目标操作数的指令的指令解码器来控制存储器访问指令的执行的装置和方法。在所公开的技术的一个示例中，基于块的处理器核心包括指令解码器，其被配置为对指令块中的指令进行解码目标操作数，所述指令被编码以允许可变数量的目标操作数，以及控制单元，为所述至少一个核执行的操作发送用于所述解码的目标操作数中的至少一个的数据。在一些示例中，该指令指示具有向量编码的目标指令。在其他示例中，可变长度格式允许指示一个或多个目标。

55. 发明申请

WO2017048650A1 DEBUG SUPPORT FOR BLOCK-BASED PROCESSOR 审中-公开
标题翻译：用于基于块的处理器的调试支持
公开(公告)号：WO2017048650A1
公开(公告)日：2017-03-23
申请号：PCT/US2016/051411
申请日：2016-09-13
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： BURGER, Douglas C. , SMITH, Aaron L.
IPC分类号： G06F9/38 , G06F11/00 , G06F11/36 , G06F9/30
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Systems and methods are disclosed for supporting debugging of programs in block-based processor architectures. In one example of the disclosed technology, a processor includes a block-based processor core for executing an instruction block comprising an instruction header and a plurality of instructions. The block-based processor core includes execution control logic and core state access logic. The execution control logic can be configured to schedule respective instructions of the plurality of instructions for execution in a dynamic order during a default execution mode and to schedule the respective instructions for execution in a static order during a debug mode. The core state access logic can be configured to read intermediate states of the block-based processor core and to provide the intermediate states outside of the block-based processor core during the debug mode.
摘要翻译：公开了用于支持基于块的处理器架构中的程序的调试的系统和方法。在所公开的技术的一个示例中，处理器包括用于执行包括指令标题和多个指令的指令块的基于块的处理器核心。基于块的处理器核心包括执行控制逻辑和核心状态访问逻辑。执行控制逻辑可以被配置为在默认执行模式期间以动态顺序调度多个指令的相应指令以便以动态顺序执行，并且在调试模式期间调度各个指令以静态顺序执行。核心状态访问逻辑可以被配置为读取基于块的处理器核的中间状态，并且在调试模式期间将中间状态提供到基于块的处理器核之外。

56. 发明申请

WO2017048649A1 REGISTER READ/WRITE ORDERING 审中-公开
标题翻译：注册阅读/写命令
公开(公告)号：WO2017048649A1
公开(公告)日：2017-03-23
申请号：PCT/US2016/051410
申请日：2016-09-13
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： BURGER, Douglas C. , SMITH, Aaron L.
IPC分类号： G06F12/0806 , G06F9/38 , G06F9/30
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Apparatus and methods are disclosed for controlling execution of register access instructions in a block-based processor architecture using a hardware structure that indicates a relative ordering of register access instruction in an instruction block. In one example of the disclosed technology, a method of operating a processor includes selecting a register access instruction of the plurality of instructions to execute based at least in part on dependencies encoded within a previous block of instructions and on stored data indicating which of the register write instructions have executed for the previous block, and executing the selected instruction. In some examples, one or more of a write mask, a read mask, a register write vector register, or a counter are used to determine register read/write dependences. Based on the encoded dependencies and the masked write vector, the next instruction block can issue when its register dependencies are available.
摘要翻译：公开的装置和方法用于使用指示指令块中的寄存器访问指令的相对排序的硬件结构来控制基于块的处理器架构中的寄存器访问指令的执行。在所公开的技术的一个实例中，一种操作处理器的方法包括：至少部分地基于在先前的指令块内编码的依存关系以及存储的数据来选择多个指令的寄存器访问指令，以指示寄存器对上一个程序段执行写入指令，并执行所选择的指令。在一些示例中，使用写掩码，读掩码，寄存器写向量寄存器或计数器中的一个或多个来确定寄存器读/写依赖性。基于编码的依赖性和掩码写入向量，下一个指令块可以在其寄存器依赖性可用时发出。

57. 发明申请

WO2017048648A1 SEGMENTED INSTRUCTION BLOCK 审中-公开
标题翻译：分段指令块
公开(公告)号：WO2017048648A1
公开(公告)日：2017-03-23
申请号：PCT/US2016/051409
申请日：2016-09-13
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： BURGER, Douglas C. , SMITH, Aaron L.
IPC分类号： G06F9/30 , G06F9/38 , G06F9/46
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Systems and methods are disclosed for fetching and decoding instructions in block-based processor architectures. In one example of the disclosed technology, a block-based processor core can be used for executing an instruction block. The instruction block can include an instruction header and one or more instructions. The block-based processor core can include header decode logic and fetch logic that are in communication with each other. The header decode logic can be configured to decode the instruction block header to determine starting positions of a plurality of sub-blocks within the instruction block. The fetch logic can be configured to initiate parallel fetch and decode operations for the plurality of sub-blocks.
摘要翻译：公开了用于在基于块的处理器架构中提取和解码指令的系统和方法。在所公开的技术的一个示例中，可以使用基于块的处理器核来执行指令块。指令块可以包括指令头和一个或多个指令。基于块的处理器核心可以包括彼此通信的报头解码逻辑和提取逻辑。报头解码逻辑可以被配置为解码指令块报头以确定指令块内的多个子块的开始位置。提取逻辑可以被配置为启动用于多个子块的并行获取和解码操作。

58. 发明申请

WO2017048605A1 CONFIGURING MODES OF PROCESSOR OPERATION 审中-公开
标题翻译：处理器操作的配置模式
公开(公告)号：WO2017048605A1
公开(公告)日：2017-03-23
申请号：PCT/US2016/051207
申请日：2016-09-12
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： BURGER, Douglas C. , SMITH, Aaron L.
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Apparatus and methods are disclosed for configuring, operating, and compiling code for, block-based processor architectures. In one example of the disclosed technology, a block-based processor includes processor cores configured to decode an instruction block header for a block-based processor instruction block including one or more fields and configure at least one of the cores to execute instructions in the instruction block according to a mode of operation specified by at least one of the fields, the modes including one or more of the following: core fusion operation, vector mode operation, memory dependence prediction operation, and/or deterministic order of execution.
摘要翻译：公开了用于配置，操作和编译用于基于块的处理器架构的代码的装置和方法。在所公开的技术的一个示例中，基于块的处理器包括被配置为对包括一个或多个字段的基于块的处理器指令块的指令块头进行解码并且配置至少一个核来执行指令中的指令的处理器核根据由至少一个字段指定的操作模式，所述模式包括以下中的一个或多个：核心融合操作，向量模式操作，存储器依赖性预测操作和/或确定性执行顺序。

59. 发明申请

WO2017019216A1 ADDRESS CACHING IN SWITCHES 审中-公开
标题翻译：地址在开关中缓存
公开(公告)号：WO2017019216A1
公开(公告)日：2017-02-02
申请号：PCT/US2016/039333
申请日：2016-06-24
申请人： GOOGLE INC.
发明人： SEREBRIN, Benjamin C.
IPC分类号： G06F12/1027 , G06F12/1081 , G06F12/109 , G06F12/14 , G06F13/38 , G06F13/40 , G06F12/1036 , G06F12/0813
CPC分类号： G06F13/4022 , G06F3/0611 , G06F3/0656 , G06F3/067 , G06F12/0813 , G06F12/0882 , G06F12/10 , G06F12/1036 , G06F12/1045 , G06F12/1081 , G06F12/109 , G06F12/1425 , G06F2212/1016 , G06F2212/1024 , G06F2212/1044 , G06F2212/1048 , G06F2212/152 , G06F2212/154 , G06F2212/264 , G06F2212/604 , G06F2212/608 , G06F2212/65 , G06F2212/657 , G06F2212/68 , G06F2212/682 , G06F2212/683
摘要： Methods, systems, and apparatus, including computer programs encoded on computer storage media, for storing an address in a memory of a switch. One of the systems includes a switch that receives packets from and delivers packets to devices connected to a bus without any components on the bus between the switch and each of the devices, a memory integrated into the switch to store a mapping of virtual addresses to physical addresses, and a storage medium integrated into the switch storing instructions executable by the switch to cause the switch to perform operations including receiving a response to an address translation request for a device connected to the switch by the bus, the response including a mapping of a virtual address to a physical address, and storing, in the memory, the mapping of the virtual address to the physical address in response to receiving the response.
摘要翻译：方法，系统和装置，包括在计算机存储介质上编码的计算机程序，用于将地址存储在交换机的存储器中。系统之一包括从交换机和每个设备之间的总线上没有任何组件的数据包接收数据包并将数据包传送到连接到总线的设备的交换机，集成到交换机中的存储器，以将虚拟地址映射到物理地址和集成到交换机中的存储介质，其存储可由交换机执行的指令，以使交换机执行操作，包括接收对由总线连接到交换机的设备的地址转换请求的响应，响应包括虚拟地址到物理地址，并且响应于接收到响应而在存储器中存储虚拟地址到物理地址的映射。

60. 发明申请

WO2016191569A1 MEMORY SYSTEM ARCHITECTURE 审中-公开
标题翻译：存储系统架构
公开(公告)号：WO2016191569A1
公开(公告)日：2016-12-01
申请号：PCT/US2016/034360
申请日：2016-05-26
申请人： GOOGLE INC.
发明人： KNIES, Allan D. , SHIU, Shinye , CHANG, Chih-Chung , MALYUGIN, Vyacheslav Vladimirovich , RAO, Santhosh
IPC分类号： G06F12/0888 , G06F12/0893 , G06F12/084 , G06F12/127
CPC分类号： G06F12/0893 , G06F12/084 , G06F12/0888 , G06F12/0891 , G06F12/1045 , G06F12/127 , G06F2212/1016 , G06F2212/604 , G06F2212/6046 , G06F2212/68
摘要： Provided are methods, systems, and apparatus for managing and controlling memory caches, in particular, system level caches outside of those closest to the CPU. The processes and representative hardware structures that implement the processes are designed to allow for detailed control over the behavior of such system level caches. Caching policies are developed based on policy identifiers, where a policy identifier corresponds to a collection of parameters that control the behavior of a set of cache management structures. For a given cache, one policy identifier is stored in each line of the cache.
摘要翻译：提供了用于管理和控制存储器高速缓存的方法，系统和装置，特别是在最接近CPU的那些之外的系统级高速缓存。旨在实现这些过程的过程和代表性的硬件结构被设计为允许对这种系统级高速缓存的行为进行详细的控制。基于策略标识符开发缓存策略，其中策略标识符对应于控制一组高速缓存管理结构的行为的参数集合。对于给定的缓存，一个策略标识符存储在高速缓存的每一行中。

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