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41. 发明申请

WO01088988A1 COULOMB BARRIER STORAGE DEVICE, COMPRISING A PLURALITY OF ELECTRON TRAPS, AND METHOD FOR MAKING SAME 审中-公开
标题翻译：包含多个电子束的COULOMB BARRIER存储器件及其制造方法
公开(公告)号：WO01088988A1
公开(公告)日：2001-11-22
申请号：PCT/FR2001/001446
申请日：2001-05-14
IPC分类号： G11C11/56 , H01L29/788 , H01L27/115 , H01L21/336 , H01L21/8247
CPC分类号： B82Y10/00 , G11C11/56 , G11C11/5621 , H01L29/7887 , H01L29/7888
摘要： The invention concerns a Coulomb barrier storage device comprising a single continuous floating gate (22) associated with a plurality of barrier islands and a control gate (38, 42), the gates being separated from said plurality of barrier islands (34), and each barrier island comprising an alternating pile (24) of a plurality of conductive (24b) and dielectric layers (24a). The invention is useful for making random-access storage units.
摘要翻译：本发明涉及一种库仑势垒存储装置，其包括与多个势垒岛相关联的单个连续浮动栅极（22）和控制栅极（38,42），所述栅极与所述多个势垒岛（34）分离，并且每个阻挡岛包括多个导电（24b）和电介质层（24a）的交替堆（24）。本发明对于制造随机存取存储单元是有用的。

42. 发明申请

WO01069607A2 MEMORY CELL, METHOD OF FORMATION, AND OPERATION 审中-公开
标题翻译：记忆细胞，形成和操作方法
公开(公告)号：WO01069607A2
公开(公告)日：2001-09-20
申请号：PCT/US2001/006842
申请日：2001-03-02
IPC分类号： H01L21/8247 , G11C11/56 , G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： B82Y10/00 , G11C11/56 , G11C11/5671 , G11C16/0416 , G11C2216/08 , H01L29/7887 , H01L29/7888
摘要： A memory cell (101), its method of formation, and operation are disclosed. In accordance with one embodiment, the memory cell (101) comprises a first and second current carrying electrode (12), a control electrode (19), and doped discontinuous storage elements (17). In accordance with an alternative embodiment, memory cell programming is accomplished by removing or adding an average of approximately at least a first charge (30, 62, 64), which can be electron(s) or hole(s) from each of the doped discontinuous storage elements (17).
摘要翻译：公开了一种存储单元（101），其形成方法和操作。根据一个实施例，存储单元（101）包括第一和第二载流电极（12），控制电极（19）和掺杂的非连续存储元件（17）。根据替代实施例，通过去除或添加大约至少第一电荷（30,62,64）的平均值来实现存储器单元编程，所述第一电荷可以是来自掺杂的每个的电子或空穴不连续存储元件（17）。

43. 发明申请

WO01050228A2 LOW LATENCY MULTI-LEVEL COMMUNICATION INTERFACE 审中-公开
标题翻译：低延迟多层通信接口
公开(公告)号：WO01050228A2
公开(公告)日：2001-07-12
申请号：PCT/US2001/000481
申请日：2001-01-05
IPC分类号： H04L25/02 , G06F12/00 , G06F13/16 , G11C7/10 , G11C7/22 , G11C11/56 , H04L25/03 , H04L25/49 , G06F
CPC分类号： G11C7/1057 , G11C5/063 , G11C7/10 , G11C7/1048 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C7/1072 , G11C7/1078 , G11C7/1087 , G11C7/1096 , G11C7/22 , G11C8/06 , G11C11/56 , G11C27/02 , G11C2207/108
摘要： A memory system uses multiple pulse amplitude modulation (multi-PAM) output drivers and receivers to send and receive multi-PAM signals. A multi-PAM signal has more than two voltage levels, with each data interval now transmitting a "symbol" at one of the valid voltage levels. In one embodiment, a symbol represents two or more bits. The multi-PAM output driver drives an output symbol onto a signal line. The output symbol represents at least two bits that include a most significant bit (MSB) and a least significant bit (LSB). The multi-PAM receiver receives the output symbol from the signal line and determines the MSB and the LSB.
摘要翻译：存储系统使用多个脉冲幅度调制（多PAM）输出驱动器和接收器来发送和接收多PAM信号。多PAM信号具有两个以上的电压电平，每个数据间隔现在以有效电压电平之一发送“符号”。在一个实施例中，符号表示两个或更多位。多PAM输出驱动器将输出符号驱动到信号线上。输出符号表示包括最高有效位（MSB）和最低有效位（LSB）的至少两个位。多PAM接收器从信号线接收输出符号并确定MSB和LSB。

44. 发明申请

WO00057498A1 ELECTRICALLY PROGRAMMABLE MEMORY ELEMENT WITH IMPROVED CONTACTS 审中-公开
标题翻译：具有改进联系方式的电子可编程存储元件
公开(公告)号：WO00057498A1
公开(公告)日：2000-09-28
申请号：PCT/US2000/007666
申请日：2000-03-22
IPC分类号： H01L21/8238 , G11C11/56 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/24 , H01L45/00 , H01L47/00
CPC分类号： H01L27/2436 , G11C11/56 , G11C11/5678 , G11C13/0004 , H01L27/2472 , H01L45/06 , H01L45/122 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1675
摘要： A memory element comprising a volume of phase change memory material (250); and first and second contact for supplying an electrical signal to the memory material (250), wherein the first contact comprises a conductive sidewall spacer (130A, B). Alternately, the first contact may comprise a contact layer having an edge adjacent to the memory material (250).
摘要翻译：一种存储元件，包括一定量的相变存储器材料（250）; 以及用于向所述存储器材料（250）提供电信号的第一和第二接触，其中所述第一接触包括导电侧壁间隔物（130A，B）。或者，第一接触可以包括具有与存储材料（250）相邻的边缘的接触层。

45. 发明申请

WO1997049086A1 FLASH MEMORY ADDRESS DECODER WITH NOVEL LATCH 审中-公开
标题翻译：闪存存储器地址解码器与新的锁定
公开(公告)号：WO1997049086A1
公开(公告)日：1997-12-24
申请号：PCT/US1997007456
申请日：1997-05-05
申请人： APLUS INTEGRATED CIRCUITS, INC.
发明人： APLUS INTEGRATED CIRCUITS, INC. , LEE, Peter, W. , TSAO, Hsing-Ya , HSU, Fu-Chang
IPC分类号： G11C11/34
CPC分类号： G11C16/3418 , G11C7/1006 , G11C7/18 , G11C8/00 , G11C8/08 , G11C8/14 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0416 , G11C16/0491 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/24 , G11C16/26 , G11C16/3413 , G11C16/3431 , G11C2211/5644 , H01L27/115
摘要： A flash memory (10) includes a flash transistor array (12a, 12b, 12i), a wordline decoder (14), a bitline decoder (18), a sourceline decoder (22) and a read/write controller (26). The read/write controller (26) has a voltage terminal to receive an input voltage and a data terminal configured to sense a signal on a selected bitline and to generate an internal old amplifier and configured to compare the new data signal to the old data signal and to generate a comparator signal. A voltage generator is configured to selectively apply one of a read set of voltages to program a selected cell and an erase set of voltages to erase a selected cell. In a multistate embodiment, the read/write controller further includes a step counter configured to generate a plurality of step counts. The voltage generator is coupled to the step counter and configured to generate a wordline high voltage (WLHV) signal based on the step count. The WLHV signal is delivered to a selected multistate cell by the wordline decoder to read the contents of the selected multistate cell. Each step compares the old data and the new data in order to determine which memory cells to change. Advantages of the invention include increased flexibility of programming and erasing and improved memory longevity.
摘要翻译：闪速存储器（10）包括闪存晶体管阵列（12a，12b，12i），字线解码器（14），位线解码器（18），源线解码器（22）和读/写控制器（26）。读/写控制器（26）具有用于接收输入电压的电压端子和被配置为感测选定位线上的信号并产生内部旧放大器并被配置为将新数据信号与旧数据信号进行比较的数据端并产生比较器信号。电压发生器被配置为选择性地施加读取的一组电压以编程所选择的单元和擦除电压组以擦除所选择的单元。在多状态实施例中，读/写控制器还包括配置成产生多个步数的步数计数器。电压发生器耦合到步进计数器并且被配置为基于步数产生字线高电压（WLHV）信号。 WLHV信号由字线解码器传送到选定的多状态单元，以读取所选择的多态单元的内容。每个步骤都比较旧数据和新数据，以确定要更改的存储单元。本发明的优点包括增加编程和擦除的灵活性并改善记忆寿命。

46. 发明申请

WO1994024707A1 ELECTRICALLY ERASABLE, DIRECTLY OVERWRITABLE, MULTIBIT SINGLE CELL MEMORY ELEMENTS AND ARRAYS FABRICATED THEREFROM 审中-公开
标题翻译：电气可擦除，直接过载，多个单个单元记忆元件和阵列组成的阵列
公开(公告)号：WO1994024707A1
公开(公告)日：1994-10-27
申请号：PCT/US1994003953
申请日：1994-04-11
申请人： ENERGY CONVERSION DEVICES, INC.
发明人： ENERGY CONVERSION DEVICES, INC. , OVSHINSKY, Stanford, R. , YE, Qiuyi , STAND, David, A. , CZUBATYJ, Wolodymyr
IPC分类号： H01L45/00
CPC分类号： G11C13/0004 , G11C11/56 , G11C11/5678 , G11C13/04 , G11C2213/72 , H01L27/2409 , H01L45/085 , H01L45/1233 , H01L45/144
摘要： The present invention comprises an electrically operated, directly overwritable, multibit, single-cell memory element. The memory element includes a volume of memory material (36) which defines the single cell memory element, a pair of spacedly disposed contacts (32, 34, 38, 40) for supply electrical input signals to set the memory material to a selected resistance value within a dynamic range, a filamentary portion controlling means disposed between the volume of memory material and at least one of the spacedly disposed contacts. The controlling means defining the size and the position of the filamentary portion during electrical formation of the memory element and limiting the size and confining the location of the filamentary portion during use of the memory element, thereby proving for a high current density within the filamentary portion of the single cell memory element upon input of a very low total current electrical signal to the spacedly disposed contacts.
摘要翻译：本发明包括电操作的直接覆盖的多位单个单元存储元件。存储元件包括限定单个单元存储器元件的存储器材料（36）的体积，一对间隔开的设置的触点（32,34,38,40），用于提供电输入信号，以将存储器材料设置为所选择的电阻值在动态范围内，设置在所述存储器体积和所述间隔布置的触点中的至少一个之间的丝状部分控制装置。控制装置在存储元件的电气形成期间限定丝状部分的尺寸和位置，并限制尺寸并限制使用存储元件期间丝状部分的位置，从而证明丝状部分内的高电流密度当将非常低的总电流电信号输入到间隔布置的触点时，单个单元存储器元件。

47. 发明申请

WO2018012740A1 터너리 내용 주소화 메모리의 저장 셀 및 이를 포함하는 터너리 내용 주소화 메모리 审中-公开
标题翻译：三元内容可寻址存储器的存储单元和三元内容可寻址存储器
公开(公告)号：WO2018012740A1
公开(公告)日：2018-01-18
申请号：PCT/KR2017/005874
申请日：2017-06-07
申请人： 경희대학교 산학협력단
发明人： 홍상훈 , 김성원 , 도현진 , 박종휘
IPC分类号： G11C15/00 , G11C11/56 , G11C15/04
CPC分类号： G11C11/56 , G11C15/00 , G11C15/04
摘要： 터너리 내용 주소화 메모리의 저장 셀은 제1 저장부, 제2 저장부 및 비교부를 포함한다. 상기 제1 저장부는 제1 데이터를 저장한다. 상기 제2 저장부는 제2 데이터를 저장한다. 상기 비교부는 상기 제1 저장부 및 상기 제2 저장부의 출력 단자에 연결되며, 입력 매칭 신호를 수신하고, 수신한 상기 입력 매칭 신호를 출력하거나 차단한다. 상기 비교부는 제1 비교 스위칭 소자 및 상기 제1 비교 스위칭 소자와 직렬로 연결되는 비교 인버터를 포함한다.
摘要翻译：三元内容可寻址存储器的存储单元包括第一存储单元，第二存储单元和比较单元。第一存储单元存储第一数据。第二存储单元存储第二数据。比较单元连接到第一存储单元和第二存储单元的输出端，接收输入匹配信号，并输出或截取接收到的匹配信号。比较部分包括与第一比较开关元件串联连接的第一比较开关元件和比较逆变器。

48. 发明申请

WO2017184853A1 METHODS FOR ENHANCED STATE RETENTION WITHIN A RESISTIVE CHANGE CELL 审中-公开
标题翻译：提高电阻变化细胞内状态保留的方法
公开(公告)号：WO2017184853A1
公开(公告)日：2017-10-26
申请号：PCT/US2017/028606
申请日：2017-04-20
申请人： NANTERO, INC.
发明人： VIVIANI, Darlene
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C11/56 , G11C13/0002 , G11C13/0004 , G11C13/004 , G11C13/025 , G11C29/028 , G11C29/50008 , G11C2013/009 , G11C2013/0092 , G11C2213/19 , G11C2213/35 , G11C2213/79 , H01L51/0048 , H01L51/0575
摘要： A method for improving the stability of a resistive change cell is disclosed. The stability of a resistive change memory cell-that is, the tendency of the resistive change memory cell to retain its programmed resistive state-may, in certain applications, be compromised if the cell is programmed into an unstable or metastable state. In such applications, a programming method using bursts of sub-pulses within a pulse train is used to drive the resistive change cell material into a stable state during the programming operation, reducing resistance drift over time within the cell.
摘要翻译：公开了一种用于改善电阻变化单元的稳定性的方法。如果电池被编程为不稳定或亚稳状态，则电阻式变化存储单元的稳定性（即电阻式变化存储单元保持其编程电阻状态的趋势）在某些应用中可能会受到影响。在这种应用中，在编程操作期间使用脉冲串内使用脉冲串的脉冲串的编程方法来驱动电阻变化单元材料进入稳定状态，从而减少单元内随时间的电阻漂移。

49. 发明申请

WO2017164689A2 스니크 전류 제어 기반 멤리스터 소자 어레이 审中-公开
标题翻译：基于Snelike电流控制的MEMS器件阵列
公开(公告)号：WO2017164689A2
公开(公告)日：2017-09-28
申请号：PCT/KR2017/003188
申请日：2017-03-24
申请人： 제주대학교 산학협력단
发明人： 배진호 , 알리샤우카트
IPC分类号： G11C13/00 , G11C11/56 , H01L45/00
CPC分类号： G11C11/56 , G11C13/00 , H01L45/00
摘要： 본 발명은 메모리와 레지스터가 결합된 멤리스터(Memristor) 소자를 소정의 금속 화합물 층에 적층하여 전압 인가 시 다른 소자로 흐르는 스니크 전류(sneak current)에 대한 발생 제어가 가능한 특성 소자로 제작함으로써 스니크 전류의 발생을 억제 가능할 뿐만 아니라 이에 따라 데이터 리드의 오류를 지양할 수 있는 기술이다.
摘要翻译：
本发明产生用于潜行电流（潜行电流）时通过堆叠存储器和忆阻器（忆阻器）设备寄存器所施加的电压被耦合到一个给定的金属化合物层流向另一元件的控制它是一种能够防止潜行电流的产生并通过使其成为特征设备来防止数据导致的错误的技术。

50. 发明申请

WO2017161960A1 一种基于磁场触发的超晶格相变单元的逻辑门电路审中-公开
公开(公告)号：WO2017161960A1
公开(公告)日：2017-09-28
申请号：PCT/CN2017/071756
申请日：2017-01-19
申请人：华中科技大学
发明人：程晓敏 , 陆彬 , 冯金龙 , 缪向水
IPC分类号： G11C11/56 , H03K19/20 , H03K19/21
CPC分类号： G11C11/56 , H03K19/20 , H03K19/21
摘要：本发明公开了一种基于磁场触发的超晶格相变单元的逻辑门电路，包括磁场发生模块，超晶格相变模块、分压电阻以及可控开关元件；通过给超晶格相变模块施加脉冲磁场与电压脉冲来控制其阻态切换；分压电阻与超晶格相变模块连接，其连接点作为逻辑门电路的输出端；可控开关元件设于超晶格相变模块与分压电阻之间的连接线上；通过闭合可控开关元件，在超晶格相变模块施加高电压或低电压脉冲信号实现逻辑写入；通过断开可控开关元件，在逻辑门电路的输出端读取逻辑运算结果；可实现与、或、非、或非、与非、同或、异或、蕴涵、逆蕴涵、多端与、多端与非、多端或、多端或非的逻辑功能；电路结构简单，实现的逻辑功能多样，电路结构简单、功耗低、具有非易失性。

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